NT3967

NT3967 TFT LCD Source Driver Features n Output: 402 output channels n 6-bit resolution /64 gray scales n Dot inversion with polarity control n V1 ~ V10 for adjusting Gamma correction n Power for analog circuit: 6.5 ~ 10 V n Output dynamic range: 0.1 ~ AVDD-0.1V n Power consumption of analog circuit: 3 mA General Description The NT3967 is a data driver IC for a color TFT LCD panel, SVGA(800*600) and UXGA(1600*1200) applications. For better performance, dot inversion and a wide range voltage output are designed in this chip and for reducing EMI, data inversion control is used. This chip supplies 10 sections of voltage-reference for Gamma correction. n Power for interface circuit: 2.5~3.6V n Operating frequency: 65MHz n Output deviation: 10 ~ 20mV n Data inversion for reducing EMI n Cascade function with bi-direction shift control n CMOS silicon gate ( p-type substrate ) n TCP package Block diagram OUT1 OUT2 OUT3 OUT402 OUT401 Out Driver Buffer ( 402 channels ) V1 ~ V10 10 Digit to Analog Converter 6 6 6 6 6 POL REV1 D00 ~ D05 D10 ~ D15 D20 ~ D25 D30 ~ D35 D40 ~ D45 D50 ~ D55 Level Shift 6 6 6 6 6 6 Decoder 1 67 6 Decoder 18 6 6 6 6 Line Latch ( 402 X 6 bits X 2 ) 18 LD REV2 DIO1 67-bit Shift Register DIO2 Vcc GND AVDD AVSS CLK SHL Version 1.0 1 DEC 7 ,2001 NT3967 TFT LCD Source Driver NT3967 Pad configuration (Face up): This figure does not specify the TCP package. DIO2 D55 D54 D53 D52 D51 D50 D45 D44 D43 D42 D41 D40 D35 D34 D33 D32 D31 D30 Vcc SHL V10 V9 V8 V7 V6 AVDD AVSS V5 V4 V3 V2 V1 GND CLK LD POL REV1 REV2 D25 D24 D23 D22 D21 D20 D15 D14 D13 D12 D11 D10 D05 D04 D03 D02 D01 D00 DIO1 OUT402 OUT401 OUT400 OUT399 OUT398 NT3967 OUT206 Dummy 18 pads Dummy OUT205 OUT5 OUT4 OUT3 OUT2 OUT1 Version 1.0 2 DEC 7,2001 NT3967 TFT LCD Source Driver Pin Description Designation D05 ~ D00 D15 ~ D10 D25 ~ D20 D35 ~ D30 D45 ~ D40 D55 ~ D50 REV1 REV2 CLK V1 ~ V10 OUT1 ~ OUT402 SHL I/O I Description Data input. For six 6-bit data,2 pixels, of color data (R, G, B) DX5 : MSB; DX0 : LSB I I I I O I Controls whether the data of D00~D25 are inverted or not. When “REV1”=1 these data will be inverted. EX. “00” à “ 3F”, “07”à “ 38”, “15”à “2A”, and so on. Controls whether the data of D30~D55 are inverted or not, same as REV1. Clock input; latching data onto the line latches at the rising edge. Gamma correction reference voltage. Th e voltage of these pins must be AVSS< V10< V9< V8 V7 > V8 > V9 > V10 >AVSS+0.1V Version 1.0 4 DEC 7,2001 NT3967 TFT LCD Source Driver Gamma correction resistor V1, V10 Name R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 R30 R31 Resistor 800 750 700 650 600 550 550 500 500 400 400 350 350 350 300 300 300 250 250 250 200 200 200 150 150 150 150 100 100 100 100 100 Name R32 R33 R34 R35 R36 R37 R38 R39 R40 R41 R42 R43 R44 R45 R46 R47 R48 R49 R50 R51 R52 R53 R54 R55 R56 R57 R58 R59 R60 R61 R62 Resistor 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 150 150 150 200 200 250 250 300 500 800 V3, V8 1.6K 8.05K V2, V9 V4, V7 2.75K 3.45K V5, V6 V3, V8 Total impedance, Rn=R0 ~ R62, equals 15.85K Version 1.0 5 DEC 7,2001 NT3967 TFT LCD Source Driver Output Voltage VS Input Data Data Output Voltage ( Positive polarity ) 00H V1 01H V2 + ( V1 – V2) X 7250/8050 02H V2 + ( V1 – V2) X 6500/8050 03H V2 + ( V1 – V2) X 5800/8050 04H V2 + ( V1 – V2) X 5150/8050 05H V2 + ( V1 – V2) X 4550/8050 06H V2 + ( V1 – V2) X 4000/8050 07H V2 + ( V1 – V2) X 3450/8050 08H V2 + ( V1 – V2) X 2950/8050 09H V2 + ( V1 – V2) X 2450/8050 0AH V2 + ( V1 – V2) X 2050/8050 0BH V2 + ( V1 – V2) X 1650/8050 0CH V2 + ( V1 – V2) X 1300/8050 V2 + ( V1 – V2) X 950/8050 0DH V2 + ( V1 – V2) X 600/8050 0EH V2 + ( V1 – V2) X 300/8050 0FH V2 10H V3 + (V2 – V3) X2450/2750 11H V3 + (V2 – V3) X 2200/2750 12H V3 + (V2 – V3) X 1950/2750 13H V3 + (V2 – V3) X 1700/2750 14H V3 + (V2 – V3) X 1500/2750 15H V3 + (V2 – V3) X 1300/2750 16H V3 + (V2 – V3) X 1100/2750 17H V3 + (V2 – V3) X 950/2750 18H V3 + (V2 – V3) X 800/2750 19H V3 + (V2 – V3) X 650/2750 1AH V3 + (V2 – V3) X 500/2750 1BH V3 + (V2 – V3) X 400/2750 1CH V3 + (V2 – V3) X 300/2750 1DH V3 + (V2 – V3) X 200/2750 1EH V3 + (V2 – V3) X 100/2750 1FH V3 20H V4 + (V3 – V4) X 1500/1600 21H V4 + (V3 – V4) X 1400/1600 22H V4 + (V3 – V4) X 1300/1600 23H V4 + (V3 – V4) X 1200/1600 24H V4 + (V3 – V4) X 1100/1600 25H V4 + (V3 – V4) X 1000/1600 26H V4 + (V3 – V4) X 900/1600 27H V4 + (V3 – V4) X 800/1600 28H V4 + (V3 – V4) X 700/1600 29H V4 + (V3 – V4) X 600/1600 2AH V4 + (V3 – V4) X 500/1600 2BH V4 + (V3 – V4) X 400 /1600 2CH V4 + (V3 – V4) X 300/1600 2DH V4 + (V3 – V4) X 200/1600 2EH V4 + (V3 – V4) X 100/1600 2FH Version 1.0 Output Voltage ( Negative polarity ) V10 V10 + ( V9 – V10) X 800/8050 V10 + ( V9 – V10) X 1550/8050 V10 + ( V9 – V10) X 2250/8050 V10 + ( V9 – V10) X 2900/8050 V10 + ( V9 – V10) X 3500/8050 V10 + ( V9 – V10) X 4050/8050 V10 + ( V9 – V10) X 4600/8050 V10 + ( V9 – V10) X 5100/8050 V10 + ( V9 – V10) X 5600/8050 V10 + ( V9 – V10) X 6000/8050 V10 + ( V9 – V10) X 6400/8050 V10 + ( V9 – V10) X 6750/8050 V10 + ( V9 – V10) X 7100/8050 V10 + ( V9 – V10) X 7450/8050 V10 + ( V9 – V10) X 7750/8050 V9 V9 + ( V8 – V9) X 300/2750 V9 + ( V8 – V9) X 550/2750 V9 + ( V8 – V9) X 800/2750 V9 + ( V8 – V9) X 1050/2750 V9 + ( V8 – V9) X 1250/2750 V9 + ( V8 – V9) X 1450/2750 V9 + ( V8 – V9) X 1650/2750 V9 + ( V8 – V9) X 1800/2750 V9 + ( V8 – V9) X 1950/2750 V9 + ( V8 – V9) X 2100/2750 V9 + ( V8 – V9) X 2250/2750 V9 + ( V8 – V9) X 2350/2750 V9 + ( V8 – V9) X 2450/2750 V9 + ( V8 – V9) X 2550/2750 V9 + ( V8 – V9) X 2650/2750 V8 V8 + ( V7 – V8) X 100/1600 V8 + ( V7 – V8) X 200/1600 V8 + ( V7 – V8) X 300/1600 V8 + ( V7 – V8) X 400/1600 V8 + ( V7 – V8) X 500/1600 V8 + ( V7 – V8) X 600/1600 V8 + ( V7 – V8) X 700/1600 V8 + ( V7 – V8) X 800/1600 V8 + ( V7 – V8) X 900/1600 V8 + ( V7 – V8) X 1000/1600 V8 + ( V7 – V8) X 1100/1600 V8 + ( V7 – V8) X 1200/1600 V8 + ( V7 – V8) X 1300/1600 V8 + ( V7 – V8) X 1400/1600 V8 + ( V7 – V8) X 1500/1600 6 DEC 7,2001 NT3967 TFT LCD Source Driver Output Voltage VS Input Data (continued) Data 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH Output Voltage ( Positive polarity ) V4 V5 + (V4 – V5) X 3350/3450 V5 + (V4 – V5) X 3250/3450 V5 + (V4 – V5) X 3150/3450 V5 + (V4 – V5) X 3050/3450 V5 + (V4 – V5) X 2950/3450 V5 + (V4 – V5) X 2800/3450 V5 + (V4 – V5) X 2650/3450 V5 + (V4 – V5) X 2500/3450 V5 + (V4 – V5) X 2300/3450 V5 + (V4 – V5) X 2100/3450 V5 + (V4 – V5) X 1850/3450 V5 + (V4 – V5) X 1600/3450 V5 + (V4 – V5) X 1300/3450 V5 + (V4 – V5) X 800/3450 V5 Output Voltage ( Negative polarity ) V7 V7 + ( V6 – V7) X 100/3450 V7 + ( V6 – V7) X 200/3450 V7 + ( V6 – V7) X 300/3450 V7 + ( V6 – V7) X 400/3450 V7 + ( V6 – V7) X 500/3450 V7 + ( V6 – V7) X 650/3450 V7 + ( V6 – V7) X 800/3450 V7 + ( V6 – V7) X 950/3450 V7 + ( V6 – V7) X 1150/3450 V7 + ( V6 – V7) X 1350/3450 V7 + ( V6 – V7) X 1600/3450 V7 + ( V6 – V7) X 1850/3450 V7 + ( V6 – V7) X 2150/3450 V7 + ( V6 – V7) X 2650/3450 V6 Version 1.0 7 DEC 7,2001 NT3967 TFT LCD Source Driver Absolute Maximum Ratings* Digital supply voltage, Vcc -0.5V to 5V Analog supply voltage, AVDD -0.5V to +11V Supply voltage, V1~ V10 -0.3 ~AVDD+0.3 Digital input voltage -0.5V to Vcc+0.5V Output voltage, DIO1 & DIO2 -0.5V to Vcc+0.5V Output voltage,OUT1~OUT420 -0.5V to AV DD+0.5V Storage temperature -55℃ to 100℃ Operating temperature -10℃ to 75 ℃ *Comments Stresses above those listed under "Absolu te Maximum Ratings" may cause permanent damage to the device. These are stress ratings only. Functional operation of this device at these or under any other conditions above those indicated in the operational sections of this specification are not implied and exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC Electrical Characteristics (V cc =2.5~3.6V , AV DD=6.5~10V, AVSS=GND=0V, TA =-10℃~75℃) (For the digital circuit) Parameter Supply Voltage Low Level Input Voltage High Level Input Voltage High Level Output Voltage Low Level Output Voltage Input Leakage Current Digital Stand-by current Digital Operating Current Symbol Min. Vcc 2.5 Vil 0 Vih 0.7xVcc Voh Vcc-0.3V Vol Ii Ist Icc Typ. 3 Max. Unit 3.6 V 0.3xVcc V Vcc V V GND+0.3V V +1 µA 50 µA 5 mA Conditions Digital power For the digital circuit For the digital circuit DIO1/2, Ioh=500uA DIO1/2, Iol=-500uA For the digital circuit CLK is stopped, DIO1/2 No load Fclk=40 MHz, FLD=50KHz (For the analog circuit) Parameter Supply Voltage Input level of V1 ~ V5 Input level of V6 ~ V10 Voltage Output Deviation Voltage Output Offset Dynamic Range of Output Sinking Current of outputs Driving Current of outputs Impedance of Gamma Correction Analog Operating Current Symbol Min. AVDD 6.5 Vref 0.4AVDD Vref 0.1 Vvd Voc Vdr IOL IOH Ri IDD Typ. 8.4 +20 +10 +10 -180 200 Rn 3 Max. 10 AVDD-0.1 0.6AVDD +25 +20 AVDD-0.1 1.3*Rn 6 Unit V V V mV mV mV V µA µA ohm mA Conditions For the analog circuit power Gamma correction voltage Gamma correction voltage Vo=0.1V ~ 1.5V & AVDD-1.5 ~ AVDD0.1V Vo=1.5V ~ AVDD-1.5V OUT1 ~ OUT402 OUT1 ~ OUT402; Vo=0.1V V.S 1.1V OUT1 ~ OUT402; Vo=9.9V V.S 8.9V Rn=15850 ohm, from V1 ~ V5 & V6~V10 No load, Fclk=33MHz, FLD=50KHz 0.1 -150 150 0.8*Rn - Version 1.0 8 DEC 7,2001 NT3967 TFT LCD Source Driver AC Electrical Characteristics 1 (Vcc =3.0~3.6V , AVDD=6.5~10V, AVSS=GND=0V, TA = -10~75℃ ) Parameter CLK frequency CLK period cycle CLK pulse width Data set-up time Data hold time Propagation delay of DIO2/1 Time that the last data to LD Pulse width of LD Time that LD to DIO1/2 POL set-up time POL hold time Output stable time Output loading Symbol Fclk Tcph Tcw T su Thd Tphl Tld Twld Tlds Tpsu Tphd Tst CL Min. 15 6 4 2 6 1 2 2 6 6 Typ. 4.5 Max. 65 11 9 Unit Mhz ns ns ns ns ns Tcph Tcph Tcph ns ns us pF Conditions D00 ~ D55, REVx and DIO1/2 to CLK D00 ~ D55, REVx and DIO1/2 to CLK CL=25pF ( Output ) 75 POL to LD POL to LD 96% final value or below with 30mV precision , CL=75pF, R=5K ohm For OUT1 ~ OUT402 AC Electrical Characteristics 2 (Vcc =2.5~3.0V , AV DD=6.5~10V, AVSS=GND=0V, TA = -10~75℃ ) Parameter CLK frequency CLK period cycle CLK pulse width Data set-up time Data hold time Propagation delay of DIO2/1 Time that the last data to LD Pulse width of LD Time that LD to DIO1/2 POL set-up time POL hold time Output stable time Output loading Symbol Fclk Tcph Tcw T su Thd Tphl Tld Twld Tlds Tpsu Tphd Tst CL Min. 22 8 6 2 1 2 2 6 6 Typ. 4.5 Max. 45 15 9 Unit Mhz ns ns ns ns ns Tcph Tcph Tcph ns ns us pF Conditions D00 ~ D55, REVx and DIO1/2 to CLK D00 ~ D55, REVx and DIO1/2 to CLK CL=25pF ( Output ) 75 POL to LD POL to LD 96% final value or below with 30mV precision , CL=75pF, R=5K ohm For OUT1 ~ OUT402 Version 1.0 9 DEC 7,2001 NT3967 TFT LCD Source Driver Timing Diagram Tcph CLK Tsu DIO1/2 ( Input ) Tsu Data, REVx Thd Second data Tphl DIO1/2 ( Output ) Last data Tphl Thd Tcw Tcw 66 67 First data CLK Last Tld Twld Tlds LD DIO1/2 ( Input ) LD Tpsu Tpdh POL 96% Odd outputs High-Z Positive 96% High-Z Even outputs Tst High-Z Negative Tst Output load condition : Output 1K 1K 1K 1K 1K 15P 15P 15P 15P 15P Vcom Version 1.0 10 DEC 7,2001 NT3967 TFT LCD Source Driver Function operation CLK DIO1/2 ( Input ) 1CLK ( min.) 2CLK ( min.) LD 1CLK Data, REVx N-2 N-1 N 1 2 3 Last Data First Data LD POL Odd Outputs Vcom V1 ~V5 V6 ~V10 Even Outputs V1 ~V5 V6 ~V10 Version 1.0 11 DEC 7,2001