BSC050N10NS5

BSC050N10NS5 MOSFET OptiMOSTM5Power-Transistor,100V SuperSO8 8 Features •OptimizedforhighperformanceSMPS,e.g.sync.rec. •100%avalanchetested •Superiorthermalresistance •N-channel •Pb-freeleadplating;RoHScompliant •Halogen-freeaccordingtoIEC61249-2-21 •175°Crated ProductValidation: Qualifiedforindustrialapplicationsaccordingtotherelevanttestsof JEDEC47/20/22 Table1KeyPerformanceParameters 7 5 6 4 1 2 3 6 5 3 2 4 7 8 1 S1 8D S2 7D Parameter Value Unit S3 6D VDS 100 V G4 5D RDS(on),max 5.0 mΩ ID 100 A Qoss 59 nC QG(0V..10V) 49 nC Type/OrderingCode Package BSC050N10NS5 PG-TDSON-8 Final Data Sheet Marking 050N10N5 1 RelatedLinks - Rev.2.2,2019-11-14 OptiMOSTM5Power-Transistor,100V BSC050N10NS5 TableofContents Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Electrical characteristics diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Disclaimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Final Data Sheet 2 Rev.2.2,2019-11-14 OptiMOSTM5Power-Transistor,100V BSC050N10NS5 1Maximumratings atTA=25°C,unlessotherwisespecified Table2Maximumratings Parameter Symbol Continuous drain current Values Unit Note/TestCondition 100 80 16 A VGS=10V,TC=25°C VGS=10V,TC=100°C VGS=10V,TA=25°C,RthJA=50K/W1) - 400 A TC=25°C - - 155 mJ ID=50A,RGS=25Ω VGS -20 - 20 V - Power dissipation Ptot - - 136 3.0 W TC=25°C TA=25°C,RthJA=50K/W2) Operating and storage temperature Tj,Tstg -55 - 175 °C IEC climatic category; DIN IEC 68-1: 55/175/56 Unit Note/TestCondition Min. Typ. Max. ID - - Pulsed drain current2) ID,pulse - Avalanche energy, single pulse3) EAS Gate source voltage 2Thermalcharacteristics Table3Thermalcharacteristics Parameter Symbol Thermal resistance, junction - case, bottom Values Min. Typ. Max. RthJC - 0.7 1.1 K/W - Thermal resistance, junction - case, top RthJC - - 20 K/W - Device on PCB, 6 cm2 cooling area1) RthJA - - 50 K/W - 1) Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm2 (one layer, 70 µm thick) copper area for drain connection. PCB is vertical in still air. 2) See Diagram 3 for more detailed information 3) See Diagram 13 for more detailed information Final Data Sheet 3 Rev.2.2,2019-11-14 OptiMOSTM5Power-Transistor,100V BSC050N10NS5 3Electricalcharacteristics atTj=25°C,unlessotherwisespecified Table4Staticcharacteristics Parameter Symbol Drain-source breakdown voltage Values Unit Note/TestCondition - V VGS=0V,ID=1mA 3.0 3.8 V VDS=VGS,ID=72µA - 0.1 10 1 100 µA VDS=100V,VGS=0V,Tj=25°C VDS=100V,VGS=0V,Tj=125°C IGSS - 10 100 nA VGS=20V,VDS=0V Drain-source on-state resistance RDS(on) - 4.3 5.3 5.0 7.1 mΩ VGS=10V,ID=50A VGS=6V,ID=25A Gate resistance1) RG - 1.2 1.8 Ω - Transconductance gfs 50 100 - S |VDS|>2|ID|RDS(on)max,ID=50A Unit Note/TestCondition Min. Typ. Max. V(BR)DSS 100 - Gate threshold voltage VGS(th) 2.2 Zero gate voltage drain current IDSS Gate-source leakage current Table5Dynamiccharacteristics Parameter Symbol Input capacitance1) Values Min. Typ. Max. Ciss - 3300 4300 pF VGS=0V,VDS=50V,f=1MHz Coss - 490 640 pF VGS=0V,VDS=50V,f=1MHz Reverse transfer capacitance Crss - 20 35 pF VGS=0V,VDS=50V,f=1MHz Turn-on delay time td(on) - 10 - ns VDD=50V,VGS=10V,ID=50A, RG,ext=3.0Ω Rise time tr - 9 - ns VDD=50V,VGS=10V,ID=50A, RG,ext=3.0Ω Turn-off delay time td(off) - 19 - ns VDD=50V,VGS=10V,ID=50A, RG,ext=3.0Ω Fall time tf - 7 - ns VDD=50V,VGS=10V,ID=50A, RG,ext=3.0Ω Unit Note/TestCondition Output capacitance1) 1) Table6Gatechargecharacteristics2) Parameter Symbol Gate to source charge Gate charge at threshold Values Min. Typ. Max. Qgs - 16 - nC VDD=50V,ID=50A,VGS=0to10V Qg(th) - 10 - nC VDD=50V,ID=50A,VGS=0to10V Gate to drain charge Qgd - 11 16 nC VDD=50V,ID=50A,VGS=0to10V Switching charge Qsw - 16 - nC VDD=50V,ID=50A,VGS=0to10V Gate charge total Qg - 49 61 nC VDD=50V,ID=50A,VGS=0to10V Gate plateau voltage Vplateau - 4.7 - V VDD=50V,ID=50A,VGS=0to10V Gate charge total, sync. FET Qg(sync) - 43 - nC VDS=0.1V,VGS=0to10V Qoss - 59 78 nC VDD=50V,VGS=0V 1) 1) 1) Output charge 1) 2) Defined by design. Not subject to production test. See ″Gate charge waveforms″ for parameter definition Final Data Sheet 4 Rev.2.2,2019-11-14 OptiMOSTM5Power-Transistor,100V BSC050N10NS5 Table7Reversediode Parameter Symbol Diode continuous forward current Diode pulse current Diode forward voltage 1) Reverse recovery time 1) Reverse recovery charge 1) Values Unit Note/TestCondition 100 A TC=25°C - 400 A TC=25°C - 0.9 1.1 V VGS=0V,IF=50A,Tj=25°C trr - 46 92 ns VR=50V,IF=50A,diF/dt=100A/µs Qrr - 68 136 nC VR=50V,IF=50A,diF/dt=100A/µs Min. Typ. Max. IS - - IS,pulse - VSD Defined by design. Not subject to production test. Final Data Sheet 5 Rev.2.2,2019-11-14 OptiMOSTM5Power-Transistor,100V BSC050N10NS5 4Electricalcharacteristicsdiagrams Diagram1:Powerdissipation Diagram2:Draincurrent 140 120 120 100 100 80 ID[A] Ptot[W] 80 60 60 40 40 20 20 0 0 25 50 75 100 125 150 175 0 200 0 25 50 75 TC[°C] 100 125 150 175 200 TC[°C] Ptot=f(TC) ID=f(TC);VGS≥10V Diagram3:Safeoperatingarea Diagram4:Max.transientthermalimpedance 3 101 10 1 µs 102 10 µs 100 0.5 100 µs 101 ZthJC[K/W] ID[A] 1 ms 10 ms 0 10 DC 0.2 0.1 10-1 0.05 0.02 0.01 single pulse 10-2 10-1 10-2 10-1 100 101 102 103 10-3 10-6 10-5 VDS[V] 10-3 10-2 10-1 tp[s] ID=f(VDS);TC=25°C;D=0;parameter:tp Final Data Sheet 10-4 ZthJC=f(tp);parameter:D=tp/T 6 Rev.2.2,2019-11-14 OptiMOSTM5Power-Transistor,100V BSC050N10NS5 Diagram5:Typ.outputcharacteristics Diagram6:Typ.drain-sourceonresistance 400 8 5V 360 5.5 V 7 320 10 V 6V 7V 6 6V 280 7V 5 RDS(on)[mΩ] ID[A] 240 200 160 5.5 V 10 V 4 3 120 2 80 5V 1 40 0 0 1 2 3 4 0 5 0 50 100 150 VDS[V] 200 250 300 350 400 ID[A] ID=f(VDS);Tj=25°C;parameter:VGS RDS(on)=f(ID);Tj=25°C;parameter:VGS Diagram7:Typ.transfercharacteristics Diagram8:Typ.forwardtransconductance 400 160 360 320 120 280 gfs[S] ID[A] 240 200 80 160 120 40 80 40 25 °C 175 °C 0 0 2 4 6 8 0 0 VGS[V] 40 60 80 100 ID[A] ID=f(VGS);|VDS|>2|ID|RDS(on)max;parameter:Tj Final Data Sheet 20 gfs=f(ID);Tj=25°C 7 Rev.2.2,2019-11-14 OptiMOSTM5Power-Transistor,100V BSC050N10NS5 Diagram9:Drain-sourceon-stateresistance Diagram10:Typ.gatethresholdvoltage 12 4 10 720 µA 3 72 µA VGS(th)[V] RDS(on)[mΩ] 8 max 6 2 typ 4 1 2 0 -60 -20 20 60 100 140 0 -60 180 -20 20 Tj[°C] 60 100 140 180 Tj[°C] RDS(on)=f(Tj);ID=50A;VGS=10V VGS(th)=f(Tj);VGS=VDS Diagram11:Typ.capacitances Diagram12:Forwardcharacteristicsofreversediode 4 103 10 25 °C 25 °C, max 175 °C 175 °C, max Ciss Coss 102 IF[A] C[pF] 103 102 101 Crss 101 0 20 40 60 80 100 100 0.00 0.25 VDS[V] 0.75 1.00 1.25 1.50 VSD[V] C=f(VDS);VGS=0V;f=1MHz Final Data Sheet 0.50 IF=f(VSD);parameter:Tj 8 Rev.2.2,2019-11-14 OptiMOSTM5Power-Transistor,100V BSC050N10NS5 Diagram13:Avalanchecharacteristics Diagram14:Typ.gatecharge 2 10 10 9 8 25 °C 50 V 7 20 V 80 V VGS[V] IAV[A] 6 101 5 4 100 °C 3 2 150 °C 100 100 101 102 103 tAV[µs] 1 0 0 10 20 30 40 50 60 Qgate[nC] IAS=f(tAV);RGS=25Ω;parameter:Tj(start) VGS=f(Qgate);ID=50Apulsed;parameter:VDD Diagram15:Drain-sourcebreakdownvoltage Diagram Gate charge waveforms 108 106 104 VBR(DSS)[V] 102 100 98 96 94 92 -80 -40 0 40 80 120 160 200 Tj[°C] VBR(DSS)=f(Tj);ID=1mA Final Data Sheet 9 Rev.2.2,2019-11-14 OptiMOSTM5Power-Transistor,100V BSC050N10NS5 5PackageOutlines DOCUMENT NO. Z8B00003332 REVISION 07 DIMENSION A A1 b D D1 D2 E E1 E2 e L M MILLIMETERS MIN. MAX. 0.90 1.20 0.15 0.35 0.34 0.54 4.80 5.35 3.90 4.40 0.03 0.23 5.70 6.10 5.90 6.42 3.88 4.31 1.27 0.45 0.71 0.45 0.69 SCALE 10:1 0 1 2 3mm EUROPEAN PROJECTION ISSUE DATE 06.06.2019 Figure1OutlinePG-TDSON-8,dimensionsinmm Final Data Sheet 10 Rev.2.2,2019-11-14 OptiMOSTM5Power-Transistor,100V BSC050N10NS5 Dimension in mm Figure2OutlineTape(TDSON-8) Final Data Sheet 11 Rev.2.2,2019-11-14 OptiMOSTM5Power-Transistor,100V BSC050N10NS5 PG-TDSON-8: RecommenGHd BoDrdpads & Apertures 1.905 1.905 1.27 3x 0.6 1.27 3x copper Figure 3 Final Data Sheet 1.6 0.2 1.27 3x 0.825 2.863 0.5 0.925 2.863 1.27 3x 1.905 0.875 1.5 0.75 0.2 2.9 4.455 3.325 0.8 0.5 1.5 0.4 1.905 stencil apertures solder mask all dimensions in mm Outline Boardpads (TDSON-8), dimensions in mm 12 Rev.2.2,2019-11-14 OptiMOS TM 5 Power-Transistor , 100 V BSC050N10NS5 Revision History BSC050N10NS5 Revision: 2019-11-14, Rev. 2.2 Previous Revision Revision Date Subjects (major changes since last revision) 2.0 2018-05-15 Release of final version 2.1 2019-10-31 Update package drawings 2.2 2019-11-14 Update "Marking" Trademarks All referenced product or service names and trademarks are the property of their respective owners. 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The Infineon Technologies component described in this Data Sheet may be used in life-support devices or systems and/or automotive, aviation and aerospace applications or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support, automotive, aviation and aerospace device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. Final Data Sheet 13 Rev. 2.2, 2019-11-14