IR3084MPBF

IR3084 XPHASE TM DATA SHEET VR 10/11 CONTROL IC DESCRIPTION The IR3084 Control IC combined with an IR XPhaseTM Phase IC provides a full featured and flexible way to implement a complete VR10 or VR11 power solution. The “Control” IC provides overall system control and interfaces with any number of “Phase” ICs which each drive and monitor a single phase of a multiphase converter. The XPhaseTM architecture results in a power supply that is smaller, less expensive, and easier to design while providing higher efficiency than conventional approaches. FEATURES                  1 to X phase operation with matching Phase IC Supports both VR11 8-bit VID code and extended VR10 7-bit VID code 0.5% Overall System Setpoint Accuracy VID Select pin sets the DAC to either VR10 or VR11 VID Select pin selects either VR11 or legacy VR10 type startups Programmable VID offset and Load Line output impedance Programmable VID offset function at the Error Amp’s non-inverting input allowing zero offset Programmable Dynamic VID Slew Rate ±300mV Differential Remote Sense Programmable 150kHz to 1MHz oscillator Enable Input with 0.85V threshold and 100mV of hysteresis VR Ready output provides indication of proper operation and avoids false triggering Phase IC Gate Driver Bias Regulator / VRHOT Comparator Operates from 12V input with 9.9V Under-Voltage Lockout 6.9V/6mA Bias Regulator provides System Reference Voltage Programmable Hiccup Over-Current Protection with Delay to prevent false triggering Small thermally enhanced 5mm x 5mm, 28 pin MLPQ package TYPICAL APPLICATION CIRCUIT CCP1 100pF EA +5.0V RT2 R117 4.7K, B=4450 1.21K RFB1 162 RCP 2.49K VREG_12V_FILTERED CFB 10nF Q4 CJD200 VGDRIVE C204 0.1uF 18 17 EAOUT VRRDY FB RFB 324 IIN VSS_SENSE RMPOUT VBIAS RDRP 787 27 VR_RDY 15 ISHARE 19 RMP 20 VBIAS C134 0.1uF IR3084MTR 16 28 9 8 7 6 5 4 3 2 1 OUTEN VID0 VID1 VID2 VID3 VID4 VID5 VID6 VID7 VID_SEL VDRP REGDRV ENABLE VID0 VID1 VID2 VID3 VID4 VID5 VID6 VID7 VIDSEL REGFB REGSET 21 C130 0.1uF 26 VCC VDAC SS/DEL ROSC CSS/DEL 0.1uF VOSNS-- LGND C135 1uF C89 100pF 24 23 25 RVSETPT 124 VSETPT OCSET VREG_12V_FILTERED R30 10 R1331 1 R137 2K VCC_SENSE C1009 100pF CCP 56nF RVGDRV 97.6K CVGDRV 10nF 14 13 ROCSET 15.8K 12 11 VDAC ROSC 30.1K RVDAC 3.5 CVDAC 33nF 22 10 Page 1 of 45 03/4/2009 IR3084 ORDERING INFORAMATION DEVICE IR3084MTRPBF IR3084MPBF ORDER QUANTITY 3000 Tape and Reel 100 Piece Strip ABSOLUTE MAXIMUM RATINGS Operating Junction Temperature……………..0 to 150oC Storage Temperature Range………………….−65oC to 150oC ESD Rating………………………………………HBM Class 1B JEDEC standard Moisture Sensitivity Level………………………JEDEC Level 3 @ 260 oC PIN # 1 2−9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Page 2 of 45 PIN NAME VIDSEL VID7−0 VOSNS− ROSC VDAC OCSET VSETPT IIN VDRP FB EAOUT RMPOUT VBIAS VCC LGND REGFB REGDRV REGSET SS/DEL VRRDY ENABLE VMAX 20V 20V 0.5V 20V 20V 20V 20V 20V 20V 20V 10V 20V 20V 20V n/a 20V 20V 20V 20V 20V 20V VMIN −0.3V −0.3V −0.5V −0.5V −0.3V −0.3V −0.3V −0.3V −0.3V −0.3V −0.3V −0.3V −0.3V −0.3V n/a −0.3V −0.3V −0.3V −0.3V −0.3V −0.3V ISOURCE 1mA 1mA 10mA 1mA 1mA 1mA 1mA 1mA 5mA 1mA 20mA 5mA 50mA 1mA 50mA 1mA 10mA 1mA 1mA 1mA 1mA ISINK 1mA 1mA 10mA 1mA 1mA 1mA 1mA 1mA 5mA 1mA 20mA 5mA 10mA 50mA 1mA 1mA 50mA 1mA 1mA 20mA 1mA 03/4/2009 IR3084 ELECTRICAL SPECIFICATIONS Unless otherwise specified, these specifications apply over: 9.5V ≤ VCC ≤ 16V, −0.3V ≤ VOSNS− ≤ 0.3V, 0 oC ≤ TJ ≤ 100 oC, ROSC = 24kΩ, CSS/DEL = 0.1F ±10% PARAMETER TEST CONDITION MIN TYP MAX UNIT −0.5 0.5 % VDAC REFERENCE System Set-Point Accuracy VID ≥ 1V, 10kΩ≤ROSC≤100kΩ, 25 oC ≤ TJ ≤ 100 oC (Deviation from Tables 1 & 2 per test circuit in Figure 1 which emulates in-VR operation) 0.8V ≤ VID < 1V, 10kΩ≤ROSC≤100kΩ, 25 oC ≤ TJ ≤ 100 oC −5 +5 mV 0.5V≤VID 0.85V, V(EAOUT) > 0.5V −2.0 −0.2 1.0 A V(SS/DEL) < 0.35V 5.6 12.5 19.4 KΩ V(EAOUT) 0.20 0.35 0.50 V V(SS/DEL) 0.35 0.60 0.85 V −5mA ≤ I(VBIAS) ≤ 0mA 6.6 −35 6.9 −20 7.2 −6 V mA −10 −53.5 −1 −51 10 −48.5 mV A 1.2 0.8 0.2 0.5 150 1.8 1.6 1.0 1.3 250 2.6 2.8 2.5 2.2 350 ms ms ms ms µs 0.85 1.3 1.5 V 40 4 70 6.5 100 9 A A 9.5 11.2 12.5 A/A 20 3.6 40 3.85 60 4.1 A V CURRENT SENSE INPUT IIN Bias Current IIN Preconditioning Pull-Down Resistance IIN Preconditioning RESET Threshold IIN Preconditioning SET Threshold VBIAS REGULATOR Output Voltage Current Limit Over-Current Comparator Input Offset Voltage OCSET Bias Current 1V ≤ V(OCSET) ≤ 5V SOFT START AND DELAY Start Delay (TD1) Soft Start Time (TD2) VID Sample Delay (TD3) VRRDY Delay (TD4 + TD5) OC Delay Time SS/DEL to FB Input Offset Voltage SS/DEL Charge Current SS/DEL Discharge Current Charge/Discharge Current Ratio OC Discharge Current Charge Voltage OC/VRRDY Delay Comparator Threshold OC/VRRDY Delay Comparator Threshold Delay Comparator Hysteresis VID Sample Delay Comparator Threshold SS/DEL Discharge Comparator Threshold RDRP = ∞ RDRP = ∞ Note 1 With FB = 0V, adjust V(SS/DEL) until EAOUT drives high Note 1 Relative to Charge Voltage, SS/DEL rising Relative to Charge Voltage, SS/DEL falling 80 mV 100 mV 20 mV 3.10 V 215 mV ENABLE INPUT Threshold Voltage Threshold Voltage Threshold Hysteresis Input Resistance Blanking Time Page 4 of 45 ENABLE rising ENABLE falling Noise Pulse < 250ns will not register an ENABLE state change. Note 1 775 675 60 50 850 750 100 100 925 825 140 200 mV mV mV KΩ 75 250 400 ns 03/4/2009 IR3084 PARAMETER TEST CONDITION MIN TYP MAX UNIT 150 0 300 10 mV A 450 500 550 kHz 70 72 74 % 10 13 15 % −112 −99 −85 A −12 0 12 mV 10 20 50 mA 0.4 0.87 1.33 V 9.3 8.5 575 9.9 9.1 800 10.3 9.5 1000 V V mV 9 14 18 mA −1.45 −1.3 −0.75 mA VRRDY OUTPUT Output Voltage Leakage Current I(VRRDY) = 4mA V(VRRDY) = 5.5V OSCILLATOR Switching Frequency Peak Voltage (4.8V typical, measured as % of VBIAS) Valley Voltage (0.9V typical, measured as % of VBIAS) DRIVER BIAS REGULATOR REGSET Bias Current 1.5V ≤ V(REGSET) ≤ VCC – 1.5V 1.5V ≤ V(REGSET) ≤ VCC – 1.5V, 100A ≤ I(REGDRV) ≤ 10mA V(REGDRV) = 0V, 1.5V ≤ V(REGSET) ≤ VCC – 1.5V, Note 1 I(REGDRV) = 10mA, Note 1 Input Offset Voltage Short Circuit Current Dropout Voltage VCC UNDER−VOLTAGE LOCKOUT Start Threshold Stop Threshold Hysteresis Start – Stop GENERAL VCC Supply Current −0.3V ≤ VOSNS− ≤ 0.3V, All VID Codes VOSNS− Current Note 1: Guaranteed by design but not tested in production Note 2: VDAC Output is trimmed to compensate for Error Amp input offsets errors EAOUT + IR3084 200 OHM ERROR AMP FB 200 OHM VSETPT + + VDAC ISINK - IOFFSET IROSC CURRENT SOURCE GENERATOR ROSC BUFFER AMP IROSC IOCSET RVDAC SYSTEM SET POINT VOLTAGE CVDAC - VDAC BUFFER AMP + - OCSET ISOURCE "FAST" VDAC ROSC + ROSC 1.2V VOSNS- Figure 1 – System Set Point Test Circuit Page 5 of 45 03/4/2009 IR3084 PIN DESCRIPTIONS PIN# PIN SYMBOL 1 VIDSEL 2−9 10 VID7−0 VOSNS− 11 ROSC 12 VDAC 13 OCSET 14 VSETPT 15 IIN 16 VDRP 17 18 19 FB EAOUT RMPOUT 20 VBIAS 21 22 VCC LGND 23 REGFB 24 REGDRV 25 REGSET 26 SS/DEL 27 VRRDY 28 ENABLE Page 6 of 45 DESCRIPTION Selects the DAC table and the type of Soft Start. There are 4 possible modes of operation: (1) GND selects VR10 DAC and VR11 type startup, (2) FLOAT (1.25V) selects VR11 DAC and VR11 type startup, (3) VBIAS (6.9V) selects VR11 DAC and legacy VR10 type startup, (4) VCC (12V) selects VR10 DAC and legacy VR10 type startup. Additional details are provided in the Theory of Operation section. Inputs to the D to A Converter. Must be connected to an external pull-up resistor. Remote Sense Input. Connect to ground at the Load. Connect a resistor to VOSNS− to program oscillator frequency and OCSET, VSETPT, REGSET, and VDAC bias currents Regulated voltage programmed by the VID inputs. Connect an external RC network to VOSNS− to program Dynamic VID slew rate and provide compensation for the internal Buffer Amplifier. Programs the hiccup over-current threshold through an external resistor tied to VDAC and an internal current source. Over-current protection can be disabled by connecting a resistor from this pin to VDAC to program the threshold higher than the possible signal into the IIN pin from the Phase ICs but no greater than 5V (do not float this pin as improper operation will occur). Error Amp non-inverting input. Converter output voltage can be decreased from the VDAC (VID) voltage with an external resistor connected to VDAC and an internal current sink. Current sensing and PWM operation are referenced to this pin. Current Sense input from the Phase ICs. Prior to startup, SS/DEL0.6V and EAOUT>0.35V, this pin is released and current balancing is enabled. If current feedback from the Phase ICs is not required for implementing droop or over-current protection connect this pin to LGND. To ensure proper operation do not float this pin. Buffered IIN signal. Connect an external RC network to FB to program converter output impedance Inverting input to the Error Amplifier. Output of the Error Amplifier. When Low, provides UVL function to the Phase ICs. Oscillator Output voltage. Used by Phase ICs to program Phase Delay 6.9V/6mA Regulated output used as a system reference voltage for internal circuitry and the Phase ICs. Power Input for internal circuitry Local Ground for internal circuitry and IC substrate connection Inverting input of the Bias Regulator Error Amp. Connect to the out put of the Phase IC Gate Driver Bias Regulator. Output of the Bias Regulator Error Amp. Non-inverting input of the Bias Regulator Error Amp. Output Voltage of the Phase IC Gate Driver Bias Regulator is set by an internal current source flowing into an external resistor connected between this pin and ground. Controls Converter Start-up and Over-Current Timing. Connect an external capacitor to LGND to program. Open Collector output that drives low during Start-Up and any external fault condition. Connect external pull-up. Enable Input. A logic low applied to this pin puts the IC into Fault mode. This pin has a 100K pull-down resistor to GND. 03/4/2009 IR3084 SYSTEM THEORY OF OPERATION XPhaseTM Architecture The XPhaseTM architecture is designed for multiphase interleaved buck converters which are used in applications requiring small size, design flexibility, low voltage, high current and fast transient response. The architecture can be used in any multiphase converter ranging from 1 to 16 or more phases where flexibility facilitates the design trade−off of multiphase converters. The scalable architecture can be applied to other applications which require high current or multiple output voltages. As shown in Figure 2, the XPhaseTM architecture consists of a Control IC and a scalable array of phase converters each using a single Phase IC. The Control IC communicates with the Phase ICs through a 5−wire analog bus, i.e. bias voltage, phase timing, average current, error amplifier output, and VID voltage. The Control IC incorporates all the system functions, i.e. VID, PWM ramp oscillator, error amplifier, bias voltage, and fault protections etc. The Phase IC implements the functions required by the converter of each phase, i.e. the gate drivers, PWM comparator and latch, over−voltage protection, and current sensing and sharing. There is no unused or redundant silicon with the XPhaseTM architecture compared to others such as a 4 phase controller that can be configured for 2, 3, or 4 phase operation. PCB Layout is easier since the 5 wire bus eliminates the need for point−to−point wiring between the Control IC and each Phase. The critical gate drive and current sense connections are short and local to the Phase ICs. This improves the PCB layout by lowering the parasitic inductance of the gate drive circuits and reducing the noise of the current sense signal. VR READY PHASE FAULT VR HOT VR FAN 12V ENABLE VIDSEL VID7 VID6 VID5 PHASE FAULT IR3084 CONTROL IC CIN >> PHASE TIMING VID4 > PWM CONTROL VID2 VOUT SENSE+ >> BIAS VOLTAGE CURRENT SHARE >> VID VOLTAGE VOUT+ IR3086 PHASE IC COUT VOUT- VID1 VID0 CCS RCS CCS RCS VOUT SENSE- PHASE FAULT CURRENT SHARE IR3086 PHASE IC ADDITIONAL PHASES CONTROL BUS INPUT/OUTPUT Figure 2 – System Block Diagram Page 7 of 45 03/4/2009 IR3084 PWM Control Method The PWM block diagram of the XPhaseTM architecture is shown in Figure 3. Feed−forward voltage mode control with trailing edge modulation is used. A high−gain wide−bandwidth voltage type error amplifier in the Control IC is used for the voltage control loop. An external RC circuit connected to the input voltage and ground is used to program the slope of the PWM ramp and to provide the feed−forward control at each phase. The PWM ramp slope will change with the input voltage and automatically compensate for changes in the input voltage. The input voltage can change due to variations in the silver box output voltage or due to drops in the PCB related to changes in load current. VIN CONTROL IC PHASE IC SYSTEM REFERENCE VOLTAGE BIASIN RAMP GENERATOR VPEAK RMPOUT RAMPIN+ RRAMP1 VVALLEY RAMPIN- - VOUT COUT R GATEL + GND RPWMRMP RVSETPT ENABLE RAMP SLOPE ADJUST - + EAIN PWMRMP VDAC VSETPT 200 OHM VOSNS+ RESET DOMINANT RRAMP2 VOSNS- - PWM COMPARATOR + VDAC VBIAS REGULATOR GATEH S - VBIAS + PWM LATCH CLOCK PULSE GENERATOR + 50% DUTY CYCLE VOSNS- - SCOMP O% DUTY CYCLE COMPARATOR + RAMP DISCHARGE CLAMP CPWMRMP X 0.91 + ISHARE 10K - FB CURRENT SENSE AMP 20mV - X34 IOFFSET CSIN+ + + + RVFB - SHARE ADJUST ERROR AMP CSCOMP - EAOUT ERROR AMP CCS RCS CCS RCS CSIN- RDRP IROSC VDRP AMP DACIN VDRP + - IIN PHASE IC SYSTEM REFERENCE VOLTAGE BIASIN RAMPIN+ PWM LATCH CLOCK PULSE GENERATOR + RRAMP1 - RAMPIN- GATEH S PWM COMPARATOR - EAIN RESET DOMINANT R GATEL + RRAMP2 RAMP SLOPE ADJUST - RPWMRMP ENABLE + PWMRMP - SCOMP O% DUTY CYCLE COMPARATOR + RAMP DISCHARGE CLAMP CPWMRMP X 0.91 - + ISHARE 20mV 10K - CURRENT SENSE AMP X34 - + SHARE ADJUST ERROR AMP CSIN+ + CSCOMP CSIN- DACIN Figure 3 – IR3084 PWM Block Diagram Frequency and Phase Timing Control The oscillator is located in the Control IC and its frequency is programmable from 150kHz to 1MHZ by an external resistor. The output of the oscillator is a 50% duty cycle triangle waveform with peak and valley voltages of approximately 4.8V and 0.9V. This signal is used to program both the switching frequency and phase timing of the Phase ICs. The Phase IC is programmed by resistor divider RRAMP1 and RRAMP2 connected between the VBIAS reference voltage and the Phase IC LGND pin. A comparator in the Phase ICs detects the crossing of the oscillator waveform with the voltage generated by the resistor divider and triggers a clock pulse that starts the PWM cycle. The peak and valley voltages track the VBIAS voltage reducing potential Phase IC timing errors. Figure 4 shows the Phase timing for an 8 phase converter. Note that both slopes of the triangle waveform can be used for synchronization by swapping the RAMP + and – pins. Page 8 of 45 03/4/2009 IR3084 50% RAMP DUTY CYCLE RAMP (FROM CONTROL IC) SLOPE = 80mV / % DC VPEAK (5.0V) VPHASE4&5 (4.5V) SLOPE = 1.6mV / ns @ 200kHz SLOPE = 8.0mV / ns @ 1MHz VPHASE3&6 (3.5V) VPHASE2&7 (2.5V) VPHASE1&8 (1.5V) VVALLEY (1.00V) CLK1 PHASE IC CLOCK PULSES CLK2 CLK3 CLK4 CLK5 CLK6 CLK7 CLK8 Figure 4 – 8 Phase Oscillator Waveforms PWM Operation The PWM comparator is located in the Phase IC. Upon receiving a clock pulse, the PWM latch is set, the PWMRMP voltage begins to increase, the low side driver is turned off, and the high side driver is then turned on. When the PWMRMP voltage exceeds the Error Amp’s output voltage the PWM latch is reset. This turns off the high side driver, turns on the low side driver, and activates the Ramp Discharge Clamp. The clamp quickly discharges the PWMRMP capacitor to the VDAC voltage of the Control IC until the next clock pulse. The PWM latch is reset dominant allowing all phases to go to zero duty cycle within a few tens of nanoseconds in response to a load step decrease. Phases can overlap and go to 100% duty cycle in response to a load step increase with turn-on gated by the clock pulses. An Error Amp output voltage greater than the common mode input range of the PWM comparator results in 100% duty cycle regardless of the voltage of the PWM ramp. This arrangement guarantees the Error Amp is always in control and can demand 0 to 100% duty cycle as required. It also favors response to a load step decrease which is appropriate given the low output to input voltage ratio of most systems. The inductor current will increase much more rapidly than decrease in response to load transients. This control method is designed to provide “single cycle transient response” where the inductor current changes in response to load transients within a single switching cycle maximizing the effectiveness of the power train and minimizing the output capacitor requirements. An additional advantage is that differences in ground or input voltage at the phases have no effect on operation since the PWM ramps are referenced to VDAC. Page 9 of 45 03/4/2009 IR3084 Body BrakingTM In a conventional synchronous buck converter, the minimum time required to reduce the current in the inductor in response to a load step decrease is; TSLEW = [L x (IMAX − IMIN)] / Vout The slew rate of the inductor current can be significantly increased by turning off the synchronous rectifier in response to a load step decrease. The switch node voltage is then forced to decrease until conduction of the synchronous rectifier’s body diode occurs. This increases the voltage across the inductor from Vout to Vout + VBODY DIODE. The minimum time required to reduce the current in the inductor in response to a load transient decrease is now; TSLEW = [L x (IMAX − IMIN)] / (Vout + VBODY DIODE) Since the voltage drop in the body diode is often higher than output voltage, the inductor current slew rate can be increased by 2X or more. This patent pending technique is referred to as “body braking” and is accomplished through the “0% Duty Cycle Comparator” located in the Phase IC. If the Error Amp’s output voltage drops below 91% of the VDAC voltage this comparator turns off the low side gate driver. Figure 5 depicts PWM operating waveforms under various conditions PHASE IC CLOCK PULSE EAIN PWMRMP VDAC Body-Braking Threshold GATEH GATEL STEADY-STATE OPERATION DUTY CYCLE INCREASE DUE TO LOAD INCREASE DUTY CYCLE DECREASE DUE TO VIN INCREASE (FEED-FORWARD) DUTY CYCLE DECREASE DUE TO LOAD DECREASE (BODY BRAKING) OR FAULT (VCC UV, VCCVID UV, OCP, VID=11111X) STEADY-STATE OPERATION Figure 5 – PWM Operating Waveforms Lossless Average Inductor Current Sensing Inductor current can be sensed by connecting a series resistor and a capacitor network in parallel with the inductor and measuring the voltage across the capacitor. The equation of the sensing network is, vC ( s )  v L ( s ) R  sL 1  iL (s) L 1  sRS C S 1  sRS C S Usually the resistor Rcs and capacitor Ccs are chosen so that the time constant of Rcs and Ccs equals the time constant of the inductor which is the inductance L over the inductor DCR. If the two time constants match, the voltage across Ccs is proportional to the current through L, and the sense circuit can be treated as if only a sense resistor with the value of RL was used. The mismatch of the time constants does not affect the measurement of inductor DC current, but affects the AC component of the inductor current. Page 10 of 45 03/4/2009 IR3084 The advantage of sensing the inductor current versus high side or low side sensing is that actual output current being delivered to the load is obtained rather than peak or sampled information about the switch currents. The output voltage can be positioned to meet a load line based on real time information. Except for a sense resistor in series with the inductor, this is the only sense method that can support a single cycle transient response. Other methods provide no information during either load increase (low side sensing) or load decrease (high side sensing). An additional problem associated with peak or valley current mode control for voltage positioning is that they suffer from peak−to−average errors. These errors will show in many ways but one example is the effect of frequency variation. If the frequency of a particular unit is 10% low, the peak to peak inductor current will be 10% larger and the output impedance of the converter will drop by about 10%. Variations in inductance, current sense amplifier bandwidth, PWM prop delay, any added slope compensation, input voltage, and output voltage are all additional sources of peak−to−average errors. Current Sense Amplifier A high speed differential current sense amplifier is located in the Phase IC, as shown in Figure 6. Its gain decreases with increasing temperature and is nominally 34 at 25ºC and 29 at 125ºC (−1470 ppm/ºC). This reduction of gain tends to compensate the 3850 ppm/ºC increase in inductor DCR. Since in most designs the Phase IC junction is hotter than the inductor these two effects tend to cancel such that no additional temperature compensation of the load line is required. The current sense amplifier can accept positive differential input up to 100mV and negative up to −20mV before clipping. The output of the current sense amplifier is summed with the DAC voltage and sent to the Control IC and other Phases through an on-chip 10KΩ resistor connected to the ISHARE pin. The ISHARE pins of all the phases are tied together and the voltage on the share bus represents the average inductor current through all the inductors and is used by the Control IC for voltage positioning and current limit protection. vL iL CSA L RL Rs Cs Vo Co vc CO Figure 6 – Inductor Current Sensing and Current Sense Amplifier Average Current Share Loop Current sharing between phases of the converter is achieved by the average current share loop in each Phase IC. The output of the current sense amplifier is compared with the share bus less a nominal 20mV offset. If current in a phase is smaller than the average current, the share adjust amplifier of the phase will activate a current source that reduces the slope of its PWM ramp thereby increasing its duty cycle and output current. The crossover frequency of the current share loop can be programmed with a capacitor at the SCOMP pin so that the share loop does not interact with the output voltage loop. Page 11 of 45 03/4/2009 IR3084 IR3084 THEORY OF OPERATION Block Diagram VRRDY UVLO DISABLE OVER CURRENT NO CPU + - + ENABLE COMPARATOR - 250ns BLANKING ENABLE - FAULT LATCH SET DOMINANT - + + 80mV 100mV VCHG 3.85V - STARTUP R NO CPU FAULT LATCH - OC COMPARATOR I_OC_DISCHG 40uA R IIN PRECONDITION LATCH VDRP VDRP AMP + - ON - EAOUT + 100k + 12.5K S 0.35V S - + 0.6V SS/DEL OC DELAY COMPARATOR + 850mV 750mV R NO CPU LATCHED SS DISCHARGE COMPARATOR IIN + - - FAULT S SET DOMINANT 0.215V VCC UVLO COMPARATOR SET DOMINANT + + 9.9V 9.1V - - + VCC OCSET SS/DEL DISCHARGE LGND STARTUP VID SAMPLE DELAY COMPARATOR OFF ICHG 70uA 3.1V - SS/DEL SET DOMINANT S ON IDISCHG 6.5uA START LATCH R + VID4 VID1 IROSC "FAST" VDAC IROSC 3.5V + + - IROSC - IROSC - 1.1V 1.1V 1.1V 1.25V - + SOFTSTART CLAMP IOCSET IROSC ENABLE 1.1V BOOT + IROSC 0.6V VID0 + - - + VID2 7.5V IROSC + VID3 DISABLE EAOUT ERROR AMP FB - VID5 1.3V + VID6 VID FAULT CODE DIGITAL TO IROSC ANALOG IROSC CONVERTER IROSC 1.3us BLANKING + + VID INPUT COMPARATORS (1 of 8 shown) VID7 IROSC 0.62V VSETPT IROSC IOFFSET VDAC ISOURCE + ISINK SET VR10 DAC IVOSNS1.3mA 12.5K VDAC BUFFER AMP SET VR11 DAC SET VID = 1.1V BOOT VIDSEL VOSNS- - 1.24V VBIAS REGULATOR + 6.9V IROSC CURRENT SOURCE GENERATOR ROSC BUFFER AMP BIAS REGULATOR ERROR AMP VCC IROSC REGDRV REGFB IREGSET - 0.9V + RMPOUT VBIAS 4.8V - 50% DUTY CYCLE + RAMP GENERATOR + - VBIAS REGSET ROSC Figure 7 – IR3084 Block Diagram VID Control An 8−bit VID voltage compatible with VR 10 (see Table 1) and VR11 (see Table 2) is available at the VDAC pin. The VIDSEL pin configures the DAC for VR10 if grounded or connected to VCC (12V) and for VR11 if floated or connected to VBIAS (6.9V). The VIDSEL pin is internally pulled−up to 1.25V through a 12.5Kohm resistor. The VID pins require an external bias voltage and should not be floated. The VID input comparators, with 0.6V threshold, monitor the VID pins and control the 8 bit Digital−to−Analog Converter (DAC) whose output is sent to the VDAC buffer amplifier. The output of the buffer amp is the VDAC pin. The VDAC voltage is post-package trimmed to compensate for the input offsets of the Error Amp to provide a 0.5% system accuracy. The actual VDAC voltage does not represent the system set point and has a wider tolerance. Page 12 of 45 03/4/2009 IR3084 VID4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID3 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 VID2 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 VID1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 VID0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 VID5 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 VID6 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Voltage 1.60000 1.59375 1.58750 1.58125 1.57500 1.56875 1.56250 1.55625 1.55000 1.54375 1.53750 1.53125 1.52500 1.51875 1.51250 1.50625 1.50000 1.49375 1.48750 1.48125 1.47500 1.46875 1.46250 1.45625 1.45000 1.44375 1.43750 1.43125 1.42500 1.41875 1.41250 1.40625 1.40000 1.39375 1.38750 1.38125 1.37500 1.36875 1.36250 1.35625 1.35000 1.34375 1.33750 1.33125 1.32500 1.31875 1.31250 1.30625 1.30000 1.29375 1.28750 1.28125 1.27500 1.26875 1.26250 1.25625 1.25000 1.24375 1.23750 1.23125 1.22500 1.21875 1.21250 1.20625 VID4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID3 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 VID2 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 VID1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 VID0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 VID5 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 VID6 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Voltage 1.20000 1.19375 1.18750 1.18125 1.17500 1.16875 1.16250 1.15625 1.15000 1.14375 1.13750 1.13125 1.12500 1.11875 1.11250 1.10625 1.10000 1.09375 FAULT FAULT FAULT FAULT 1.08750 1.08125 1.07500 1.06875 1.06250 1.05625 1.05000 1.04375 1.03750 1.03125 1.02500 1.01875 1.01250 1.00625 1.00000 0.99375 0.98750 0.98125 0.97500 0.96875 0.96250 0.95625 0.95000 0.94375 0.93750 0.93125 0.92500 0.91875 0.91250 0.90625 0.90000 0.89375 0.88750 0.88125 0.87500 0.86875 0.86250 0.85625 0.85000 0.84375 0.83750 0.83125 Table 1 – VR10 VID Table with 6.25mV extension Page 13 of 45 03/4/2009 IR3084 Hex (VID7:VID0) 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F Dec (VID7:VID0) 00000000 00000001 00000010 00000011 00000100 00000101 00000110 00000111 00001000 00001001 00001010 00001011 00001100 00001101 00001110 00001111 00010000 00010001 00010010 00010011 00010100 00010101 00010110 00010111 00011000 00011001 00011010 00011011 00011100 00011101 00011110 00011111 00100000 00100001 00100010 00100011 00100100 00100101 00100110 00100111 00101000 00101001 00101010 00101011 00101100 00101101 00101110 00101111 00110000 00110001 00110010 00110011 00110100 00110101 00110110 00110111 00111000 00111001 00111010 00111011 00111100 00111101 00111110 00111111 Voltage Fault Fault 1.60000 1.59375 1.58750 1.58125 1.57500 1.56875 1.56250 1.55625 1.55000 1.54375 1.53750 1.53125 1.52500 1.51875 1.51250 1.50625 1.50000 1.49375 1.48750 1.48125 1.47500 1.46875 1.46250 1.45625 1.45000 1.44375 1.43750 1.43125 1.42500 1.41875 1.41250 1.40625 1.40000 1.39375 1.38750 1.38125 1.37500 1.36875 1.36250 1.35625 1.35000 1.34375 1.33750 1.33125 1.32500 1.31875 1.31250 1.30625 1.30000 1.29375 1.28750 1.28125 1.27500 1.26875 1.26250 1.25625 1.25000 1.24375 1.23750 1.23125 1.22500 1.21875 Hex (VID7:VID0) 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F Dec (VID7:VID0) 01000000 01000001 01000010 01000011 01000100 01000101 01000110 01000111 01001000 01001001 01001010 01001011 01001100 01001101 01001110 01001111 01010000 01010001 01010010 01010011 01010100 01010101 01010110 01010111 01011000 01011001 01011010 01011011 01011100 01011101 01011110 01011111 01100000 01100001 01100010 01100011 01100100 01100101 01100110 01100111 01101000 01101001 01101010 01101011 01101100 01101101 01101110 01101111 01110000 01110001 01110010 01110011 01110100 01110101 01110110 01110111 01111000 01111001 01111010 01111011 01111100 01111101 01111110 01111111 Voltage 1.21250 1.20625 1.20000 1.19375 1.18750 1.18125 1.17500 1.16875 1.16250 1.15625 1.15000 1.14375 1.13750 1.13125 1.12500 1.11875 1.11250 1.10625 1.10000 1.09375 1.08750 1.08125 1.07500 1.06875 1.06250 1.05625 1.05000 1.04375 1.03750 1.03125 1.02500 1.01875 1.01250 1.00625 1.00000 0.99375 0.98750 0.98125 0.97500 0.96875 0.96250 0.95625 0.95000 0.94375 0.93750 0.93125 0.92500 0.91875 0.91250 0.90625 0.90000 0.89375 0.88750 0.88125 0.87500 0.86875 0.86250 0.85625 0.85000 0.84375 0.83750 0.83125 0.82500 0.81875 Table 2 – VR11 VID Table (Part 1) Page 14 of 45 03/4/2009 IR3084 Hex (VID7:VID0) 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF Dec (VID7:VID0) 10000000 10000001 10000010 10000011 10000100 10000101 10000110 10000111 10001000 10001001 10001010 10001011 10001100 10001101 10001110 10001111 10010000 10010001 10010010 10010011 10010100 10010101 10010110 10010111 10011000 10011001 10011010 10011011 10011100 10011101 10011110 10011111 10100000 10100001 10100010 10100011 10100100 10100101 10100110 10100111 10101000 10101001 10101010 10101011 10101100 10101101 10101110 10101111 10110000 10110001 10110010 10110011 10110100 10110101 10110110 10110111 10111000 10111001 10111010 10111011 10111100 10111101 10111110 10111111 Voltage 0.81250 0.80625 0.80000 0.79375 0.78750 0.78125 0.77500 0.76875 0.76250 0.75625 0.75000 0.74375 0.73750 0.73125 0.72500 0.71875 0.71250 0.70625 0.70000 0.69375 0.68750 0.68125 0.67500 0.66875 0.66250 0.65625 0.65000 0.64375 0.63750 0.63125 0.62500 0.61875 0.61250 0.60625 0.60000 0.59375 0.58750 0.58125 0.57500 0.56875 0.56250 0.55625 0.55000 0.54375 0.53750 0.53125 0.52500 0.51875 0.51250 0.50625 0.50000 0.49375 0.48750 0.48125 0.47500 0.46875 0.46250 0.45625 0.45000 0.44375 0.43750 0.43125 0.42500 0.41875 Hex (VID7:VID0) C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF Dec (VID7:VID0) 11000000 11000001 11000010 11000011 11000100 11000101 11000110 11000111 11001000 11001001 11001010 11001011 11001100 11001101 11001110 11001111 11010000 11010001 11010010 11010011 11010100 11010101 11010110 11010111 11011000 11011001 11011010 11011011 11011100 11011101 11011110 11011111 11100000 11100001 11100010 11100011 11100100 11100101 11100110 11100111 11101000 11101001 11101010 11101011 11101100 11101101 11101110 11101111 11110000 11110001 11110010 11110011 11110100 11110101 11110110 11110111 11111000 11111001 11111010 11111011 11111100 11111101 11111110 11111111 Voltage 0.41250 0.40625 0.40000 0.39375 0.38750 0.38125 0.37500 0.36875 0.36250 0.35625 0.35000 0.34375 0.33750 0.33125 0.32500 0.31875 0.31250 0.30625 0.30000 0.29375 0.28750 0.28125 0.27500 0.26875 0.26250 0.25625 0.25000 0.24375 0.23750 0.23125 0.22500 0.21875 0.21250 0.20625 0.20000 0.19375 0.18750 0.18125 0.17500 0.16875 0.16250 0.15625 0.15000 0.14375 0.13750 0.13125 0.12500 0.11875 0.11250 0.10625 0.10000 0.10000 0.10000 0.10000 0.10000 0.10000 0.10000 0.10000 0.10000 0.10000 0.10000 0.10000 FAULT FAULT Table 2 – VR11 VID Table (Part 2) Page 15 of 45 03/4/2009 IR3084 The IR3084 can accept changes in the VID code while operating and vary the DAC voltage accordingly. The sink/source capability of the VDAC buffer amp is programmed by the same external resistor that sets the oscillator frequency. The slew rate of the voltage at the VDAC pin can be adjusted by an external capacitor between VDAC pin and the VOSNS− pin. A resistor connected in series with this capacitor is required to compensate the VDAC buffer amplifier. Digital VID transitions result in a smooth analog transition of the VDAC voltage and converter output voltage minimizing inrush currents in the input and output capacitors and overshoot of the output voltage. Adaptive Voltage Positioning Adaptive Voltage Positioning (AVP) is needed to reduce the output voltage deviations during load transients and the power dissipation of the load when it is drawing high current. The circuitry related to the voltage positioning is shown in Figure 8. Resistor RSETPT is connected between the VDAC pin and VSETPT pin to set the desired amount of fixed offset voltage below the DAC voltage. The VSETPT is internally connected to the non−inverting input of the voltage error amplifier and an internal current source IOFFSET, whose value is programmed by the same external resistor that programs the oscillator frequency. The voltage drop across RSETPT caused by IOFFSET sets the no-load l offset voltage below the nominal DAC setting. The voltage at the VDRP pin is a buffered version of the share bus and represents the sum of the DAC voltage and the average inductor current of all the phases. The VDRP pin is connected to the FB pin through the resistor RDRP. Since the Error Amp will force the loop to maintain FB to be equal to the VSETPT reference voltage, a current will flow into the FB pin equal to (VDRP−VSETPT) / RDRP. When the load current increases, the VDRP voltage increases accordingly. More current flows through the feedback resistor RFB, and makes the output voltage lower proportional to the load current. The positioning voltage can be programmed by the resistor RDRP so that the droop impedance produces the desired converter output impedance. The offset and slope of the converter output impedance are referenced to and therefore independent of the VDAC voltage. Due to the difference between VDAC and VSETPT, the VDRP will cause extra offset voltage through RDRP and RFB. The total offset voltage is the sum of voltage across RVSETPT and the voltage drop on the RFB at no load. Control IC VDAC VDAC Phase IC Current Sense Amplifier + VDAC - 10k CSIN- Vo Error Amplifier VDRP Amplifier ... ... FB RFB RDRP Phase IC VDRP Current Sense Amplifier + IIN ISHARE VDAC 10k CSIN+ - - + IOFFSET EAOUT CSIN+ - ISHARE + VSETPT RSETPT CSIN- Figure 8 − Adaptive voltage positioning Page 16 of 45 03/4/2009 IR3084 Inductor DCR Temperature Correction If the thermal compensation of the inductor DCR provided by the temperature dependent gain of the current sense amplifier is not adequate, a negative temperature coefficient (NTC) thermistor can be used for additional correction. The thermistor should be placed close to the inductor and connected in parallel with the feedback resistor, as shown in Figure 9. The resistor in series with the thermistor is used to reduce the nonlinearity of the thermistor. Control IC VDAC RSETPT VSETPT + EAOUT IOFFSET Vo RFB Error Amplifier AVP Amplifier RFB2 Rt RDRP VDRP + IIN Figure 9 − Temperature compensation of inductor DCR Remote Voltage Sensing To compensate for impedance in the ground plane, the VOSNS− pin is used for remote sensing and connects directly to the load. The VDAC voltage is referenced to VOSNS− to avoid additional error terms or delay related to a separate differential amplifier. The capacitor connecting the VDAC and VOSNS− pins ensure that high speed transients are fed directly into the error amp without delay. Start-up Modes The IR3084 has a programmable soft-start function to limit the surge current during the converter start-up. A capacitor connected between the SS/DEL and LGND pins controls soft start as well as over-current protection delay and hiccup mode timing. A charge current of 70uA controls the positive slope of the voltage at the SS/DEL pin. There are two types of start-up possible: Boot Mode (VR11) and Non-Boot Mode (legacy VR10). In Boot Mode, the soft start circuitry will initially set the voltage at the VDAC pin to 1.1V and the converter’s output will slowly rise, using the slew rate set by the capacitor at the SS/DEL pin, until it’s equal to 1.1V. After Vcore achieves the 1.1V Boot voltage, there will be a short delay, the VID pins will be sampled, and the voltage at the VDAC pin and the converter’s output will increase or decrease to the desired VID setting using the dynamic VID slew rate. In Non-Boot Mode, the soft start sequence will ramp the voltage at the VDAC pin directly to the external VID setting using the slew rate set by the capacitor at the SS/DEL pin without pausing at the 1.1V Boot voltage. Page 17 of 45 03/4/2009 IR3084 Figure 10a depicts the start-up sequence without AVP in Boot Mode (VRM11) − VIDSEL is either floating or grounded. First, the VDAC pin is charged to the 1.1V Boot voltage. Then, if there are no fault conditions, the SS/DEL capacitor will begin to be charged. Initially, the error amplifier’s output will be clamped low until the voltage at the SS/DEL pin reaches 1.3V. After the voltage at the SS/DEL pin rises to 1.3V, the error amplifier’s output will begin to rise and the converter’s output voltage will be regulated 1.3V below the voltage at the SS/DEL pin. The converter’s output voltage will slowly ramp to the 1.1V Boot voltage. The SS/DEL pin’s voltage will continue to increase until it rises above the 3.1V threshold of the VID delay comparator. When the SS/DEL voltage exceeds 3.1V, the VID inputs will be sampled and the VDAC pin will transition to the level determined by the VID inputs at the dynamic VID slew rate. When the voltage on the SS/DEL pin rises above 3.77V the VRRDY Delay Comparator will allow the VRRDY signal to be asserted. SS/DEL will continue to rise until finally settling at 3.85V, indicating the end of the start-up sequence. Figure 10b depicts the start-up sequence in Non-Boot Mode − VIDSEL is connected to VBIAS (6.9V) or to VCC (12V). First, the external VID setting is sampled and the VDAC pin is set to the desired VID voltage. Then, if there are no fault conditions, the SS/DEL capacitor will begin to charge. Initially, the error amplifier’s output will be clamped low until the voltage at the SS/DEL rises to 1.3V. After the voltage at the SS/DEL pin reaches 1.3V, the error amplifier’s output will begin to rise and the converter’s output voltage will be regulated 1.3V below the voltage at the SS/DEL pin. As the voltage at the SS/DEL pin continues to rise, the converter’s output voltage will slowly increase until it is equal to the voltage at the VDAC pin. When the voltage on the SS/DEL pin rises above 3.77V the VRRDY Delay Comparator will allow the VRRDY signal to be asserted. SS/DEL will continue to rise until finally settling at 3.85V, indicating the end of the start−up sequence. If AVP is used (RDRP ≠ ∞), the soft start timing will change slightly because of the resistor from the VDRP amplifier to the Error Amplifier’s FB pin. During startup with AVP, the VDRP amplifier will produce a voltage at the FB pin equal to VDAC times the resistor divider formed by the droop resistor and the feedback resistor from Vcore to the FB pin. To offset the contribution from the VDRP amplifier, the voltage at the SS/DEL pin will have to rise to beyond 1.3V before the Error Amplifier’s output and Vcore begin to rise. For a DAC setting of 1.3V with typical load line slope, the Error Amplifier’s output will begin to rise when the voltage at the SS/DEL pin reaches approximately 1.6V. The effect of this offset will be to slightly lengthen the Start Delay (TD1) and shorten the Soft Start Ramp Time (TD2). The following table summarizes the differences between the 4 modes associated with setting the VIDSEL pin. In addition to changing the soft start sequence, the NO_CPU code may or may not be ignored during startup and the NO_CPU code may or may not be latched. VIDSEL Voltage VID Table GND FLOAT (1.2V) VBIAS (6.9V) VCC (12V) VR10 VR11 VR11 VR10 1.1V Boot Voltage During Startup? YES YES NO NO Ignore NO CPU Codes During Startup? YES YES NO NO Latch NO CPU Fault Code? YES YES NO NO Table 3: 3084 Controller Functionality versus VIDSEL Voltages Page 18 of 45 03/4/2009 IR3084 9.1V UVLO +12Vin ENABLE (VTT) 0.85V 1.100V VDAC 3.85V 3.77V 3.10V 1.30V SS/DEL EAOOUT 1.100V VDAC IIN 1.100V VOUT VRRDY START (ENABLE ENDS FAULT MODE) START DELAY 1.8ms (TD1) SOFT START TIME 1.6ms (TD2) VID SAMPLE DELAY 1.0ms (TD3) VR_RDY DELAY 1.3ms (TD4+TD5) NORMAL OPERATION POWER-DOWN (VCC UVL INITIATES FAULT MODE) DYNAMIC VID TIME 200us (TD4) Figure 10a – Start−up Waveforms with Boot Mode (VID Setting > 1.1V) 9.1V UVLO +12Vin ENABLE (VTT) 0.85V VID SETTING VDAC 3.77V 1.30V SS/DEL EAOOUT VID SETTING IIN VID SETTING VOUT VRRDY START (ENABLE ENDS FAULT MODE) START DELAY 1.8ms SOFT START TIME 1.6ms VR_RDY DELAY 2.3ms POWER-DOWN (VCC UVL INITIATES FAULT MODE) NORMAL OPERATION Figure 10b – Start−up Waveforms without 1.1V Boot Mode (VID Setting=1.1V) Page 19 of 45 03/4/2009 IR3084 Fault Modes Under Voltage Lock Out, VID = FAULT, as well as a low signal on the ENABLE input immediately sets the fault latch. This causes the EAOUT pin to drive low turning off the Phase IC drivers. The VRRDY pin also drives low. The SS/DEL capacitor will discharge down to 0.215V through a 6.5uA current source. If the fault has cleared the fault latch will be reset by the discharge comparator allowing a normal start-up sequence to occur. If a VID = FAULT condition is latched it can only be cleared by cycling power to the IR3084 on and off. Over−Current Protection Delay and Hiccup Mode Figure 11 depicts the operating waveforms of the Over-Current protection. A delay is included if an over-current condition occurs after a successful soft start sequence. This is required because over-current conditions can occur as part of normal operation due to load transients or VID transitions. If an over-current fault occurs during normal operation it will activate the SS/DEL discharge current of 40uA but will not set the fault latch immediately. If the over-current condition persists long enough for the SS/DEL capacitor to discharge below the 100mV offset of the delay comparator, the Fault latch will be set pulling the error amp’s output low inhibiting switching in the phase ICs and de-asserting the VRRDY signal. The SS/DEL capacitor will continue to discharge until it reaches 0.215V and the fault latch is reset allowing a normal soft start to occur. If an over-current condition is again encountered during the soft start cycle the fault latch will be set without any delay and hiccup mode will begin. During hiccup mode the 10.8 to 1 charge to discharge current ratio results in a 9% hiccup mode duty cycle regardless of at what point the over-current condition occurs. If the voltage at the SS/DEL pin is pulled below the SS/DEL to FB Input Offset Voltage (0.85V min), the converter can be disabled. SS/DEL (3.85V DURING NORMAL OPERATION) 3.77V 3.75V 1.3V DISCHARGE VOLTAGE (0.215V) VOUT VRRDY OCP THRESHOLD IOUT NORMAL OPERATION HICCUP MODE OVER-CURRENT PROTECTION OCP DELAY RESTART AFTER OCP Figure 11 – Over-Current Protection Waveforms (VID = 1.1V for simplicity) Page 20 of 45 03/4/2009 NORMAL OPERATION IR3084 Under Voltage Lockout (UVLO) The UVLO function monitors the IR3084’s VCC supply pin and ensures that there is adequate voltage to safely power the internal circuitry. The IR3084’s UVLO threshold is set higher than the minimum operating voltage of compatible Phase ICs thus providing UVLO protection for them as well. UVLO at the Phase ICs is a function of the Error Amplifier’s output voltage. When the IR3084 is in UVLO, the Error Amplifier is disabled and EAOUT is at a very low voltage ( 1.1V (4a) TD 4  CVDAC  1.1V  VDAC  I SINK if VDAC < 1.1V (4b) Where: VDAC is the DAC voltage set by the VID pins. ISOURCE and ISINK are the source and sink currents of the VDAC pin. If Boot Mode is not used then TD4 = 0. Page 25 of 45 03/4/2009 IR3084 No Load Output Voltage Setting Resistor RVSETPT, Feedback Resistor RFB, and AVP Resistor RDRP An external resistor, RVSETPT, connected between the VDAC pin and the VSETPT pin is used to set the no load output voltage offset, VO_NLOFST, which is the difference between the VDAC voltage and output voltage at no load. However, the converter’s output voltage will be set by the combination of VSETPT plus some contribution from the VDRP pin. At no load, both pins of the Error Amplifier are at VDAC – VSETPT while the VDRP pin is at VDAC + VOS•GCSA (VOS and GCSA are the input offset and gain of the current sense amplifiers). Because the VDRP pin is at a higher voltage than the FB pin of the Error Amplifier, VDRP will contribute to the no load offset through the RDRP and RFB resistors. The design approach is to choose a value for the feedback resistor, RFB, from 100 to 2K and then calculate RDRP and RVSETPT to provide the required no load offset voltage. VSETPT  A A* D  C * B (A  B  C  D) Io * RL * GCSA  VCS _ TOFST * GCSA  VOS_EA n B  VO_NLOFST  Io * Ro  VOS_EA Where: (5) C  VCS _ TOFST * GCSA  VOS_EA D  VO_NLOFST  VOS_EA IO is the full load output current of the converter RL is the ESR of the output inductor GCSA is the gain of the current sense amplifiers n is the number of phases VOS_EA is the offset voltage of the error amplifier (− to + pin) VO_NLOFST is the desired no load offset voltage below the DAC setting Ro is the desired load line resistance VCS_TOFST is the total offset voltage of the current sense amplifiers, see below. The total input offset voltage (VCS_TOFST) of the current sense amplifier in the phase IC is the sum of input offset (VCS_OFST) of the amplifier itself plus that created by the amplifier input bias currents flowing through the current sense resistors RCS+ and RCS− as shown in Equation (6). VCS_TOFST  VCS_OFST  I CSIN   RCS    I CSIN   RCS   (6) Finally, calculate the no-load setpoint resistor using Equation (7) and the droop resistor using Equation (8); RVSETPT  Where: VSETPT IVSETPT IVSETPT is the current into the VSETPT pin at the switching frequency which is a function of ROSC, see Figure 15 on page 23. VSETPT is calculated by Equation (5). RDRP  RFB  Page 26 of 45 (7) VSETPT  C D  VSETPT (8) 03/4/2009 IR3084 Soft Start Capacitor CSS/DEL and Resistor RSS/DEL Because the capacitor CSS/DEL programs three different time parameters, i.e. soft start time, over current latch delay time, and the frequency of hiccup mode, they should be considered together while choosing CSS/DEL. The soft-start ramp time (TD2) is the time required for the converter’s output voltage to rise from 0V to the DAC voltage (VDAC). Given a desired soft-start ramp time (TD2) and the soft-start charge current (ICHG) from the data sheet, the value of the external capacitor (CSS/DEL) can be calculated using Equation (9). C SS / DEL  I CHG * TD 2 70 *10 6 * TD 2  RFB RFB     VDAC  1   VDAC  1    RFB  RDRP   RFB  RDRP  (9) Where: VDAC = 1.1V in Boot Mode or the DAC voltage set by the VID pins without Boot Mode. RFB is the resistor from Vcore to the FB pin of the controller. RDRP is the resistor from VDRP to FB. If droop is not used, set the second term within the parenthesis to zero (RDRP = ∞). Once CSS/DEL is determined, the soft start delay time TD1, the VID sample time TD3, the VRRDY delay time TD5, and the over-current fault latch delay time TOCDEL are determined and can be calculated using Equations (10), (11), (12), and (13) respectively. TD1  C SS / DEL  RFB   1.3V  VDAC   I CHG RFB  RDRP   (10) Where: VDAC = 1.1V in Boot Mode or the DAC voltage set by the VID pins without Boot Mode. ICHG is the soft-start charge current, nominally 70µA. RFB is the resistor from Vcore to the FB pin of the controller. RDRP is the resistor from VDRP to FB. If droop is not used, set the second term within the parenthesis to zero (RDRP = ∞). TD3  C SS / DEL C  3.1V  1.3V  1.1V   SS / DEL6  0.7V I CHG 70 * 10 (11) If Boot Mode is not used, then TD3 is zero. TD5  C C SS / DEL * (3.85V  3.1V ) * 0.75V  TD 4  SS / DEL 6  TD 4 I CHG 70 * 10 (12) Where: TD4 is the VID voltage rise time calculated from Equation 4. TOCDEL  C SS / DEL * 100mV C SS / DEL * 100mV  I OC _ DISCHG 40 * 10 6 (13) Where: IOC_DISCHG is the over-current discharge current of the SS/DEL pin from the data sheet. Page 27 of 45 03/4/2009 IR3084 Over Current Setting Resistor ROCSET The inductor DC resistance is utilized to sense the inductor current. The copper wire of the inductor has a constant temperature coefficient of 3850 PPM, and therefore the maximum inductor DCR can be calculated from Equation (14), where RL_MAX and RL_ROOM are the inductor DCR at maximum temperature TL_MAX and room temperature T_ROOM respectively. R L_MAX  R L_ROOM  [1  3850*10 6  (TL_MAX  TROOM )] (14) The current sense amplifier gain of the IR3086A decreases with temperature at the rate of 1470 PPM, which compensates part of the inductor DCR increase. The phase IC die temperature is only a couple of degrees Celsius higher than the PCB temperature due to the low thermal impedance of MLPQ package. The minimum current sense amplifier gain at the maximum phase IC temperature TIC_MAX is calculated from Equation (15). GCS_MIN  GCS_ROOM  [1  1470*10 6  (TIC_MAX  TROOM )] (15) The over-current limit is set by the external resistor ROCSET as defined in Equation (16), where ILIMIT is the required over current limit. IOCSET, the bias current of the OCSET pin, changes with switching frequency setting resistor ROSC and is determined by the curve in Figure 14 on page 23. KP is the ratio of inductor peak current to average current in each phase and is calculated from Equation (17). ROCSET  [ KP  GCS _ MIN I LIMIT  R L_MAX  (1  K P )  VCS_TOFST ]  n I OCSET (V I  VO _ FL )  VO _ FL /(L  V I  f SW  2) I LIMIT /n (16) (17) Where: VI is the input voltage to the converter (nominally 12V). VO_FL is the output voltage of the converter with droop at the over-current threshold. L is the value of the output inductors. fSW is the switching frequency. ILIMIT is the DC output current of the converter when the over-current fault occurs. n is the number of phases. Page 28 of 45 03/4/2009 IR3084 IR3086 EXTERNAL COMPONENTS PWM Ramp Resistor RPWMRMP and Capacitor CPWMRMP PWM ramp is generated by connecting the resistor RPWMRMP between a voltage source and PWMRMP pin as well as the capacitor CPWMRMP between PWMRMP and LGND. Choose the desired PWM ramp magnitude VRAMP and the capacitor CPWMRMP in the range of 100pF and 470pF, and then calculate the resistor RPWMRMP from Equation (18). To achieve feed−forward voltage mode control, the resistor RRAMP should be connected to the input of the converter. R PWMRMP  V O V *f IN SW *C V *[ln(V  V )  ln(V  V )] PWMRMP IN DAC IN DAC PWMRMP (18) Inductor Current Sensing Capacitor CCS+ and Resistors RCS+ and RCS− The DC resistance of the inductor is utilized to sense the inductor current. Usually the resistor RCS+ and capacitor CCS+ in parallel with the inductor are chosen to match the time constant of the inductor, and therefore the voltage across the capacitor CCS+ represents the inductor current. If the two time constants are not the same, the AC component of the capacitor voltage is different from that of the real inductor current. The time constant mismatch does not affect the average current sharing among the multiple phases, but affect the current signal ISHARE as well as the output voltage during the load current transient if adaptive voltage positioning is adopted. Measure the inductance L and the inductor DC resistance RL. Pre−select the capacitor CCS+ and calculate RCS+ as follows. RCS   L RL C CS  (19) The bias current flowing out of the non-inverting input of the current sense amplifier creates a voltage drop across RCS+, which is equivalent to an input offset voltage of the current sense amplifier. The offset affects the accuracy of converter current signal ISHARE as well as the accuracy of the converter output voltage if adaptive voltage positioning is adopted. To reduce the offset voltage, a resistor RCS− should be added between the amplifier inverting input and the converter output. The resistor RCS− is determined by the ratio of the bias current from the non-inverting input and the bias current from the inverting input. RCS   I CSIN   RCS  I CSIN  (20) If RCS− is not used, RCS+ should be chosen so that the offset voltage is small enough. Usually RCS+ should be less than 2 kΩ and therefore a larger CCS+ value is needed. Page 29 of 45 03/4/2009 IR3084 Over Temperature Setting Resistors RHOTSET1 and RHOTSET2 The threshold voltage of VRHOT comparator is proportional to the die temperature TJ (ºC) of phase IC. Determine the relationship between the die temperature of phase IC and the temperature of the power converter according to the power loss, PCB layout and airflow etc, and then calculate HOTSET threshold voltage corresponding to the allowed maximum temperature from Equation (21). V HOTSET  4.73*10 3 *TJ  1.241 (21) There are two ways to set the over temperature threshold, central setting and local setting. In the central setting, only one resistor divider is used, and the setting voltage is connected to HOTSET pins of all the phase ICs. To reduce the influence of noise on the accuracy of over temperature setting, a 0.1uF capacitor should be placed next to HOTSET pin of each phase IC. In the local setting, a resistor divider per phase is needed, and the setting voltage is connected to HOTSET pin of each phase. The 0.1uF decoupling capacitor is not necessary. Use VBIAS as the reference voltage. If RHOTSET1 is pre−selected, RHOTSET2 can be calculated as follows. R HOTSET2  R HOTSET1  V HOTSET V BIAS  V HOTSET (22) Phase Delay Timing Resistors RPHASE1 and RPHASE2 The phase delay of the interleaved multiphase converter is programmed by the resistor divider connected at RMPIN+ or RMPIN− depending on which slope of the oscillator ramp is used for the phase delay programming of phase IC, as shown in Figure 4. If the positive slope is used, RMPIN+ pin of the phase IC should be connected to RMPOUT pin of the control IC and RMPIN− pin should be connected to the resistor divider. When RMPOUT voltage is above the trip voltage at RMPIN− pin, the PWM latch is set. GATEL becomes low, and GATEH becomes high after the non-overlap time. If the negative slope is used, RMPIN− pin of the phase IC should be connected to RMPOUT pin of the control IC and RMPIN+ pin should be connected to the resistor divider. When RMPOUT voltage is below the trip voltage at RMPIN− pin, the PWM latch is set. GATEL becomes low, and GATEH becomes high after the non-overlap time. It is best to use the VBIAS voltage as the reference for the resistor dividers because the oscillator ramp magnitude from the control IC will track the VBIAS voltage. It is best to avoid the peak and valley of the oscillator ramp for better noise immunity. Determine the ratio of the programming resistors corresponding to the desired switching frequencies and phase numbers. If the resistor RPHASEx1 is pre-selected, the resistor RPHASEx2 is determined as: R PHASEx2  RAPHASEx  R PHASEx1 1  RAPHASEx Page 30 of 45 (23) 03/4/2009 IR3084 Combining the Over Temperature and Phase Delay Setting Resistors RPHASE1, RPHASE2 and RPHASE3 The over temperature setting resistor divider can be combined with the phase delay resistor divider to save one resistor per phase. Calculate the HOTSET threshold voltage VHOTSET corresponding to the allowed maximum temperature from Equation (20). If the over temperature setting voltage is lower than the phase delay setting voltage, VBIAS*RAPHASEx, connect RMPIN+ or RMPIN− pin between RPHASEx1 and RPHASEx2 and connect HOTSET pin between RPHASEx2 and RPHASEx3 respectively. Pre-select RPHASEx1, then calculate RPHASEx2 and RPHASEx3, R PHASEx2  (RAPHASEx  V BIAS  V HOTSET )*R PHASEx1 V BIAS  (1  RAPHASEx ) (24) R PHASEx3  V HOTSET  R PHASEx1 V BIAS*(1  RAPHASEx ) (25) If the over temperature setting voltage is higher than the phase delay setting voltage, VBIAS*RAPHASEx, connect HOTSET pin between RPHASEx1 and RPHASEx2 and connect RMPIN+ or RMPIN− between RPHASEx2 and RPHASEx3 respectively. Pre-select RPHASEx1, R PHASEx2  (V HOTSET  RAPHASEx  V BIAS )  R PHASEx1 V BIAS  V HOTSET (26) R PHASEx3  RAPHASEx  V BIAS*R PHASEx1 V BIAS  V HOTSET (27) Bootstrap Capacitor CBST Depending on the duty cycle and gate drive current of the phase IC, a 0.1uF to 1uF capacitor is needed for the bootstrap circuit. Decoupling Capacitors for Phase IC 0.1uF−1uF decoupling capacitors are required at VCC and VCCL pins of phase ICs. Page 31 of 45 03/4/2009 IR3084 VOLTAGE LOOP COMPENSATION The adaptive voltage positioning is used in the computer applications to meet the load line requirements. Like current mode control, the adaptive voltage positioning loop introduces extra zero to the voltage loop and splits the double poles of the power stage, which make the voltage loop compensation much easier. Resistors RFB and RDRP are chosen according to Equations (15) and (16), and the selection of compensation type depends on the capacitors used. For the applications using Electrolytic, Polymer or AL−Polymer capacitors, type II compensation shown in Figure 20 (a) is usually enough. While for the applications with only ceramic capacitors, type III compensation shown in Figure 20 (b) is preferred. CCP1 CCP1 RFB VO+ RCP VO+ RFB CCP - VDAC RDRP CFB FB CCP EAOUT FB EAOUT VDRP RFB1 RCP EAOUT + (a) Type II compensation VDRP RDRP VDAC EAOUT + CDRP (b) Type III compensation Figure 20: Voltage Loop Compensation Networks Type II Compensation Determine the compensation at no load, the worst case condition. Choose the crossover frequency fc between 1/10 and 1/5 of the switching frequency per phase. Assume the time constant of the resistor and capacitor across the output inductors matches that of the inductor, RCP and CCP can be determined by Equations (28) and (29). RCP  C CP  (2π * f C ) 2 * L E * C E * R FB * V PWMRMP VO * 1  (2π * f C * C E * RCE ) 2 10 * L E * C E RCP (28) (29) Where LE and RCE are the equivalent output inductance and ESR of the output capacitors, respectively. CCP1 is optional and may be needed in some applications to reduce the jitter caused by the high frequency noise. A ceramic capacitor between 10pF and 220pF is usually enough. Page 32 of 45 03/4/2009 IR3084 Type III Compensation Determine the compensation at no load, the worst case condition. Choose the crossover frequency fc between 1/10 and 1/5 of the switching frequency per phase. Assume the time constant of the resistor and capacitor across the output inductors matches that of the inductor, RCP and CCP can be determined by Equations (30) and (31), where CE is equivalent output capacitance. RCP  C CP  (2π * f C ) 2 * L E * C E * V PWMRMP Vo (30) 10 * L E * C E (31) RCP Choose resistor RFB1 according to Equation (33), and determine CFB and RDRP from Equations (32) and (33). R FB1  C FB  1 * R FB 2 to R FB1  2 * R FB 3 1 (32) (33) 4π * f C1 * R FB1 CCP1 is optional and may be needed in some applications to reduce the jitter caused by the high frequency noise. A ceramic capacitor between 10pF and 220pF is usually enough. CURRENT SHARE LOOP COMPENSATION The crossover frequency of the current share loop should be at least one decade lower than that of the voltage loop in order to eliminate the interaction between the two loops. A capacitor from SCOMP to LGND is usually enough for most of the applications. Choose the crossover frequency of current share loop (fCI) based on the crossover frequency of voltage loop (fC), and determine the CSCOMP, C SCOMP  0.65 * R PWMRMP * V I * I O * GCS_ROOM * R LE * [1  2π * f CI * C E * ( VO I O )] * FMI VO * 2π * f CI * 1.05 * 10 6 Where FMI is the PWM gain in the current share loop, FMI  R PWMRMP * C PWMRMP * f SW * V PWMRMP (VO  V PWMRMP  V DAC ) * (V I  V DAC ) Page 33 of 45 (35) 03/4/2009 (34) IR3084 DESIGN EXAMPLE: VRM 11 7−PHASE CONVERTER SPECIFICATIONS Input Voltage: VI = 12V DAC Voltage: VDAC = 1.3V No Load Output Voltage Offset: VO_NLOFST = 15mV Output Current: IO = 130 ADC Maximum Output Current: IOMAX = 150 ADC Load Line Slope: RO = 1.20 mΩ VRM11 Startup Boot Voltage = 1.100V Soft Start Time: TD2 = 1.1ms VCC Ready to VCC Power Good Delay: TD5 = 1.0ms Over Current Delay: TOCDEL = 250µs Dynamic VID Negative Slew Rate: SRDOWN = 2.5mV/us Over Temperature Threshold: TPCB = 115 ºC POWER STAGE Phase Number: n = 7 Switching Frequency: fSW=400 kHz Output Inductors: L = 220 nH, RL = 0.60 mΩ Output Capacitors: C = 560uF, RC = 7mΩ, Number Cn = 10 IR3084 EXTERNAL COMPONENTS Oscillator Resistor Rosc The switching frequency sets the value of ROSC as shown by the curve in Figure 13 on page 23. In this design, the switching frequency of 400kHz per phase requires ROSC to be 30.1kΩ. VDAC Slew Rate Programming Capacitor CVDAC and Resistor RVDAC From Figure 17 on page 23, the sink current of the VDAC pin at 400kHz (ROSC=30.1kΩ) is 80uA. Calculate the VDAC slew-rate programming capacitor from the specified negative slew rate using Equation (1). CVDAC  I SINK 80 * 10 6   32.0nF , SR DOWN 2.5 * 10 3 / 10 6 Choose CVDAC = 33nF Calculate the VDAC compensation resistor from Equation (2); RVDAC  0.5  3.2*10 15 CVDAC 2  0.5  3.2*10 15  3.5Ω (33*10 9 ) 2 From Figure 17 on page 23, the source current of the VDAC pin is 90uA at ROSC = 30.1KΩ. The VDAC positive slew rate is can be calculated using Equation (3); SRUP I SOURCE 90*10 6    2.7mV/uS CVDAC 33*10 9 Page 34 of 45 03/4/2009 IR3084 Using the calculated value of CVDAC, find the positive VID voltage rise time (TD4) to the specified nominal DAC voltage of 1.300V during startup with Boot Mode using Equation 4a; TD 4  CVDAC 33nF * 1.300V  1.1V   73.3us  VDAC  1.1V   90uA I SOURCE No Load Output Voltage Setting Resistor RVSETPT, RFB and Adaptive Voltage Positioning Resistor RDRP First, use Equations (19) and (20) to calculate the current sense resistors RCS+ and RCS−, respectively. For this design, in the next section, RCS+ is determined to be 10KΩ and RCS− is found to be 6.19KΩ. Second, calculate the total input offset voltage (VCS_TOFST) of the current sense amplifiers using Equation (6). From the IR3086A data sheet, typical values for the ICSIN+ and ICSIN− bias currents are determined to be 0.25µA and 0.40µA, respectively. VCS_TOFST  VCS_OFST  I CSIN   RCS    I CSIN   RCS    0.55mV  0.25 *10 6 *10 K   0.40 *10 6 * 6.19 K   0.574mV Next, derive the intermediate calculations (A,B,C,D) as shown below before finally calculating RVSETPT and RDRP using Equations (7) and (8). From Figure 15 on page 23, the IVSETPT bias current is determined to be 40µA at ROSC=30.1kΩ and a typical value for the offset voltage of the error amplifier is 0.0mV. A Io * RL * GCSA 130 * 0.60 *10 3 * 34  VCS _ TOFST * GCSA  VOS _ EA   0.574 *10 3 * 34  0.0mV n 7  0.3984 B  VO _ NLOFST  Io * Ro  VOS _ EA  15 * 10 3  130 * 1.20 * 10 3  0.0mV  0.1710 C  VCS_TOFST*GCSA  VOS_EA  0.574*10 3 *34  0.0mV  0.0.0195 D  VO _ NLOFST  VOS _ EA  15 * 10 3  0.0mV  0.015 VSETPT  A* D  C * B 0.3984 * 0.015  0.0195 * 0.1710   0.00494V ( A  B  C  D) 0.3984  0.1710  0.0195  0.015 RVSETPT  VSETPT 0.00494   123.5ohms IVSETPT 40 x10 6 Choose the closest standard resistor value to this with 1% tolerance or RVESTPT = 124ohms. Page 35 of 45 03/4/2009 IR3084 Select RFB = 324 ohms and then calculate the droop resistor, RDRP  RFB  VSETPT  C 0.00494  0.0195  324   787.1ohms D  VSETPT 0.015  0.00494 Choose the next standard value higher than this with 1% tolerance or RDRP = 787ohms. Soft Start Capacitor CSS/DEL and Startup Times Calculate the soft start capacitor from the required soft start time using Equation (9) with Boot Mode; C SS / DEL  70 * 10 6 * TD 2 70 *10 6 *1.1 *10 3  0.0988uF or 0.1uF  RFB 324     VDAC  1    1.1V * 1   324  787   RFB  RDRP  The soft start delay time can be calculated using Equation (10) with Boot Mode; TD1  C SS/DEL I CHG 6 RFB  0.1 *10     1.3V  VDAC   RFB  RDRP  70 * 10 6  324   * 1.3V  1.1V *  324  787    2.31ms The VID sample time can be found using Equation (11); TD3  C SS / DEL  0.7V 0.1 * 10 6  0.7   1.00mS I CHG 70 * 10 6 The power good delay time can be found using Equation (12); TD5  C SS / DEL * 0.75V 0.1 *10 6 * 0.75V  TD 4   73us  0.998ms I CHG 70 *10 6 Finally, use Equation (13) to calculate the over-current fault latch delay time; TOCDEL  C SS / DEL *100mV 0.1 *10 6 *100 *10 3   250us 40 *10 6 40 * 10 6 Page 36 of 45 03/4/2009 IR3084 Over Current Setting Resistor ROCSET Assume that room temperature is 25ºC and the target PCB temperature is 100 ºC. The phase IC die temperature is usually about 1 ºC higher than that of phase IC and the inductor temperature is close to PCB temperature. Calculate the Inductor’s DC resistance at 100 ºC using Equation (14); RL_MAX  RL_ROOM  [1  3850*106  (TL_MAX  TROOM )]  0.60*103  [1  3850*106  (100  25)]  0.77m The current sense amplifier gain is 34 at 25ºC, and its gain at 101ºC is calculated using Equation (15), GCS_MIN  GCS_ROOM  [1  1470*10 6  (TIC_MAX  TROOM )]  34  [1  1470*10 6  (101  25)]  30.2 Here we will set the over current shutdown threshold to 155A at maximum operating temperature. From Figure 14 on page 23, the bias current of the OCSET pin (IOCSET) is 42.5µA with ROSC=30.1kΩ. The total current sense amplifier input offset voltage calculated previously is 0.574mV, which includes the offset created by the current sense amplifier input resistor mismatch. Calculate the constant KP, the ratio of inductor peak current over average current in each phase using Equation (17); KP  (V I  VO )  VO /( L  V I  f SW  2) (12  1.18)  1.18 /(220 * 10 9  12  400 * 10 3  2)   0.273 I LIMIT / n 155 / 7 Finally, calculate the over-current setting resistor using Equation (16); ROCSET  [ ( GCS _ MIN R LIMIT  R L_MAX  (1  K P )  VCS_TOFST ]  n I OCSET 30 .2 155  0.77 * 10 3  1  0.273   0.574 * 10 3 )   15.8K  7 42.5 * 10 3 Page 37 of 45 03/4/2009 IR3084 IR3086 PHASE IC COMPONENTS PWM Ramp Resistor RRAMP and Capacitor CRAMP Set the PWM ramp magnitude VPWMRMP to 0.8V. Choose 220pF for the PWM ramp capacitor CPWMRMP and calculate the resistor RPWMRMP using Equation (18); R PWMRMP   V IN  f SW  C PWMRMP  [ln(V IN 12  400*10  220*10 3 12 VO  V DAC )  ln(V IN  V DAC  V PWMRMP )] 1.30  15.8kΩ ,  [ln(12  1.30)  ln(12  1.30  0.8)] Choose a standard resistor value, RPWMRMP=15.8kΩ. Inductor Current Sensing Capacitor CCS+ and Resistors RCS+ and RCS− Choose CCS+=47nF and calculate RCS+ using Equation (19); R CS  L R L 220 * 10 9 /(0.47 * 10 3 )   10.0kΩ C CS 47 * 10 9 The bias currents of CSIN+ and CSIN− are 0.25uA and 0.4uA respectively. Calculate resistor RCS− using Equation (20); RCS   0.25 0.25  RCS   10.0 *10 3  6.2k , 0.4 0.4 choose RCS− = 6.19kΩ Over Temperature Setting Resistors RHOTSET1 and RHOTSET2 Use central over temperature setting and set the temperature threshold at 115 ºC, which corresponds the IC die temperature of 116 ºC. Calculate the HOTSET threshold voltage corresponding to the temperature thresholds using Equations (21) and (22); V HOTSET  4.73 *10 3 * T J  1.241  4.73 *10 3 116  1.241  1.79V , choose RHOTSET1=20.0kΩ, R HOTSET 2  R HOTSET 1  V HOTSET 20 * 10 3  1.79   7.14k V BIAS  VHOTSET 6.8  1.79 Page 38 of 45 03/4/2009 IR3084 Phase Delay Timing Resistors RPHASEx1 to RPHASEx2 (x=1,2,…,7) The phase delay resistor ratios for phases 1 to 7 at 400kHz are (from the X−Phase Excel based design spreadsheet); RAPHASE1=0.580, RAPHASE2=0.397, RAPHASE3=0.215, RAPHASE4=0.206, RAPHASE5=0.353 RAPHASE6=0.5 and RAPHASE7=0.647. Pre−select RPHASE11=RPHASE21=RPHASE31=RPHASE41=RPHASE51=RPHASE61=RPHASE71=20kΩ, R PHASE12  RAPHASE1 0.58  RPHASE11   20 * 10 3  27.6k 1  RAPHASE1 1  0.58 Calculating the other resistors from the same formula results in; RPHASE22=13.2kΩ, RPHASE32=5.48kΩ, RPHASE42=5.2kΩ, PPHASE52=10.9kΩ, RPHASE62=20kΩ, RPHASE72=36.6kΩ. Phase ICs 1−3 should have the RMPOUT voltage from the 3084 controller connected to their RMPIN− pin so they will trigger on the negative slope of the RMPOUT waveform. Phase ICs 4−7 should have the RMPOUT voltage from the 3084 controller connected to their RMPIN+ pin so they will trigger on the positive slope of the RMPOUT waveform. Bootstrap Capacitor CBST Choose CBST=0.1uF. Decoupling Capacitors for Phase IC and Power Stage Choose CVCC=0.1uF, CVCCL=0.1uF VOLTAGE LOOP COMPENSATION AL−Polymer output capacitors are used in the design, for instructional purposes Type III compensation as shown in Figure 18(b) will be demonstrated here. First, choose the desired crossover frequency as 1/10 of the switching frequency, fC =40 kHz, and determine Rcp and CCP using Equations (30) and (31): RCP (2 * f C ) 2 * LE * C E * RFB * VPWMRMP (2 * 40 * 103 ) 2 * (220 * 10 9 / 7) * (560 * 10 6 * 10) * 324 * 0.8   Vo 1.30  0.015  130 * 1 * 10 3  2.49K C CP  R FB1  C FB  10 * L E * C E RCP  10 * (220 * 10 9 / 7) * (560 * 10 6 * 10) 2.49 * 10 3 1 1 * R FB  * 324  162 2 2 1 4 * f C * R FB1   53nF , Choose CCP=56nF Choose RFB1=162Ω 1  12.3nF 4 * 40 * 10 3 * 162 Choose CFB=10nF Choose CCP1=100pF to reduce high frequency noise. Page 39 of 45 03/4/2009 IR3084 CURRENT SHARE LOOP COMPENSATION The crossover frequency of the current share loop (fCI) should be at least one decade lower than that of the voltage loop fC. Choose the crossover frequency of current share loop fCI =4kHz, and calculate FMI and CSCOMP using Equations (34) and (35); FMI  R PWMRMP * C PWMRMP * f SW *V PWMRMP 15.8 * 10 3 * 220 * 10 12 * 400 * 10 3 * 0.8   0.0105 (V I  V PWMRMP  V DAC ) * (V I  V DAC ) (12  0.8  1.30) * (12  1.30) C SCOMP    0.65 * R PWMRMP * V I * I O * GCS _ ROOM * R LE * [1  2 * f CI * C E * (VO I O )] * FMI VO * 2 * f CI * 1.05 * 10 6 0.65 *15.8 *10 3 *12 *130 * 34 * (0.47 *10 3 7) * [1  2 * 4 *10 3 * 5600 *10 6 * (1.30  130 *1.0 *10 3 ) 130] * 0.0105 (1.30  130 *1.0 *10 3 ) * 2 * 4 *10 3 *1.05 *10 6 36574 * [2.266] * 0.0105 30.859 *10 9 = 28.2nF Choose CSCOMP=22nF with 5% tolerance for best current sharing between phases. Page 40 of 45 03/4/2009 IR3084 LAYOUT GUIDELINES The following layout guidelines are recommended to reduce the parasitic inductance and resistance of the PCB layout, therefore minimizing the noise coupled to the IC. VRRDY VID0 ENABLE VID1 To SYSTEM Page 41 of 45 VID2 VOSNS- CFB RFB RFB1 CDRP RVDAC ROSC CVDAC VOSNS+ ROSC SS/DEL VID4 CSS/DEL REGSET VID3 GND VDAC VID5 RREGSET REGDRV VID6 GND ROCSET OCSET REGFB RVCC RDRP1 RDRP IIN FB VDRP VSETPT VOSNS- LGND RSETPT EAOUT To VIN VBIAS CVCC RMPOUT CCP CCP1 LGND PLANE VCC  VID7  VID_SEL  Dedicate at least one middle layer for a ground plane LGND. Connect the ground tab under the control IC to LGND plane through a via. Place the following critical components on the same layer as control IC and position them as close as possible to the respective pins, ROSC, ROCSET, RVDAC, CVDAC, CVCC, CSS/DEL and RCC/DEL. Avoid using any via for the connection. Place the compensation components on the same layer as control IC and position them as close as possible to EAOUT, FB and VDRP pins. Avoid using any via for the connection. Use Kelvin connections for the remote voltage sense signals, VOSNS+ and VOSNS−, and avoid crossing over the fast transition nodes, i.e. switching nodes, gate drive signals and bootstrap nodes. Control bus signals, VDAC, RMPOUT, IIN, VBIAS, and especially EAOUT, should not cross over the fast transition nodes. RCP    To Voltage Remote Sense 03/4/2009 IR3084 METAL AND SOLDER RESIST  The solder resist should be pulled away from the metal lead lands by a minimum of 0.06mm. The solder resist mis−alignment is a maximum of 0.05mm and it is recommended that the lead lands are all Non Solder Mask Defined (NSMD). Therefore pulling the S/R 0.06mm will always ensure NSMD pads.  The minimum solder resist width is 0.13mm, therefore it is recommended that the solder resist is completely removed from between the lead lands forming a single opening for each “group” of lead lands.  At the inside corner of the solder resist where the lead land groups meet, it is recommended to provide a fillet so a solder resist width of ≥ 0.17mm remains.  The land pad should be Solder Mask Defined (SMD), with a minimum overlap of the solder resist onto the copper of 0.06mm to accommodate solder resist mis−alignment. In 0.5mm pitch cases it is allowable to have the solder resist opening for the land pad to be smaller than the part pad.  Ensure that the solder resist in−between the lead lands and the pad land is ≥ 0.15mm due to the high aspect ratio of the solder resist strip separating the lead lands from the pad land.  The single via in the land pad should be tented with solder resist 0.4mm diameter, or 0.1mm larger than the diameter of the via.  No PCB traces should be routed nor vias placed under any of the 4 corners of the IC package. Doing so can cause the IC to rise up from the PCB resulting in poor solder joints to the IC leads. Page 42 of 45 03/4/2009 IR3084 PCB METAL AND COMPONENT PLACEMENT  Lead land width should be equal to nominal part lead width. The minimum lead to lead spacing should be ≥ 0.2mm to minimize shorting.  Lead land length should be equal to maximum part lead length + 0.2 mm outboard extension + 0.05mm inboard extension. The outboard extension ensures a large and inspectable toe fillet, and the inboard extension will accommodate any part misalignment and ensure a fillet.  Center pad land length and width should be equal to maximum part pad length and width. However, the minimum metal to metal spacing should be ≥ 0.17mm for 2 oz. Copper (≥ 0.1mm for 1 oz. Copper and ≥ 0.23mm for 3 oz. Copper)  A single 0.30mm diameter via shall be placed in the center of the pad land and connected to ground to minimize the noise effect on the IC. Page 43 of 45 03/4/2009 IR3084 STENCIL DESIGN  The stencil apertures for the lead lands should be approximately 80% of the area of the lead lands. Reducing the amount of solder deposited will minimize the occurrence of lead shorts. Since for 0.5mm pitch devices the leads are only 0.25mm wide, the stencil apertures should not be made narrower; openings in stencils < 0.25mm wide are difficult to maintain repeatable solder release.  The stencil lead land apertures should therefore be shortened in length by 80% and centered on the lead land.  The land pad aperture should be striped with 0.25mm wide openings and spaces to deposit approximately 50% area of solder on the center pad. If too much solder is deposited on the center pad the part will float and the lead lands will be open.  The maximum length and width of the land pad stencil aperture should be equal to the solder resist opening minus an annular 0.2mm pull back to decrease the incidence of shorting the center land to the lead lands when the part is pushed into the solder paste. Page 44 of 45 03/4/2009 IR3084 PACKAGE INFORMATION 28L MLPQ (5 x 5 mm Body) – θJA = 30oC/W, θJC = 3oC/W Data and specifications subject to change without notice. This product has been designed and qualified for the Consumer market. Qualification Standards can be found on IR’s Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252−7105 TAC Fax: (310) 252−7903 Visit us at www.irf.com for sales contact information. www.irf.com Page 45 of 45 03/4/2009