IR3092
DATA SHEET
2 PHASE OPTERON, ATHLON, OR VR10.X CONTROL IC
DESCRIPTION
The IR3092 Control IC provides a full featured, single chip solution to implement robust power conversion
solutions for three different microprocessor families; 1) AMD Opteron, 2) AMD Athlon or 3) Intel VR10.X
family of processors. The user can select the appropriate VID range with a single pin. PWM Control and 2
phase gate drive functions are integrated into a single IC. In addition to CPU power, the IR3092 offers a
compact, efficient solution for high current POL converters.
FEATURES
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
5 bit or 6 bit VID with 0.5% overall system accuracy
Selectable VID Code for AMD Opteron, AMD Athlon or Intel VR10.X
Programmable Slew Rate response to “On-the-Fly” VID Code Changes
3.5A Gate Drive Capability
Programmable 100KHz to 540KHz oscillator
Programmable Voltage Positioning (can be disabled)
Programmable Softstart
Programmable Hiccup Over-Current Protection with Delay to prevent false triggering
Simplified Powergood provides indication of proper operation and avoids false triggering
Operates up to 21V input with 7.8V Under-Voltage Lockout
5V UVL with 4.3V Under-Voltage Lockout threshold
Adjustable Voltage, 150mA Bias Regulator provides MOSFET Drive Voltage
Enable Input
OVP Output
Available in a 48L MLPQ package
ORDERING INFORMATION
x
DEVICE
ORDER QUANTITY
IR3092MTR
3000 per Reel
*IR3092M
100 piece strips
Samples Only
VID2
VID1
VID0
VID5
NC
NC
ENABLE
OVP
CSINP1
CSINM
NC
VCCH1
PACKAGE INFORMATION
Page 1 of 37
IR3092
48LD MLPQ
LGND
SETBIAS
VCC
NC
NC
BIASOUT
PWRGD
CSINP2
NC
VID_SEL
NC
NC
VID3
VID4
ROSC
VOSNSOCSET
VDAC
VDRP
FB
EAOUT
SS/DEL
SCOMP
NC
GAT EH1
PGND1
GAT EL1
VCCL
5VUVL
GAT EL2
PGND2
GAT EH2
VCCH2
NC
NC
NC
48L MLPQ
(7 x 7 mm Body)
o
– JA = 27 C/W
06/25/04
IR3092
PIN DESCRIPTION
PIN# PIN SYMBOL PIN DESCRIPTION
1
2
3
4
VID3
VID4
ROSC
VOSNS-
5
OCSET
6
VDAC
7
VDRP
8
FB
9
EAOUT
10
SS/DEL
11
SCOMP
12
13
14
15
16-17
18
19
20
21
22
23-27
28
29
30
31
N/C
LGND
SETBIAS
VCC
N/C
BIASOUT
PWRGD
CSINP2
N/C
VID_SEL
N/C
VCCH2
GATEH2
PGND2
GATEL2
32
5VUVL
33
34
35
36
37
38
39
40
41
42
43-44
45
46
47
48
VCCL
GATEL1
PGND1
GATEH1
VCCH1
NC
CSINM1
CSINP1
OVP
ENABLE
N/C
VID5
VID0
VID1
VID2
Page 2 of 37
Inputs to VID D to A Converter
Inputs to VID D to A Converter
Connect a resistor to VOSNS- to program oscillator frequency and FB, OCSET, BBFB, and VDAC bias currents
Remote Sense Input. Connect to ground at the Load.
Programs the hiccup over-current threshold through an external resistor tied to VDAC and an internal current
source.
Regulated voltage programmed by the VID inputs. Current Sensing and Over Current Protection are referenced
to this pin. Connect an external RC network to VOSNS- to program Dynamic VID slew rate.
Buffered IIN signal. Connect an external RC network to FB to program converter output impedance
Inverting input to the Error Amplifier. Converter output voltage is offset from the VDAC voltage through an
external resistor connected to the converter output voltage at the load and an internal current source. Bias
current is a function of ROSC. Also OVPsense.
Output of the Error Amplifier
Controls Converter Softstart, Power Good, and Over-Current Timing. Connect an external capacitor to LGND to
program the timing.
Compensation for the Current Share control loop. Connect a capacitor to ground to set the control loop’s
bandwidth. Phase 2 is forced to match phase 1’s current.
No Connect.
Local Ground and IC substrate connection
External resistor to ground sets voltage at BIASOUT pin. Bias current is a function of ROSC.
Power for internal circuitry and source for BIASOUT regulator
No Connect.
150mA open-looped regulated voltage set by SETBIAS for GATE drive bias.
Open Collector output that drives low during Softstart or any fault condition. Connect external pull-up.
Non-inverting input to the Phase 2 Current Sense Amplifier.
No Connect.
Ground Selects VR10 VID, Float Selects OPTERON VID, VCC Selects ATHLON VID
No Connect.
Power for Phase 2 High-Side Gate Driver
Phase 2 High-Side Gate Driver Output and input to GATEL2 non-overlap comparator.
Return for Phase 2 Gate Drivers
Phase 2 Low-Side Gate Driver Output and input to GATEH2 non-overlap comparator.
Can be used to monitor the driver supply voltage or 5V supply voltage when converting from 5V. An under
voltage condition initiates Soft Start.
Power for Phase 1 and 2 Low-Side Gate Drivers.
Phase 1 Low-Side Gate Driver Output and input to GATEH1 non-overlap comparator.
Return for Phase 1 Gate Drivers
Phase 1 High-Side Gate Driver Output and input to GATEL1 non-overlap comparator.
Power for Phase 1 High-Side Gate Driver
Not connected
Inverting input to the Phase 1Current Sense Amplifier.
Non-inverting input to the Current Sense Amplifier.
Output that drives high during an Over-Voltage condition.
Enable Input. A logic low applied to this pin puts the IC into Fault mode.
No Connect.
Inputs to VID D to A Converter
Inputs to VID D to A Converter
Inputs to VID D to A Converter
Inputs to VID D to A Converter
06/25/04
IR3092
ABSOLUTE MAXIMUM RATINGS
o
Operating Junction Temperature……………..150 C
o
o
Storage Temperature Range………………….-65 C to 150 C
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
NAME
VID3
VID4
ROSC
VOSNSOCSET
VDAC
VDRP
FB
EAOUT
SS/DEL
SCOMP
N/C
LGND
SETBIAS
VCC
N/C
N/C
BIASOUT
PWRGD
CSINP2
N/C
VID_SEL
N/C
N/C
N/C
N/C
N/C
VCCH2
GATEH2
PGND2
GATEL2
5VUVL
VCCL
GATEL1
PGND1
GATEH1
VCCH1
N/C
CSINM1
CSINP1
OVP
ENABLE
N/C
N/C
VID5
VID0
VID1
VID2
Page 3 of 37
VMAX
30V
30V
30V
0.5V
30V
30V
30V
30V
10V
30V
30V
n/a
n/a
30V
30V
n/a
n/a
30V
30V
30V
n/a
30V
n/a
n/a
n/a
n/a
n/a
30V
30V
0.3V
30V
30V
30V
30V
0.3V
30V
30V
n/a
30V
30V
30V
30V
n/a
n/a
30V
30V
30V
30V
VMIN
-0.3V
-0.3V
-0.5V
-0.5V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
n/a
n/a
-0.3V
-0.3V
n/a
n/a
-0.3V
-0.3V
-0.3V
n/a
-0.3V
n/a
n/a
n/a
n/a
n/a
-0.3V
-0.3V DC, -2V for 100ns
-0.3V
-0.3V DC, -2V for 100ns
-0.3V
-0.3V
-0.3V DC, -2V for 100ns
-0.3V
-0.3V DC, -2V for 100ns
-0.3V
n/a
-0.3V
-0.3V
-0.3V
-0.3V
n/a
n/a
-0.3V
-0.3V
-0.3V
-0.3V
ISOURCE
1mA
1mA
1mA
10mA
1mA
1mA
5mA
1mA
10mA
1mA
5mA
n/a
50mA
1mA
1mA
n/a
n/a
250mA
1mA
250mA
n/a
1mA
n/a
n/a
n/a
n/a
n/a
n/a
3A for 100ns, 200mA DC
3A for 100ns, 200mA DC
3A for 100ns, 200mA DC
1mA
n/a
3A for 100ns, 200mA DC
3A for 100ns, 200mA DC
3A for 100ns, 200mA DC
n/a
n/a
250mA
250mA
1mA
1mA
n/a
n/a
1mA
1mA
1mA
1mA
ISINK
1mA
1mA
1mA
10mA
1mA
1mA
5mA
1mA
20mA
1mA
5mA
n/a
1mA
1mA
250mA
n/a
n/a
1mA
20mA
1mA
n/a
1mA
n/a
n/a
n/a
n/a
n/a
3A for 100ns, 200mA DC
3A for 100ns, 200mA DC
n/a
3A for 100ns, 200mA DC
1mA
3A for 100ns, 200mA DC
3A for 100ns, 200mA DC
n/a
3A for 100ns, 200mA DC
3A for 100ns, 200mA DC
n/a
1mA
1mA
1mA
1mA
n/a
n/a
1mA
1mA
1mA
1mA
06/25/04
IR3092
ELECTRICAL SPECIFICATIONS
Unless otherwise specified, these specifications apply over: 7.3V VCC 21V, 4V VCCL 14V,
o
o
4V VCCHX 28V, CGATEHX =3.3nF, CGATELX =6.8nF, 0 C TJ 125 C
PARAMETER
VDAC Reference
System Set-Point Accuracy
TEST CONDITION
-0.3V 92616- 9&RQQHFW)%WR
EAOUT, Measure V(EAOUT) –
V(VOSNS-) deviation from Table 1.
Applies to all VID codes.
RROSC = 42k9'$& 2&6(7
RROSC = 42k9'$& 2&6(7
VID_SEL=0, Referenced to VOSNSVID_SEL=Float, Referenced to
VOSNS-
MIN
TYP
MAX
0.5
UNIT
%
56
50
0.4
1.3
62
58
0.6
1.5
71
67
0.8
1.7
PA
PA
V
V
1.0
1.2
1.4
V
Tracks ATHLON threshold
V(VID_SEL)3.2V
3.0
2.1
30
60
3.4
2.6
60
190
3.8
3.2
100
375
V
V
k
k
VID0-5 = 1V
Referenced to LGND
Delay to PWRGD assertion
9
4.5
0.5
15
4.9
1.7
27
5.2
4.1
PA
V
Ps
Connect FB to EAOUT, Measure
V(EAOUT)-V(VDAC). From Table 1.
Applies to all VID codes and -0.3V
VOSNS- 91RWH
-5
-1
3
mV
FB Bias Current
DC Gain
Gain-Bandwidth Product
RROSC = 42k
Note 1
Note 1
28
90
4
30.5
100
7
33
105
PA
dB
MHz
Slew Rate
Source Current
Sink Current
Max Voltage
Min Voltage
VDRP Buffer Amplifier
Positioning Offset Voltage
Note 1, 50mV FB signal
280
.75
4.5
1.25
380
1.0
4.9
90
500
1.5
5.3
150
V/Ps
PA
mA
V
mV
-125
0
125
mV
0.2
5
200
10
280
3.75
20
400
V
mA
PA
Source Current
Sink Current
VID Input Threshold, INTEL
VID Input Threshold, AMD
VID_SEL OPTERON
Threshold
VID_SEL ATHLON Threshold
VID_SEL Float Voltage
VID_SEL Pull-up Resistance
VID_SEL Pull-down
Resistance
VID Pull-up Current
VID Float Voltage
VID = 11111 Fault Blanking
Error Amplifier
Input Offset Voltage
Output Voltage Range
Source Current
Sink Current
Page 4 of 37
V(VDRP) – V(VDAC) with
CSINMX=CSINPX=0, Note 1.
06/25/04
IR3092
PARAMETER
Oscillator
Switching Frequency
Phase1 to Phase2 Shift
BIASOUT Regulator
SETBIAS Bias Current
Set Point Accuracy
BIASOUT Dropout Voltage
BIASOUT Current Limit
Soft Start and Delay
SS/DEL to FB Input Offset
Voltage
Charge Current
Hiccup Discharge Current
OC Discharge Current
Charge/Discharge Current
Ratio
Charge Voltage
Delay Comparator Threshold
Delay Comparator Hysteresis
Discharge Comparator
Threshold
Over-Current Comparator
Input Offset Voltage
OCSET Bias Current
Max OCSET Set Point
Under-Voltage Lockout
VCC Start Threshold
VCC Stop Threshold
VCC Hysteresis
5VUVL Start Threshold
5VUVL Stop Threshold
5VUVL Hysteresis
5VUVL Input Resistance
PWRGD Output
Output Voltage
Leakage Current
Enable Input
Threshold, INTEL
Threshold, AMD
Input Resistance
Pull-up Voltage
Page 5 of 37
TEST CONDITION
MIN
TYP
MAX
UNIT
RROSC = 42k
GATEH1 rise to GATEH2 rise
160
155
200
170
240
190
kHz
°
RROSC = 42k
V(SETBIAS)-V(BIASOUT) @ 100mA
I(BIASOUT)=100mA,Threshold when
V(SETBIAS)-V(BIASOUT)=0.45V
105
0.1
1.2
115
0.3
1.8
125
0.55
2.5
PA
V
V
150
300
450
mA
0.8
1.3
1.8
V
25
2.5
25
9
55
5.5
45
10
75
7.5
70
11
PA
PA
PA
PA/PA
3.8
200
15
200
4.0
240
30
260
4.2
280
45
350
V
mV
mV
mV
-125
0
125
mV
28
3.95
30
33
PA
V
7.2
6.7
450
4.05
3.92
100
24
7.8
7.3
500
4.3
4.125
175
36
8.3
7.8
750
4.55
4.33
250
72
V
V
mV
V
V
mV
k
150
0
300
10
mV
PA
0.4
1.3
0.6
1.5
0.8
1.7
V
V
7.5
2.4
15
3.0
20
3.7
k
V
With FB = 0V, adjust V(SS/DEL) until
EAOUT drives high
Relative to Charge Voltage
V(OCSET)-V(VDAC),
CSIN=CSINP1=CSINP2, Note 1.
RROSC = 42k
Start – Stop
Start – Stop
To LGND
I(PWRGD) = 4mA
V(PWRGD) = 5.5V
VID_SEL=0, Referenced to VOSNSVID_SEL=Float, Referenced to
VOSNS-
06/25/04
IR3092
PARAMETER
Gate Drivers
GATEH Rise Time
GATEH Fall Time
GATEL Rise Time
GATEL Fall Time
High Voltage (AC)
Low Voltage (AC)
GATEL low to GATEH high
delay
GATEH low to GATEL high
delay
Disable Pull-Down Current
PWM Comparator
Propagation Delay
TEST CONDITION
VCCHX = 12V, Measure 2V to 9V
transition time, Note 1
VCCHX = 12V, Measure 9V to 2V
transition time, Note 1
VCCL = 12V, Measure 2V to 9V transition
time, Note 1
VCCL = 12V, Measure 9V to 2V transition
time, Note 1
Measure VCCL – GATELX or VCCHX –
GATEHX, Note 1
Measure GATELX or GATEHX, Note 1
VCCHX = VCCL = 12V, Measure the time
from GATELX falling to 2V to GATEHX
rising to 2V, Note 1
VCCHX = VCCL = 12V, Measure the time
from GATEHX falling to 2V to GATELX
rising to 2V, Note 1
GATHX or GATELX=2V with VCC = 0V.
Measure Gate pull-down current
MIN
TYP
MAX
UNIT
11
40
ns
11
40
ns
20
65
ns
20
65
ns
0
0.5V
V
20
0
35
0.5V
60
V
ns
20
35
60
ns
20
35
50
PA
100
150
ns
4
0.9
75
V
VCCHX = VCCL = 12V, Measure the time
from EAOUT fall crossing VDAC to
GATEHX falling to 11V. (Note 1)
Common Mode Input Range
Internal Ramp Start Voltage
Internal Ramp Amplitude
0.45
40
0.7
57
Current Sense Amplifier
CSINP1&2 Bias Current
CSINM Bias Current
Input Current Offset Ratio
Average Input Offset Voltage
Offset Voltage Mismatch
o
Gain at TJ = 25 C
o
Gain at TJ = 125 C
Gain Mismatch
Differential Input Range
Common Mode Input Range
-0.5
-1
0.7
-4
-8
22.0
18.5
-0.3
-25
0
-0.2
-0.4
1.7
0
0
23.5
20.0
0
Page 6 of 37
CSINM/CSINPX
(VDRP-VDAC)/GAIN withCSINX=0, Note1.
Monitor I(SCOMP)
0.1
0.2
2.6
4
8
25.0
24.0
0.3
75
2.8
06/25/04
V
mV /
%DTC
PA
PA
PA/PA
mV
mV
V/V
V/V
V/V
mV
V
IR3092
PARAMETER
Share Adjust Error Amplifier
Input Offset Voltage
MAX Duty Cycle Adjust Ratio
MIN Duty Cycle Adjust Ratio
Transconductance
SCOMP Source/Sink Current
Equal Duty Cycle Comparator
Threshold
Duty Cycle Match at Startup
SCOMP Precharge Current
0% Duty Cycle Comparator
Threshold Voltage
Propagation Delay
Body Braking Disable
Comparator Threshold
OVP
VR10 Comparator Threshold
AMD Comparator Threshold
Propagation Delay
Source Current
Pull Down Resistance
High Voltage
General
VCC Supply Current
VOSNS- Current
VCCHX Supply Current (12V)
VCCHX Supply Current (28V)
VCCL Supply Current
TEST CONDITION
MIN
TYP
MAX
UNIT
Note 1
Duty Cycle of GATEH2 to GATEH1
Duty Cycle of GATEH2 to GATEH1
Note 1
-5
1.5
0.6
100
15
0.45
0
2
0.5
200
28
0.7
5
3
0.4
300
40
0.85
mV
%/%
%/%
PA/V
PA
V
DTC GATEH1 – DTC GATEH2
V(SS/DEL)=0
-5
250
0
420
5
600
%
PA
(Internal Ramp1 Start Voltage) – (0DC
Threshold)
VCCL = 12V. Step EAOUT from .8V to
.3V and measure time to GATELX
transition to < 11V.
Compare V(FB) to V(VDAC)
100
150
200
mV
200
320
ns
50
80
110
mV
VID_SEL=0V. Compare to V(VDAC)
Float VID_SEL. Compare to V(VDAC)
VCCL = 12V. V(EAOUT)=0V. Step FB
460mV above V(VDAC). Measure time
to GATELX transition to >1V.
120
360
145
480
200
180
600
300
mV
mV
ns
10
20
.8
20
45
1.2
80
1.6
mA
k
V
23
2
3
5
5
29
3
5
7
10
34
4
7
9
16
mA
mA
mA
mA
mA
OVP to PGND1
I(OVP)=10mA, V(VCC)-V(OVP)
-0.3V VOSNS- 0.3V, All VID Codes
Note 1: Guaranteed by design, but not tested in production
Note 2: VDAC Output is trimmed to compensate for Error Amp input offsets errors
Page 7 of 37
06/25/04
IR3092
TYPICAL OPERATING CHARACTERISTICS
I(VDAC) Sink and Source Currents vs. ROSC
180
80
160
I(VDAC) Source Current
70
I(FB) in uA
140
I(VDAC) Sink Current
60
I(OCSET) in uA
120
100
50
uA
uA
I(FB) and I(OCSET) Currents vs. ROSC
90
40
80
30
60
20
40
10
20
0
0
10
20
30
40
50
60
70
80
90
100
10
20
30
40
50
60
70
ROSC in Kohms
Oscillator Frequency vs. ROSC
550
500
450
400
350
300
250
200
150
100
50
0
90
100
80
90
100
I(SETBIAS) vs. ROSC
250
200
150
100
50
0
10
20
30
40
50
60
70
ROSC in Kohms
80
90
10
100
20
30
40
50
60
70
ROSC in Kohms
Peak Gate Drive Current vs. Load Capacitance
Frequency and Bias Current Accuracy vs. ROSC (includes
temperature)
4.0
6
3.5
4
Frequency
3
FB Bias
2
OCSET
Bias
SETBIAS
I(GATEX) in Amps
5
+/-3 Sigma Variation (%)
80
300
uA
Frequency in KHz
ROSC in Kohms
3.0
I(RISE)
I(FALL)
2.5
c
2.0
1.5
1
0
1.0
10
20
30
40
50
60
ROSC (KOhm)
Page 8 of 37
70
80
90
100
1
3.5
6
8.5
11
13.5
16
18.5
C(GATEX) in nF
06/25/04
21
IR3092
TYPICAL OPERATING CHARACTERISTICS
Error Amplifier Frequency Response
100
0
-100
93dB DC gain
88° Phase Margin
3.1MHz Crossover
-180
1.0Hz
10Hz
100Hz
DB(V(comp))
P(V(comp))
Page 9 of 37
1.0KHz
10KHz
100KHz
1.0MHz
10MHz 100MHz
Frequency
06/25/04
IR3092
IR3092 THEORY OF OPERATION
IOVP
OVP
ROSC
ON
45k
UVL
VCCH1
IROSC
FB
EAOUT
IROSC
IROSC
IN
-
1.243
OVP Comparator
GATEHI1
GateHI
QB
BB DISABLE COMPARATOR
FB
OL_IN
+
-
-
-
+
AMD=450mV
INTEL=150mV
4.300V START
4.125V STOP
VCCL
IROSC/2
+
-
PWRGD
GATEHI
OL_OUT
RSFF
UVL
5VUVL
R
OL_IN
Q
CLK2
Oscillator
7.8V START
7.3V STOP
BIASOUT
S
+
SETBIAS
RESET DOMINANT
CLK1
+
4 X IROSC
10p
PWM COMPARATOR
80mV
PGND DRIVE
LGND
PGND DRIVE
VCC
IN
0.7V
OL_OUT
GATELO
GATEL1
GateLO
VDAC
PGND1
0% DUTY CYCLE
VDAC
+
-
X25
0.55V
-
+
-
-
+
OFF
-
VDRP
Q
R
F11111
AMD=1.5V
INTEL=0.6V
DAC
OUT
VID4
VID3
VID2
VID0
18uA
VOSNS-
VID1
ATHLON_DAC
OPTERON_DAC
IN
IROSC
FAST DAC
GATEHI
GATEH2
OL_OUT
GateHI
PWM COMPARATOR
VCCL
4.9V
U18
H FORCES IROSC/2 AT SS
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