IRAC11662-100W

User Guide 1.0 IRAC11662-100W +16V Low-side Smart Rectification 100W Flyback Demo Board User’s Guide by HELEN DING, ISRAEL SERRANO 19 April 2010 Rev.1A 19 April 2010 UG #1.0 Page 1 of 24 WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105 http://www.irf.com/ Data and specifications subject to change without notice. Table of Contents 1.0 INTRODUCTION 2.0 GENERAL DESCRIPTION 2.1 IRAC11662-100W +16V Demo Board Schematic Diagram 2.2 IRAC11662-100W +16V Demo Board Pictures 2.3 IRAC11662-100W +16V Demo Board PCB Layout 3.0 Circuit Description 4.0 Test Connection and Set up Pictures 5.0 Circuit Features 5.1 OVT Setting 5.2 ENABLE Setting 5.3 MOT Setting 5.4 Mosfet Selection Design Tips 6.0 Test Waveforms 6.1.1 Transient Load Test 6.1.2 Static Load Test 6.1.3 Ripple And Noise Measurement 6.1.4 Dynamic load Test 7.0 Line / Load Regulation Test 7.1 IR11662 Demo Board V-I Characteristics Curve 7.2 System Efficiency Test 7.3 Thermal Verification 8.0 Summary 9.0 Appendix 9.1 Transformer turns ratio, Duty Cycle and Secondary Current Relationship Chart 9.2 IR11662 100W +16V SR Demo Board Power Transformer Specs 10.0 IRAC11662-100W +16V Demo Board Bill of Materials (BOM) Rev.1A 19 April 2010 UG #1.0 Page 2 of 24 WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105 http://www.irf.com/ Data and specifications subject to change without notice. Page(s) 2 3 3 4 5 6 7 8 9 9 9 9 10 11-17 11-13 14-15 16 17 18 18 19 20 21 21-25 21 22 23-24 1.0 INTRODUCTION Generally, Schottky diodes are traditional devices use in passive rectification in order to have low conduction loss in secondary side for switching power supplies. The proliferations of synchronous rectification (SR) idea - which is mostly use in buck-derive topologies - have reached the domain of flyback application in recent years. The use of low-voltage-low-Rdson mosfet has become so attractive to replace the Schottky rectifiers in high current applications because it offers several system advantages such as dramatic decrease in conduction loss and better thermal management of the whole system by reducing the cost investment in heat sink and PCB space. A number of techniques in the implementation of SR in flyback converters are continuously growing from a simple self-driven (secondary winding voltage detection) to a more complex solution using “current transformer sensing” or combinations of both to improve the existing technology. The idea has become quite complicated though and additional discrete devices have made the cost and part counts issue even worse. Moreover, the issue of reverse current conduction (-due to the delay in sensing the sharp drop of secondary current during turn-off phase of the SR) still lingers on in different input line/ output load conditions. The use of a simple fast-rate-direct-sensing of voltage drop across the mosfet (Vsd) using integrated solution has pave the way for a much simpler and effective means of controlling the SR mosfets as well as alleviating the reverse current and multiple-pulse gate turn-ON issues. The objective of this user guide is to show the advantages of SR application using integrated IC approach and study the practical limits of the efficiency improvements vs. the normal rectification method. 2.0 GENERAL DESCRIPTION The IRAC11662-100W demo board is a universal-input flyback converter with single DC output capable of delivering continuous 100W (@ +16V x 6.25A) during active rectification mode. This demo board is primarily designed to study synchronous rectification using IR11662 in low-side configuration to take advantage of simpler derivation of Vcc supply from converter’s output. It is equipped with necessary jumpers to ease exploring the conduction behavior of synchronous rectifiers SRs in quasi-resonant mode, so discussion would be confined to variable frequency switching in Critical Conduction Mode. It features the fast Vsd sensing of the IR11662 Smart Rectifier Control IC with gate output drive capability of +1A/-4A. It drives 2 pcs. of SRs in parallel (100V N-ch mosfet IRF7853 in SO-8 package with very low Rdson in its class : 18 mΩ max). This had greatly simplified the overall mechanical design for not having those bulky and heavy heat sinks normally seen in high current flyback design using passive rectification. Rev.1A 19 April 2010 UG #1.0 Page 3 of 24 WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105 http://www.irf.com/ Data and specifications subject to change without notice. 6 5 4 3 2 1 2 4 CON1 - + 2 + 2 4 8 7 6 5 J2 Vout-tp Rs14 $ 3 2 1 SR2 4 1 optoK Cs21 10nF $ Rs23 470R 16Vout Vd-P Vd1-P Cs24 100nF + U1 IR1166 5 16Vout Vd 6 LGND EN 7 optoK Vs Vs1 8 VdTP Cs25 2 1 4 - + 32 1 10nf of GND MOT J4 Rev 1A 4 1 Document Number 1950-0808 JUMPER1 1 IRAC1166-100W Schematic Diagram 2 1 Title Rs18 33K OVT Rs20 0 0 Page 4 of 24 3 Checked : ISRAEL SERRANO 10K 2 Vgate LED 2 Vcc Rs21 10K 1 J3 Cs22 *10nF Cs20 47nF Vs 1 0R1 3W 1 2 CS18 100NF 3 Note: * Optional $ Unstuffed # Trimming 1 GNDS Rs22 1K Rp9 1K Sheet Vcc-P 1 1 FB 2 GND 3 COMP 2 J5 5 2 470pF 1kV Q1 IRFP22N60K 3 1k 100nF 100UF/35V Rp12 22R Tuesday, November 28, 2006 U4 AS4305 or AQ105 TP 1 220nf Rp10 CS17 22UF/35V CS 4 2 Rs17 10R Cp7 1 Cp8 VCC G-TP 2 2 Rs24 5.6K Ds5 Ls4148 Rp8 Date: Rs26 Dp5 LS4148 1 Gatedr Rs15 10R VCC 2 16Vout 1 8 7 6 5 Rp9A 12K Cp12 22pf SR1 IRF7853 1 TEA1507 Size Rs25 30m Rp6 910K SR1 2 Rp7 5K1 1 Cp11 4n7 3 2 1 1 Rs16 4K7 Vout-TP VCC DRAIN GND HVS CTRL DRIVER DEM Isns Cp6 4 2 Rp5 0R Rp11 280k U3 SFH615A2 optoK UG #1.0 1 2 3 4 8 7 6 5 J1 1 U2 SR2 IRF7853 2 2 1 3 1 Dp3 Ls4148 1 2 L2 40uH 0 optoA 2 Cp9 22pf Cp5 + Cs19 $ 2 Dp2 BAV103/200V 1 1 2 10uH Cp10 10nf 2 Cp13 1n 5 Cs23 1000UF/25V 1000UF/25V 1 0 Rp4 3K3 Rp3 22R 1500UF/25V 1500UF/25V 2 10 11 12 Cs16 Cs14 Cs15 + + + PQ3535 Dp1 1N5407 L3 Vouttp TP + Rs13 2K2 10R NTC Thermistor 2 1 L1 1uH 8A OptoA 7 8 9 1 Cp3 330UF/400V 1 2 Cp4 4N7/1kV 2 Rp1 19 April 2010 WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105 http://www.irf.com/ Data and specifications subject to change without notice. Cp2 4N7/1kV Rp2 47K 2W 3 FUSE 1 6GBU06 DB1 1 F1 3 T1 1 Cp1 220NF/275V 1 2 3 4 CON2 FIGURE 1. IRAC11662-100W SCHEMATIC DIAGRAM Rev.1A IRAC1166-100W +16V Demo Board Schematic Diagram 2.1 IRAC11662-100W Demo Board Pictures Figure 2A. Top side of the IRAC11662-100W Demo Board Figure 2B. Bottom side of the IRAC11662-100W Demo Board - - ++ AC Input Rev.1A 19 April 2010 +16 V x 6.25A Output UG #1.0 Page 5 of 24 WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105 http://www.irf.com/ Data and specifications subject to change without notice. 2.2 PCB Layout for IRAC11662-100W Figure 3A. Top layer etch with silkscreen print Figure 3B. Bottom layer etch with silkscreen print. Rev.1A 19 April 2010 UG #1.0 Page 6 of 24 WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105 http://www.irf.com/ Data and specifications subject to change without notice. 3.0 CIRCUIT DESCRIPTION The PCB design is basically optimized as a test platform to evaluate of active rectification using Smart synchronous rectification and as well as basic features of flyback converter operating in quasi-resonant mode. This demo board has 2-pin connector ( CON1 ) for AC input and a time-lag type 3.5A fuse for input current overload protection. Minimum input filtering is provided (Cp1-Xcap) before AC input voltage (90-264VAC) is routed to a 6Amp-bridge rectifier (DB1). Primary side controller (U2) basically drives the primary Mosfet Q1 to operate in CriticalConduction mode to eliminate turn-ON switching loss thru ZVS (zero voltage switching only occurs when NVsec > Vdcin ) or thru LVS ( low-voltage switching when nVsec< Vdcin) to reduce capacitive losses of Q1 especially at high line condition. The switching frequency Fsw at full load varies from ~38 to ~84kHz typically from low to high input condition and falls back to minimum value (fixed ~ 6 -10kHz) to reduce input power during light load condition. Auxiliary winding is loosely monitored by demagnetization pin4 of U2 through Dp3, Rp5 and Rp11 network that sets the OVP limit with Rp6 and Rp11 sets the over power limit of the converter. Optocoupler U3 provides isolated output voltage feedback to the primary side. The output voltage level across load connector CON2 (+16Vo) is monitored and regulated by the V/I Secondary error amplifier U4 (AQ105 or AS4305) that also manages the output current limiting function by monitoring the voltage across the RS25-26 current sense resistors. The power stage of the secondary is using 2-SO8 low IRF7853 synch-fets (SR) in parallel to implement the low-side synchronous rectification. In this configuration, it is simpler to derive the Vcc supply for the U1 (IR11662 SO8-IC) controller directly from the DC output Vout. Jumper J5 is used to isolate U1’s Vcc from Vout so that user may easily evaluate IC’s power consumption especially during standby load condition. In the absence of a sensitive low current probe, the quiescent current Icc through Dp4 can be calculated from the differential voltage across the Rs17. The decoupling capacitor Cs17 and Cs18 provides additional filtering which is necessary to clean high frequency noise especially when U1 is driving several mosfets (SR1 // SR2) with high Qg parameters normally associated with high currentlow voltage mosfets. The Vd and Vs sense pins monitor the voltage (Vsd) across the sync rect mosfets and proper attention was taken during PCB routing to ensure the integrity of differential voltage Vsd. This is done by directly taking the signal Vd from the drain pins of SR1//SR2 using a dedicated trace. Probe points as well as redundant test hook points are provided to facilitate easy probing of essential test waveforms. Rev.1A 19 April 2010 UG #1.0 Page 7 of 24 WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105 http://www.irf.com/ Data and specifications subject to change without notice. 4.0 TEST CONNECTION AND SETUP DIAGRAM 4.1 Recommended setup for Voltage and Current probing Fig. 4A Direct gate voltage probing using tip & gnd spring. Fig. 4B Recommended probing of secondary current waveform. Rev.1A 19 April 2010 Fig. 4C Connecting O-scope probe to hook Gate drive test points. Fig. 4D Recommended probing of Vout’s Ripple & Noise voltage. UG #1.0 Page 8 of 24 WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105 http://www.irf.com/ Data and specifications subject to change without notice. 5.0 CIRCUIT FEATURES 5.1 OVT setting: The Offset Voltage Threshold can be easily selected by changing the position of jumper J3 according to system mode of operation as shown on Table 1 below. Since the demo board is practically designed to operate in Critical conduction mode, OVT pin can be left floating or grounded to prolong the MOSFET’s channel conduction period a bit compared to connecting it to Vcc. As a result, this would give the advantage of further reducing the conduction period of the MOSFET’s (SR1 & SR2) body diode, thus achieving more efficient operation. Reducing the chance of having reverse current during the fast turn-off phase of the sync-fets is another strong reason for having this feature available. Table 1 System mode of operation OVT connected to DCM or CrCM Ground, VTH1= -3.5mV Boundary CCM Floating, VTH1= -10.5mV CCM VCC, VTH1= -19.0 mV The general observation during light load condition (~10-20% full load) is that a ~0.5 to ~1.2% efficiency improvement was seen for OVT=Gnd compared to OVT=floating. This small difference is no longer significant when the load becomes heavy for CrCM operation. 5.2 Enable setting: The IC is enabled by default knowing that EN pin is tied internally to VCC through a resistor. Having a jumper on J4 location will connect EN pin to Gnd and will immediately disable the internal gate drive circuit of the IR11662 IC. By putting a jumper J4 in/out would help the user to quickly evaluate the effect in efficiency by investigating the change in input power as a result of having SR fets working compared to just having an ordinary passive rectification offered by the body diode(s) when the gate drive is disabled. CAUTION : This demo board is basically designed for evaluation of functionality of IR11662 IC. The users may disable the IC by shorting J4 EN to GND for quick testing at full load but with care should be taken. It is strongly advise not to load more than 4.6 - 6Amp with IR11662 disabled for a prolong period of time (>1min). This is to prevent damaging the MOSFET’s body diode due to overheating when the load current passes through the mosfets’ body diode while SRs are turned-OFF. Never power-up the unit without shorting J5. 5.3 Minimum ON Time (MOT) setting: MOT setting is used to de-sensitize the IC from multiple change in Vsd during the turn-ON phase of SRs which is cause by the ringing of the secondary winding voltage (Vsec). MOT can be adjusted through Rs18 (according to AN1087 simplified equation RMOT =2.5x1010*tmot ) and is chosen to be 1.2us which is usually enough to ignore the parasitic noises at Vsd in a quasi-resonant switching converters such as this demo board. Rev.1A 19 April 2010 UG #1.0 Page 9 of 24 WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105 http://www.irf.com/ Data and specifications subject to change without notice. 5.4 Mosfet Selection Design Tips Application note AN1087 has made it easy to understand the calculations required in flyback sync-rect driving circuits using IR116x series ICs. Choosing the right mosfet(s) to satisfy the performance–cost requirement of any sync rect design should be simple as well. Voltage rating: SRs should also follow similar equation in most flyback design as shown below: Vsd > k*[Vo +(VDCinmax /(Npri/Nsec) )] where k =1.1 to 1.4 as a guard band for startup stress due to leakage spike. RdsON rating: Generally, it is easy to meet >1% system efficiency improvement if the conduction loss of the SRs becomes twice smaller than normal passive rectification approach. This is to achieve better thermal performance especially if the designer wishes to consider not having too bulky and heavy heatsink in the design, but take note that it would still be largely dependent on the size PCB copper area allotted to the SRs. We should also consider the estimated Rdson at 25˚C (normally shown in the datasheet) would be approximately ~1.8 times higher at Tj=125˚C. As a rule of thumb, we will base our calculation on these assumptions to simplify the mosfet selection criteria. For typical 100V Schottky rectifiers, Vf is around ~ 600 mV ( @Tj=125˚C), so in this case we should find a 100-V mosfet(s) with lower Rdson which will have a ~150mV max Vsd at rated full load current (Ioave). For quick estimation of Isecrms, designer might find Fig. 9.1 useful to quickly estimate Isecrms since Ioave is normally given as standard design specs. Calculating the rms value of secondary current is easier for CrCM mode where D = N*Vsec/ (N*Vsec + Vdcinmin) N=Npri / Nsec , N = 31/5 eqn. 1 Let Vsec =16.1, Vdcmin=100, D= ~50% h = Vf (Schottkydiode) / Vsd(mosfet ) eqn.2 Pdis SR < 1/h* Vfdiode* Ioave eqn.3 With h > 2, Target VSD(@Tj=125˚C) ≤ 600mV / 2 ≤ 300mV 2 I secrms*RdsON (@Tj=125˚C) ≤ 300 mV*Ioave eqn.4 RdsON (@Tj=125˚C) = ~1.8*RdsON (@Tj=25˚C) I sec rms = Rev.1A 2 Ioave (1 − D ) / 3 (1 − D ) 19 April 2010 eqn.5 eqn.6 Combining equations 4, 5, and 6 RDSON @ Tj = 25C RDSON ≤ ≤ 166mV [ 3(1 − D )] 4 Ioave eqn.7 0.125 * (50%) 0.125 * 0.5 = = 0.010Ω 6.25 Ioave RdsON @Tj=25˚C ≤ 10 mΩ We can use 2-SO8 mosfets (IRF7853) in parallel having equivalent RdsON (@Tj=25˚C) of ~9 mΩ. Note : Vsd(@Tj=125˚C)