StrongIRFET™
IRFS7534-7PPbF
HEXFET® Power MOSFET
Application
Brushed motor drive applications
BLDC motor drive applications
Battery powered circuits
Half-bridge and full-bridge topologies
Synchronous rectifier applications
Resonant mode power supplies
OR-ing and redundant power switches
DC/DC and AC/DC converters
DC/AC inverters
VDSS
60V
RDS(on) typ.
1.60m
max
1.95m
D
G
S
ID (Silicon Limited)
255A
ID (Package Limited)
240A
Benefits
Improved gate, avalanche and dynamic dV/dt ruggedness
Fully characterized capacitance and avalanche SOA
Enhanced body diode dV/dt and dI/dt capability
Lead-free, RoHS compliant
G
Gate
Package Type
IRFS7534-7PPbF
D2Pak-7PIN
Standard Pack
Form
Quantity
Tube
50
Tape and Reel Left
800
8
Complete Part Number
IRFS7534-7PPbF
IRFS7534TRL7PP
Limited By Package
250
6
T J = 125°C
4
2
200
150
100
50
T J = 25°C
0
0
4
6
8
10
12
14
16
18
20
VGS, Gate -to -Source Voltage (V)
Fig 1. Typical On-Resistance vs. Gate Voltage
1
S
Source
300
ID = 100A
ID, Drain Current (A)
RDS(on), Drain-to -Source On Resistance (m )
Base Part Number
D
Drain
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25
50
75
100
125
150
175
T C , Case Temperature (°C)
Fig 2. Maximum Drain Current vs. Case Temperature
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IRFS7534-7PPbF
Absolute Maximum Rating
Symbol
ID @ TC = 25°C
ID @ TC = 100°C
ID @ TC = 25°C
IDM
PD @TC = 25°C
VGS
TJ
TSTG
Parameter
Continuous Drain Current, VGS @ 10V (Silicon Limited)
Continuous Drain Current, VGS @ 10V (Silicon Limited)
Continuous Drain Current, VGS @ 10V (Package Limited)
Pulsed Drain Current
Maximum Power Dissipation
Linear Derating Factor
Gate-to-Source Voltage
Operating Junction and
Storage Temperature Range
Soldering Temperature, for 10 seconds (1.6mm from case)
Max.
255
180
240
790
290
2.0
± 20
Units
A
W
W/°C
V
-55 to + 175
°C
300
Avalanche Characteristics
Symbol
Parameter
EAS (Thermally limited)
Single Pulse Avalanche Energy
EAS (Thermally limited)
Single Pulse Avalanche Energy
IAR
Avalanche Current
Repetitive Avalanche Energy
EAR
Thermal Resistance
Symbol
Parameter
Junction-to-Case
RJC
Junction-to-Ambient
RJA
Static @ TJ = 25°C (unless otherwise specified)
Symbol
Parameter
V(BR)DSS
Drain-to-Source Breakdown Voltage
V(BR)DSS/TJ Breakdown Voltage Temp. Coefficient
RDS(on)
Static Drain-to-Source On-Resistance
VGS(th)
IDSS
Gate Threshold Voltage
Drain-to-Source Leakage Current
IGSS
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Gate Resistance
RG
Max
370
773
Units
mJ
See Fig 15, 16, 23a, 23b
Typ.
–––
–––
Min.
60
–––
–––
–––
2.1
–––
–––
–––
–––
–––
Max.
0.51
40
A
mJ
Units
°C/W
Typ. Max. Units
Conditions
––– –––
V
VGS = 0V, ID = 250µA
46
––– mV/°C Reference to 25°C, ID = 1mA
1.60 1.95
VGS = 10V, ID = 100A
m
2.00 –––
VGS = 6.0V, ID = 50A
–––
3.7
V
VDS = VGS, ID = 250µA
–––
1.0
VDS = 60V, VGS = 0V
µA
––– 150
VDS = 60V,VGS = 0V,TJ =125°C
––– 100
VGS = 20V
nA
––– -100
VGS = -20V
1.9
–––
Notes:
Calculated continuous current based on maximum allowable junction temperature. Bond wire current limit is 240A.
Note that current limitations arising from heating of the device leads may occur with some lead mounting
arrangements. (Refer to AN-1140)
Repetitive rating; pulse width limited by max. junction temperature.
Limited by TJmax, starting TJ = 25°C, L = 74µH, RG = 50, IAS = 100A, VGS =10V.
ISD 100A, di/dt 1240A/µs, VDD V(BR)DSS, TJ 175°C.
Pulse width 400µs; duty cycle 2%.
Coss eff. (TR) is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 80% VDSS.
Coss eff. (ER) is a fixed capacitance that gives the same energy as Coss while VDS is rising from 0 to 80% VDSS.
R is measured at TJ approximately 90°C.
Limited by TJmax, starting TJ = 25°C, L = 1mH, RG = 50, IAS = 39A, VGS =10V.
When mounted on 1" square PCB (FR-4 or G-10 Material). For recommended footprint and soldering techniques
refer to application note #AN-994.please refer to application note to AN-994:
http://www.irf.com/technical-info/appnotes/an-994.pdf
2
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IRFS7534-7PPbF
Dynamic Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
Symbol
gfs
Qg
Qgs
Qgd
Qsync
td(on)
tr
Parameter
Forward Transconductance
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain Charge
Total Gate Charge Sync. (Qg - Qgd)
Turn-On Delay Time
Rise Time
Min.
190
–––
–––
–––
–––
–––
–––
Typ. Max. Units
Conditions
––– –––
S VDS = 10V, ID =100A
200 300
ID = 100A
50
–––
VDS = 30V
nC
59
–––
VGS = 10V
141 –––
140 –––
VDD = 30V
ID = 100A
120 –––
ns
195 –––
RG= 2.7
VGS = 10V
86
–––
td(off)
Turn-Off Delay Time
–––
tf
Ciss
Coss
Crss
Fall Time
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
–––
–––
–––
–––
Coss eff.(ER)
Effective Output Capacitance (Energy Related)
–––
900
–––
VGS = 0V, VDS = 0V to 48V
Coss eff.(TR)
Output Capacitance (Time Related)
–––
1150
–––
VGS = 0V, VDS = 0V to 48V
Parameter
Continuous Source Current
(Body Diode)
Pulsed Source Current
(Body Diode)
Min.
Typ. Max. Units
–––
––– 255
–––
–––
790
VSD
Diode Forward Voltage
–––
–––
1.2
dv/dt
Peak Diode Recovery dv/dt
trr
Reverse Recovery Time
Qrr
Reverse Recovery Charge
IRRM
Reverse Recovery Current
–––
–––
–––
–––
–––
–––
9.4
45
48
64
78
2.4
–––
–––
–––
–––
–––
–––
9990
915
590
–––
–––
–––
VGS = 0V
VDS = 25V
pF ƒ = 1.0MHz
Diode Characteristics
Symbol
IS
ISM
3
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A
V
Conditions
MOSFET symbol
showing the
integral reverse
p-n junction diode.
D
G
S
TJ = 25°C,IS = 100A,VGS = 0V
V/ns TJ = 175°C,IS =100A,VDS = 60V
TJ = 25°C
VDD = 51V
ns
TJ = 125°C
IF = 100A,
TJ = 25°C di/dt = 100A/µs
nC
TJ = 125°C
A TJ = 25°C
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IRFS7534-7PPbF
1000
1000
ID, Drain-to-Source Current (A)
100
BOTTOM
10
TOP
ID, Drain-to-Source Current (A)
TOP
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
4.5V
100
1
4.5V
0.1
60µs PULSE WIDTH
BOTTOM
4.5V
10
60µs PULSE WIDTH
Tj = 175°C
Tj = 25°C
1
0.01
0.1
1
10
100
0.1
1000
1000
100
1000
2.5
RDS(on) , Drain-to-Source On Resistance
(Normalized)
ID, Drain-to-Source Current (A)
10
Fig 4. Typical Output Characteristics
Fig 3. Typical Output Characteristics
100
T J = 175°C
10
T J = 25°C
1
VDS = 25V
60µs PULSE WIDTH
0.1
ID = 100A
VGS = 10V
2.0
1.5
1.0
0.5
2.0
3.0
4.0
5.0
6.0
7.0
8.0
-60 -40 -20 0 20 40 60 80 100120140160180
VGS, Gate-to-Source Voltage (V)
T J , Junction Temperature (°C)
Fig 5. Typical Transfer Characteristics
100000
Fig 6. Normalized On-Resistance vs. Temperature
14.0
VGS = 0V,
f = 1 MHZ
C iss = C gs + C gd, C ds SHORTED
VGS, Gate-to-Source Voltage (V)
C rss = C gd
C oss = C ds + C gd
C, Capacitance (pF)
1
V DS, Drain-to-Source Voltage (V)
V DS, Drain-to-Source Voltage (V)
Ciss
10000
Coss
Crss
1000
ID= 100A
12.0
VDS= 48V
VDS= 30V
10.0
VDS= 12V
8.0
6.0
4.0
2.0
0.0
100
1
10
100
VDS, Drain-to-Source Voltage (V)
Fig 7. Typical Capacitance vs.
Drain-to-Source Voltage
4
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
4.5V
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0
50
100
150
200
250
QG, Total Gate Charge (nC)
Fig 8. Typical Gate Charge vs.
Gate-to-Source Voltage
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IRFS7534-7PPbF
1000
100µsec
ID, Drain-to-Source Current (A)
ISD, Reverse Drain Current (A)
1msec
T J = 175°C
100
T J = 25°C
10
1
100
Limited by
package
OPERATION
IN THIS
AREA
LIMITED BY
RDS(on)
10
10msec
1
Tc = 25°C
Tj = 175°C
Single Pulse
VGS = 0V
0.1
0.1
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
0.1
VSD, Source-to-Drain Voltage (V)
1
10
VDS, Drain-toSource Voltage (V)
Fig 9. Typical Source-Drain Diode Forward Voltage
Fig 10. Maximum Safe Operating Area
1.6
78
Id = 1.0mA
76
1.2
74
Energy (µJ)
V(BR)DSS , Drain-to-Source Breakdown Voltage (V)
DC
72
70
68
0.8
0.4
66
0.0
64
-10
-60 -40 -20 0 20 40 60 80 100120140160180
T J , Temperature ( °C )
10
20
30
40
50
60
VDS, Drain-to-Source Voltage (V)
Fig 11. Drain-to-Source Breakdown Voltage
RDS(on), Drain-to -Source On Resistance ( m)
0
Fig 12. Typical Coss Stored Energy
4.0
Vgs = 5.5V
Vgs = 6.0V
Vgs = 7.0V
Vgs = 8.0V
Vgs = 10V
3.5
3.0
2.5
2.0
1.5
0
20 40 60 80 100 120 140 160 180 200
ID, Drain Current (A)
Fig 13. Typical On-Resistance vs. Drain Current
5
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IRFS7534-7PPbF
Thermal Response ( Z thJC ) °C/W
1
D = 0.50
0.20
0.10
0.1
0.05
0.02
0.01
0.01
0.001
SINGLE PULSE
( THERMAL RESPONSE )
0.0001
1E-006
1E-005
0.0001
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
0.001
0.01
0.1
1
t1 , Rectangular Pulse Duration (sec)
Fig 14. Maximum Effective Transient Thermal Impedance, Junction-to-Case
1000
Avalanche Current (A)
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming Tj = 150°C and
Tstart =25°C (Single Pulse)
100
10
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming j = 25°C and
Tstart = 150°C.
1
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
tav (sec)
Fig 15. Avalanche Current vs. Pulse width
EAR , Avalanche Energy (mJ)
400
TOP
Single Pulse
BOTTOM 1.0% Duty Cycle
ID = 100A
300
200
100
0
25
50
75
100
125
150
175
Starting T J , Junction Temperature (°C)
Fig 16. Maximum Avalanche Energy vs. Temperature
6
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Notes on Repetitive Avalanche Curves , Figures 15, 16:
(For further info, see AN-1005 at www.irf.com)
1.Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a
temperature far in excess of Tjmax. This is validated for every
part type.
2. Safe operation in Avalanche is allowed as long asTjmax is not
exceeded.
3. Equation below based on circuit and waveforms shown in Figures
23a, 23b.
4. PD (ave) = Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage
increase during avalanche).
6. Iav = Allowable avalanche current.
7. T = Allowable rise in junction temperature, not to exceed Tjmax
(assumed as 25°C in Figure 15, 16).
tav = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
ZthJC(D, tav) = Transient thermal resistance, see Figures 13)
PD (ave) = 1/2 ( 1.3·BV·Iav) = T/ ZthJC
Iav = 2T/ [1.3·BV·Zth]
EAS (AR) = PD (ave)·tav
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IRFS7534-7PPbF
20
IF = 60A
V R = 51V
TJ = 25°C
3.5
15
3.0
TJ = 125°C
2.5
IRRM (A)
VGS(th) , Gate threshold Voltage (V)
4.0
ID = 250µA
ID = 1.0mA
ID = 1.0A
2.0
1.5
10
5
1.0
0.5
0
-75 -50 -25
0
25 50 75 100 125 150 175
0
200
T J , Temperature ( °C )
600
800
1000
diF /dt (A/µs)
Fig 17. Threshold Voltage vs. Temperature
Fig 18. Typical Recovery Current vs. dif/dt
20
400
IF = 100A
V R = 51V
TJ = 25°C
TJ = 125°C
IF = 60A
V R = 51V
TJ = 25°C
300
TJ = 125°C
QRR (nC)
15
IRRM (A)
400
10
5
200
100
0
0
0
200
400
600
800
1000
0
200
diF /dt (A/µs)
400
600
800
1000
diF /dt (A/µs)
Fig 20. Typical Stored Charge vs. dif/dt
Fig 19. Typical Recovery Current vs. dif/dt
400
IF = 100A
V R = 51V
TJ = 25°C
300
QRR (nC)
TJ = 125°C
200
100
0
0
200
400
600
800
1000
diF /dt (A/µs)
Fig 21. Typical Stored Charge vs. dif/dt
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IRFS7534-7PPbF
Fig 22. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET® Power MOSFETs
V(BR)DSS
tp
15V
L
VDS
D.U.T
RG
IAS
20V
tp
DRIVER
+
V
- DD
A
I AS
0.01
Fig 23a. Unclamped Inductive Test Circuit
Fig 23b. Unclamped Inductive Waveforms
Fig 24a. Switching Time Test Circuit
Fig 24b. Switching Time Waveforms
Id
Vds
Vgs
VDD
Vgs(th)
Qgs1 Qgs2
Fig 25a. Gate Charge Test Circuit
8
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Qgd
Qgodr
Fig 25b. Gate Charge Waveform
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IRFS7534-7PPbF
D2Pak-7Pin Package Outline (Dimensions are shown in millimeters (inches))
Note: For the most current drawing please refer to IR website at http://www.irf.com/package/
9
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IRFS7534-7PPbF
D2Pak-7Pin Part Marking Information
D2Pak-7Pin Tape and Reel
Note: For the most current drawing please refer to IR website at http://www.irf.com/package/
10
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IRFS7534-7PPbF
Qualification Information†
Industrial
(per JEDEC JESD47F) ††
Qualification Level
Moisture Sensitivity Level
D2Pak-7Pin
MSL1
Yes
RoHS Compliant
†
Qualification standards can be found at International Rectifier’s web site: http://www.irf.com/product-info/reliability/
††
Applicable version of JEDEC standard at the time of product release.
Revision History
Date
11/5/2014
Comments
Updated EAS (L =1mH) = 773mJ on page 2
Updated note 9 “Limited by TJmax, starting TJ = 25°C, L = 1mH, RG = 50, IAS = 39A, VGS =10V” on page 2
IR WORLD HEADQUARTERS: 101 N. Sepulveda Blvd., El Segundo, California 90245, USA
To contact International Rectifier, please visit http://www.irf.com/whoto-call/
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IMPORTANT NOTICE
The information given in this document shall in no
event be regarded as a guarantee of conditions or
characteristics (“Beschaffenheitsgarantie”) .
With respect to any examples, hints or any typical
values stated herein and/or any information
regarding the application of the product, Infineon
Technologies hereby disclaims any and all
warranties and liabilities of any kind, including
without limitation warranties of non-infringement
of intellectual property rights of any third party.
In addition, any information given in this document
is subject to customer’s compliance with its
obligations stated in this document and any
applicable legal requirements, norms and
standards concerning customer’s products and any
use of the product of Infineon Technologies in
customer’s applications.
The data contained in this document is exclusively
intended for technically trained staff. It is the
responsibility of customer’s technical departments
to evaluate the suitability of the product for the
intended application and the completeness of the
product information given in this document with
respect to such application.
For further information on the product, technology,
delivery terms and conditions and prices please
contact your nearest Infineon Technologies office
(www.infineon.com).
WARNINGS
Due to technical requirements products may
contain dangerous substances. For information on
the types in question please contact your nearest
Infineon Technologies office.
Except as otherwise explicitly approved by Infineon
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authorized
representatives
of
Infineon
Technologies, Infineon Technologies’ products may
not be used in any applications where a failure of
the product or any consequences of the use thereof
can reasonably be expected to result in personal
injury.