TLE42744GV33ATMA1

TLE42744 Low Dropout Linear Voltage Regulator T LE42744DV50 T LE42744GV50 T LE42744EV50 T LE42744GV33 T LE42744DV33 T LE42744GSV33 Data Sheet Rev. 1.2, 2014-07-03 Automotive Power Low Dropout Linear Voltage Regulator 1 TLE42744 Overview Features • Very Low Current Consumption • Output Voltages 5 V and 3.3 V ±2% • Output Current up to 400 mA • Very Low Dropout Voltage • Output Current Limitation • Reverse Polarity Protection • Overtemperature Shutdown • Wide Temperature Range From -40 °C up to 150 °C • Green Product (RoHS compliant) • AEC Qualified PG-TO252-3 PG-SSOP-14 exposed pad PG-TO263-3 PG-SOT223-4 Description The TLE42744 is a monolithic integrated low dropout voltage regulator for load currents up to 400 mA. An input voltage up to 40 V is regulated to VQ,nom = 5 V / 3.3 V with a precision of ±2%. The device is designed for the harsh environment of automotive applications. Therefore it is protected against overload, short circuit and overtemperature conditions by the implemented output current limitation and the overtemperature shutdown circuit. The TLE42744 can be also used in all other applications requiring a stabilized 5 V / 3.3 V voltage. Due to its very low quiescent current the TLE42744 is dedicated for use in applications permanently connected to VBAT. Type Package Marking TLE42744DV50 PG-TO252-3 42744V5 TLE42744GV50 PG-TO263-3 42744V5 TLE42744EV50 PG-SSOP-14 exposed pad 42744V5 TLE42744DV33 PG-TO252-3 42744V33 TLE42744GV33 PG-TO263-3 42744V33 TLE42744GSV33 PG-SOT223-4 42744V33 Data Sheet 2 Rev. 1.2, 2014-07-03 TLE42744 Block Diagram 2 Block Diagram Saturation Control and Protection Circuit Temperature Sensor Ι Q Control Amplifier Buffer Bandgap Reference GND AEB01959 Figure 1 Data Sheet Block Diagram 3 Rev. 1.2, 2014-07-03 TLE42744 Pin Configuration 3 Pin Configuration 3.1 Pin Assignment PG-TO252-3, PG-TO263-3 and PG-SOT223-4 GND 4 GND 1 3 1 I Ι Q Ι GND Q AEP02561 2 GND 3 Q PinConfig_PG-SOT2234.vsd AEP02281 Figure 2 Pin Configuration (top view) 3.2 Pin Definitions and Functions PG-TO252-3, PG-TO263-3 and PG-SOT223-4 Pin No. Symbol Function 1 I Input block to ground directly at the IC with a ceramic capacitor 2 GND Ground internally connected to heat slug 3 Q Output block to ground with a capacitor close to the IC terminals, respecting the values given for its capacitance and ESR in “Functional Range” on Page 6 4 / Heat Slug – Heat Slug internally connected to GND; connect to GND and heatsink area Data Sheet 4 Rev. 1.2, 2014-07-03 TLE42744 Pin Configuration 3.3 Pin Assignment PG-SSOP-14 exposed pad n.c. n.c. 1 14 2 13 n.c. I n.c. 3 12 n.c. GND 4 11 n.c. n.c. 5 10 n.c. n.c. 6 9 Q n.c. 7 8 n.c. TLE7274-2_PINCONFIG_SSOP14.SVG Figure 3 Pin Configuration (top view) 3.4 Pin Definitions and Functions PG-SSOP-14 exposed pad Pin No. Symbol Function 1, 2, 3, 5, 6, 7 n.c. Not connected can be open or connected to GND 4 GND Ground 8, 10, 11, 12, 14 n.c. Not connected can be open or connected to GND 9 Q Output block to ground with a capacitor close to the IC terminals, respecting the values given for its capacitance and ESR in “Functional Range” on Page 6 13 I Input block to ground directly at the IC with a ceramic capacitor Pad – Exposed Pad connect to GND and heatsink area Data Sheet 5 Rev. 1.2, 2014-07-03 TLE42744 General Product Characteristics 4 General Product Characteristics 4.1 Absolute Maximum Ratings Table 1 Absolute Maximum Ratings1) Tj = -40 °C to 150 °C; all voltages with respect to ground, (unless otherwise specified) Parameter Symbol Values Unit Note / Test Condition Number Min. Typ. Max. VI -42 – 45 V – P_4.1.1 VQ -1 – 40 V – P_4.1.2 Tj Tstg -40 – 150 °C – P_4.1.3 -50 – 150 °C – P_4.1.4 ESD Absorption VESD,HBM -4 – 4 kV Human Body Model (HBM)2) P_4.1.5 ESD Absorption VESD,CDM -1000 – 1000 V Charge Device Model (CDM)3) at all pins P_4.1.6 Input I Voltage Output Q Voltage Temperature Junction temperature Storage temperature ESD Susceptibility 1) not subject to production test, specified by design 2) ESD susceptibility Human Body Model “HBM” according to AEC-Q100-002 - JESD22-A114 3) ESD susceptibility Charged Device Model “CDM” according to ESDA STM5.3.1 Notes 1. Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. Integrated protection functions are designed to prevent IC destruction under fault conditions described in the data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are not designed for continuous repetitive operation. 4.2 Functional Range Table 2 Functional Range Parameter Symbol Values Min. Typ. Max. Unit Note / Test Condition Number Input voltage VI 5.5 – 40 V TLE42744DV50, TLE42744GV50, TLE42744EV50 P_4.2.1 Input voltage VI 4.7 – 40 V TLE42744GV33, TLE42744DV33, TLE42744GSV33 P_4.2.2 Data Sheet 6 Rev. 1.2, 2014-07-03 TLE42744 General Product Characteristics Table 2 Functional Range (cont’d) Parameter Symbol Values Min. Unit Note / Test Condition Number Typ. Max. Output Capacitor’s Requirements for Stability CQ 22 – µF 1) P_4.2.3 Output Capacitor’s Requirements for Stability ESR(CQ) – 3 Ω 2) P_4.2.4 Junction temperature Tj -40 150 °C – P_4.2.5 1) the minimum output capacitance requirement is applicable for a worst case capacitance tolerance of 30% 2) relevant ESR value at f = 10 kHz Note: Within the functional or operating range, the IC operates as described in the circuit description. The electrical characteristics are specified within the conditions given in the Electrical Characteristics table. 4.3 Thermal Resistance Note: This thermal data was generated in accordance with JEDEC JESD51 standards. For more information, go to www.jedec.org. Table 3 Thermal Resistance Parameter Symbol Values Unit Note / Test Condition Number K/W measured to heat slug P_4.3.1 Min. Typ. Max. TLE42744DV50, TLE42744DV33 (PG-TO252-3) Junction to Case1) RthJC RthJA RthJA – Junction to Ambient1) Junction to Ambient1) Junction to Ambient 1) Junction to Ambient 1) 3.6 – 2) – 27 – K/W FR4 2s2p board P_4.3.2 – 115 – K/W FR4 1s0p board, footprint only3) P_4.3.3 RthJA – 52 – K/W FR4 1s0p board, 300 mm² heatsink area3) P_4.3.4 RthJA – 40 – K/W FR4 1s0p board, 600 mm² heatsink area3) P_4.3.5 3.6 – K/W measured to heat slug P_4.3.6 TLE42744GV50, TLE42744GV33 (PG-TO263-3) Junction to Case1) RthJC RthJA RthJA – Junction to Ambient1) Junction to Ambient1) Junction to Ambient 1) Junction to Ambient 1) Data Sheet 2) – 22 – K/W FR4 2s2p board – 74 – K/W FR4 1s0p board, footprint only3) P_4.3.8 RthJA – 42 – K/W FR4 1s0p board, 300 mm² heatsink area3) P_4.3.9 RthJA – 34 – K/W FR4 1s0p board, 600 mm² heatsink area3) P_4.3.10 7 P_4.3.7 Rev. 1.2, 2014-07-03 TLE42744 General Product Characteristics Table 3 Thermal Resistance (cont’d) Parameter Symbol Values Unit Note / Test Condition Number Min. Typ. Max. TLE42744EV50 (PG-SSOP-14 exposed pad) Junction to Case1) RthJC – 7 – K/W measured to exposed pad P_4.3.11 Junction to Ambient1) RthJA RthJA – 43 – K/W FR4 2s2p board2) P_4.3.12 – 120 – K/W FR4 1s0p board, footprint only3) P_4.3.13 Junction to Ambient1) RthJA – 59 – K/W FR4 1s0p board, 300 mm² heatsink area3) P_4.3.14 Junction to Ambient1) RthJA – 49 – K/W FR4 1s0p board, 600 mm² heatsink area3) P_4.3.15 – 17 – K/W measured to heat slug P_4.3.16 – 54 – K/W FR4 2s2p board2) P_4.3.17 Junction to Ambient1) RthJC RthJA RthJA – 139 – K/W FR4 1s0p board, footprint only3) P_4.3.18 Junction to Ambient1) RthJA – 73 – K/W FR4 1s0p board, 300 mm² heatsink area3) P_4.3.19 Junction to Ambient1) RthJA – 64 – K/W FR4 1s0p board, 600 mm² heatsink area3) P_4.3.20 Junction to Ambient 1) TLE42744GSV33 (PG-SOT223-4) Junction to Case1) Junction to Ambient1) 1) Not subject to production test, specified by design. 2) Specified RthJA value is according to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board; The Product (Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm³ board with 2 inner copper layers (2 x 70µm Cu, 2 x 35µm Cu). Where applicable a thermal via array under the exposed pad contacted the first inner copper layer. 3) Specified RthJA value is according to Jedec JESD 51-3 at natural convection on FR4 1s0p board; The Product (Chip+Package) was simulated on a 76.2 × 114.3 × 1.5 mm3 board with 1 copper layer (1 x 70µm Cu). Data Sheet 8 Rev. 1.2, 2014-07-03 TLE42744 Electrical Characteristics 5 Electrical Characteristics 5.1 Electrical Characteristics Voltage Regulator Table 4 Electrical Characteristics VI =13.5 V; Tj = -40 °C to 150 °C; all voltages with respect to ground (unless otherwise specified) Parameter Symbol Values Min. Typ. Max. Unit Note / Test Condition Number Output Q Output Voltage VQ 4.9 5.0 5.1 V TLE42744DV50, TLE42744GV50, TLE42744EV50 5 mA < IQ< 400 mA 6 V < VI < 28 V P_5.1.1 Output Voltage VQ 4.9 5.0 5.1 V TLE42744DV50, TLE42744GV50, TLE42744EV50 5 mA < IQ