TLE4275GV33ATMA1

Linear Voltage Regulator 3.3 V Fixed Output Voltage TLE 4275 V33 Feature Overview • • • • • • • • • • • • • • Output voltage 3.3 V ± 2 % Current capability 400 mA Stable with ceramic output capacitor Reset circuit functional without supply voltage present Reset output active low down to VQ = 1 V Reset circuit sensing the output voltage with programmable delay time Maximum input voltage -42 V ≤ VI ≤ +45 V ESD Resistivity 4 kV (Human Body Model) Reverse polarity protection Short circuit protection Overtemperature shutdown Automotive temperature range -40 °C ≤ Tj ≤ 150 °C Green Product (RoHS compliant) AEC qualified PG-TO252-5-11 The TLE 4275 V33 is a monolithic integrated low dropout fixed output voltage regulator for loads up to 400mA. An integrated reset generator with adjustable power-on delay time as well as several protection circuits predestine the IC for supplying microprocessor systems in an automotive environment. Supply TLE 4275 V33 I Q PG-TO263-5-1 Regulated Output Voltage +5V Load e. g. Micro Controller Protection Circuits GND Bandgap Reference Reset Generator Bo l c k Di ag ra m_ A p pC ircui t1.v sd or: RO D GND CQ CD Figure 1 Simplified Block Diagram and Typical Application Type Package TLE 4275 D V33 PG-TO252-5-11 (RoHS compliant) TLE 4275 G V33 PG-TO263-5-1 (RoHS compliant) Datasheet 1 Rev. 1.2, 2015-12-18 TLE 4275 V33 Pin Definitions and Functions 1 Pin Definitions and Functions GND 1 5 Ι RO Ι D Q GND Q D RO AEP02580 IEP02528 PG-TO252-5-11 PG-TO263-5-1 Figure 2 Pin Assignment Pin Symbol Function 1 I Regulator Input and IC Supply. • For compensating line influences, a capacitor to GND close to the IC terminals is recommended. 2 RO Reset Output. • Open collector output. External pull-up resistor to a positive voltage rail required. • Leave open if the reset function is not needed. 3 GND PG-TO263-5-1 only: Ground Reference. • Connect to TAB and heatsink area 4 D Reset Delay Timing. • Connect a ceramic capacitor to GND for reset delay timing adjustment. • Leave open if the reset function is not needed. 5 Q Regulator Output. • Block to GND with a capacitor close to the IC terminals, respecting capacitance and ESR requirements given in the table “Functional Range”. TAB GND PG-TO252-5-11 only: Ground Reference. • Connect to heatsink area. TAB – PG-TO263-5-1 only: • Connect to heatsink area and ground reference (pin 3). Datasheet 2 Rev. 1.2, 2015-12-18 TLE 4275 V33 Electrical Characteristics 2 Electrical Characteristics 2.1 Absolute Maximum Ratings -40 °C ≤ Tj ≤ 150 °C; all voltages with respect to ground (unless otherwise specified) Pos. Parameter Symbol Limit Values Unit Conditions Min. Max. VI II -42 45 V – – – mA internally limited VQ IQ -1 16 V – – – mA internally limited VRO IRO -0.3 25 V – -5 5 mA VD ID -0.3 7 V -2 2 mA IGND – – mA internally limited Tj Tstg -40 150 °C – -50 150 °C – VESD,HBM VESD,CDM -4 4 kV HBM1) -500 500 V CDM2) MSL 1 – – Regulator Input and IC Supply I 2.1.1 Voltage 2.1.2 Current Regulator Output Q 2.1.3 Voltage 2.1.4 Current Reset Output RO 2.1.5 Voltage 2.1.6 Current Reset Delay Timing D 2.1.7 Voltage 2.1.8 Current – Ground GND 2.1.9 Current Temperatures 2.1.10 Junction Temperature 2.1.11 Storage Temperature ESD Susceptibility 2.1.12 ESD Resistivity 2.1.13 Moisture Level 2.1.14 Moisture Level 1) ESD susceptibility, Human Body Model “HBM” according to EIA/JESD 22-A114B. 2) ESD susceptibility, Charged Device Model “CDM” according to EIA/JESD22-C101 or ESDA STM5.3.1 Note: Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note: Integrated protection functions are designed to prevent IC destruction under fault conditions described in the data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are not designed for continuous repetitive operation. Datasheet 3 Rev. 1.2, 2015-12-18 TLE 4275 V33 Electrical Characteristics 2.2 Pos. Functional Range Parameter 2.2.1 Input Voltage 2.2.2 Junction Temperature 2.2.3 Output Capacitor 2.2.4 Symbol VI Tj CQ ESRCQ Limit Values Unit Conditions / Remarks Min. Max. 4.4 42 V VQ = VI - Vdr 1) -40 150 °C – 22 – µF – 2) – 3 Ω – 1) For details on max. output current vs. input voltage see Table 1: Electrical Characteristics Voltage Regulator 2) The minimum output capacitance requirement is applicable for a worst case capacitance tolerance of 30% Note: Within the functional range the IC operates as described in the circuit description. The electrical characteristics are specified within the conditions given in the related electrical characteristics table. 2.3 Pos. Thermal Resistance Parameter Symbol Typ. Value Unit Conditions Rth,j-a 144 K/W Footprint only1) 78 K/W 300 mm2 PCB heatsink area1) 55 K/W 600 mm2 PCB heatsink area1) 1.8 K/W 79 K/W Footprint only1) 53 K/W 300 mm2 PCB heatsink area1) 39 K/W 600 mm2 PCB heatsink area1) 1.3 K/W Package P-TO252-5: 2.3.1 2.3.2 Junction – Ambient PG-TO252-5-11 2.3.3 2.3.4 Junction – Case PG-TO252-5-11 Rth,j-c Package P-TO263-5: 2.3.1 2.3.2 Junction – Ambient PG-TO263-5-1 Rth,j-a 2.3.3 2.3.4 Junction – Case PG-TO263-5-1 Rth,j-c 1) EIA/JESD 52_2, FR4, 80 × 80 × 1.5 mm; 35μ Cu, 5μ Sn; horizontal position; zero airflow. Not subject to production test; specified by design. Datasheet 4 Rev. 1.2, 2015-12-18 TLE 4275 V33 Block Description and Electrical Characteristics 3 Block Description and Electrical Characteristics 3.1 Voltage Regulator The output voltage VQ is controlled by comparing a portion of it to an internal reference and driving a PNP pass transistor accordingly. The control loop stability depends on the output capacitor CQ, the load current, the chip temperature and the poles/zeros introduced by the integrated circuit. To ensure stable operation, the output capacitor’s capacitance and its equivalent series resistor ESR requirements given in the table “Operating Range” have to be maintained. For details see also the typical performance graph “Output Capacitor Series Resistor ESRCQ vs. Output Current IQ”. Also, the output capacitor shall be sized to buffer load transients. An input capacitor CI is strongly recommended to buffer line influences. Connect the capacitors close to the IC terminals. Protection circuitry prevent the IC as well as the application from destruction in case of catastrophic events. These safeguards contain output current limitation, reverse polarity protection as well as thermal shutdown in case of overtemperature. In order to avoid excessive power dissipation that could never be handled by the pass element and the package, the maximum output current is decreased at input voltages above VI = 22 V. The thermal shutdown circuit prevents the IC from immediate destruction under fault conditions (e.g. output continuously short-circuited) by switching off the power stage. After the chip has cooled down, the regulator restarts. This leads to an oscillatory behaviour of the output voltage until the fault is removed. However, junction temperatures above 150 °C are outside the maximum ratings and therefore significantly reduce the IC lifetime. The TLE 4275 V33 allows a negative supply voltage. However, several small currents are flowing into the IC increasing its junction temperature. This has to be considered for the thermal design, respecting that the thermal protection circuit is not operating during reverse polarity conditions For details see typical performance graphs. Supply I Q Regulated Output Voltage Saturation Control Current Limitation C CI Temperature Shutdown Bandgap Reference Datasheet } CQ LOAD GND Blo c k Dia gra m _Vo lta ge Re gu la tor.v s d Figure 3 ESR Block Diagram Voltage Regulator Circuit 5 Rev. 1.2, 2015-12-18 TLE 4275 V33 Block Description and Electrical Characteristics Table 1 Electrical Characteristics Voltage Regulator VI = 13.5 V; -40 °C ≤ Tj ≤ 150 °C (unless otherwise specified) Pos. Parameter Symbol Limit Values Unit Remark / Test Condition Min. Typ. Max. 3.23 3.3 3.37 V 1 mA ≤ IQ ≤ 400 mA; 5 V ≤ VI ≤ 28 V 3.1.1 3.23 3.3 3.37 V 1 mA ≤ IQ ≤ 300 mA; 4.4 V ≤ VI ≤ 28 V 3.1.2 3.23 3.3 3.37 V 1 mA ≤ IQ ≤ 200 mA; 4.4 V ≤ VI ≤ 40 V 3.1.1 Output Voltage VQ 3.1.3 Load Regulation steady-state dVQ,load -30 -15 – mV 3.1.4 Line Regulation steady-state dVQ,line – 5 15 mV 3.1.5 Power Supply Ripple Rejection PSRR – 60 – dB 3.1.6 Output Current Limitation IQ,max 401 – 1000 mA IQ = 5 mA to 400 mA; VI = 6 V VI = 8 V to 32 V; IQ = 5 mA fripple = 100 Hz; Vripple = 0.5 Vpp 1) VQ = 3.0 V 3.1.7 Overtemperature Shutdown Tj,sd Threshold 151 – 200 °C Tj increasing 1) 3.1.8 Overtemperature Shutdown Tj,hy Threshold Hysteresis – 25 – K 1) Parameter not subject to production test; specified by design. 3.2 Current Consumption Table 2 Electrical Characteristics Current Consumption VI = 13.5 V; -40 °C ≤ Tj ≤ 150 °C (unless otherwise specified) Pos. Parameter Symbol Limit Values Unit Conditions Min. Typ. Max. – 180 220 µA 3.2.2 – 180 240 µA 3.2.3 – 8 12 mA IQ = 1 mA; Tj = 25 °C IQ = 1 mA; Tj ≤ 85 °C IQ = 250 mA 3.2.4 – 20 30 mA IQ = 400 mA 3.2.1 Current Consumption Iq Iq = IQ - II Datasheet 6 Rev. 1.2, 2015-12-18 TLE 4275 V33 Block Description and Electrical Characteristics 3.3 Reset Function The reset function contains serveal features: Output Undervoltage Reset: An output undervoltage condition is indicated setting the Reset Output “RO” to low. This signal might be used to reset a microcontroller during low supply voltage. In case the battery voltage is already lower than the buffered output voltage VQ of the voltage regulator, the reset circuit is supplied from the output “Q”, ensuring a defined reset switching threshold also at VI = 0 V. The Reset Output “RO” is held “low” down to an output voltage of VQ = 1 V, even if the input voltage VI is 0 V. Power-On Reset Delay Time: The power-on reset delay time td,PWR-ON allows a microcontoller and oscillator to start up. This delay time is the time period from exceeding the reset switching threshold VRT until the reset is released by switching the reset output “RO” from “low” to “high”. The power-on reset delay time td,PWR-ON is defined by an external delay capacitor CD connected to pin “D” which is charged up by the delay capacitor charge current ID,ch starting from VD = 0 V. For easy calculating the power-on reset delay time, a multiplier factor Fd,PWR-ON = td,PWR-ON / CD is specified. Hence, td,PWR-ON becomes: td,PWR-ON = Fd,PWR-ON *CD . (1) For a precise calculation consider also the delay capacitor’s tolerance. Undervoltage Reset Delay Time: Unlike the power-on reset delay time, the undervoltage reset delay td time considers a short output undervoltage event where the delay capacitor CD is assumed to be discharged to VD = VDST,lo only before the charging sequence restarts. Therefore, the undervoltage reset delay time td is defined by the delay capacitor charge current ID,ch starting from VD = VDST,lo and the external delay capacitor CD. For easy calculating the undervoltage reset delay time, a multiplier factor Fd = td / CD is specified. Hence, td becomes: td = Fd *CD . (2) For a precise calculation consider also the delay capacitor’s tolerance. Reset Reaction Time: The total reset reaction rime trr,total considers the internal reaction time trr,int and the discharge time trr,d defined by the external delay capacitor CD (see typical performance graph for details). Hence, the total reset reaction rime becomes: trr,total = trr,int + trr,d . (3) Reset Output “RO” Low for VQ ≥ 1 V: In case of an undervoltage reset condition reset output “RO” is held “low” for VQ ≥ 1 V, even if the input voltage VI is 0 V. This is achieved by supplying the reset circuit from the output capacitor. Datasheet 7 Rev. 1.2, 2015-12-18 TLE 4275 V33 Block Description and Electrical Characteristics Reset Output “RO”: The Reset Output “RO” is an open collector output requiring an external pull-up resistor to a voltage rail VIO. As the maximum Reset Output Sink Current IRO,max is limited, the minimum external pull-up resistor calculates: RRO,external,min = VIO / IRO,max. (4) e.g. +5 V Supply I Q Int. Supply VDD or CQ Control RO ID,c h Reset V DS T VRT MicroController IDR,ds ch GND D Blo c k Di a gra m _Res etSta nd ard _RO n op ul l up .v s d GND CD Figure 4 Block Diagram Reset Circuit VΙ t < t rr VQ V Q, rt d V Ι D,c = dt CD VD t V DU V DRL VRO t rr t rd t t Power-on-Reset Figure 5 Datasheet Thermal Shutdown Voltage Dip at Input Undervoltage Secondary Spike Overload at Output AED03010 Timing Diagram Reset 8 Rev. 1.2, 2015-12-18 TLE 4275 V33 Block Description and Electrical Characteristics Table 3 Electrical Characteristics Reset Function VI = 13.5 V; -40 °C ≤ Tj ≤ 150 °C (unless otherwise specified) Pos. Parameter Symbol Limit Values Min. Pos. Parameter Symbol Typ. Unit Conditions Unit Conditions / Remarks VI ≥ 4.4 V VQ decreasing VI = 0 V VQ decreasing Max. Limit Values Min. Typ. Max. 3.06 3.13 3.2 V 2.5 2.9 VRT1 V 100 130 – mV Calculated Value: VQ,nom - VRT . VI ≥ 4.4 V Output Undervoltage Reset Comperator: 3.3.1 Output Undervoltage Reset VRT1 Switching Threshold 3.3.2 VRT2 3.3.3 Output Undervoltage Reset VRH Headroom Reset Output RO: 3.3.4 Reset Output Low Voltage VRO,low – 0.2 0.4 V 3.3.5 Reset Output Sink Current Limitation IRO,max 0.3 – – mA 3.3.6 Reset Output External Pull-up Resistor to VQ RRO 3.3 – – kΩ 1 V ≤ VQ ≤ VRT ; IRO = 0.3 mA 1 V ≤ VQ < VRT ; VRO = 3.3V VRO ≤ 0.4 V at reset condition 3.3.7 Reset Output Leakage Current IRO,leak – 0 2 µA VRO = 5 V Reset Delay Timing: 3.3.8 Upper Delay Switching Threshold VDST,hi – 1.8 – V – 3.3.9 Lower Delay Switching Threshold VDST,lo – 0.6 – V – 3.3.10 Delay Capacitor Charge Current ID,ch – 6 – µA VD = 1 V 3.3.11 Delay Capacitor Reset Discharge Current IDR,dsch – 70 – mA VD = 1 V 3.3.12 Undervoltage Reset Delay Time Factor Fd = td / CD Fd 0.13 0.20 0.27 ms / nF Calculated Value: Fd = (VDST,hi - VDST,lo) / ID,ch CD ≥ 10 nF 1) 3.3.13 Power-on Reset Delay Time Factor Fd,PWR-ON = td,PWR-ON / CD Fd,PWR-ON 0.21 0.30 0.39 ms / nF Calculated Value: Fd = VDST,hi / ID,ch CD ≥ 10 nF 1) 3.3.14 Delay Capacitor Discharge Time trr,d – 0.7 2 µs Calculated Value: trr,d = CD*(VDST,hi - VDST,lo)/ ID,dsch CD = 47 nF 3.3.15 Internal Reset Reaction Time trr,int – 2 6.5 µs CD = 0 nF 2) 1) For lower values of CD, the accuracy given is not guaranteed; see typ. performance graph for details. 2) Parameter not subject to production test; specified by design. Datasheet 9 Rev. 1.2, 2015-12-18 TLE 4275 V33 Package Outlines 4 Package Outlines 6.5 +0.15 -0.05 A 1) 2.3 +0.05 -0.10 0.51 MIN. 1.14 4.56 10.6 6.4 5.8 0.5 +0.08 -0.04 5 x 0.6 ±0.1 0.34 0.8 ±0.15 (4.24) 1 ±0.1 Footprint (Reflow Soldering) 0.9 +0.20 -0.01 0...0.15 5.36 0.15 MAX. per side 0.5 +0.08 -0.04 B (5) 0.8 9.98 ±0.5 6.22 -0.2 5.7 MAX. 2.2 0.1 B 0.25 M A B 1) Includes mold flashes on each side. All metal surfaces tin plated, except area of cut. Dimensions in mm Figure 6 PG-TO252-5-11 Package Outline and Footprint 4.4 10 ±0.2 1.27 ±0.1 A 8.5 1) Footprint (Reflow Soldering) B 0.05 10.8 16.15 2.7 ±0.3 4.7 ±0.5 9.4 2.4 0.1 7.55 1) 9.25 ±0.2 (15) 1±0.3 0...0.3 4.6 0...0.15 5 x 0.8 ±0.1 0.5 ±0.1 0.6 4 x 1.7 0.25 M A B 8˚ MAX. 1.1 7.9 0.1 B 1) Typical Metal surface min. X = 7.25, Y = 6.9 All metal surfaces tin plated, except area of cut. GPT09113 Dimensions in mm Figure 7 PG-TO263-5-1 Package Outline and Footprint Green Product (RoHS compliant) To meet the world-wide customer requirements for environmentally friendly products and to be compliant with government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e Pbfree finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020). Find more package information on the Infineon Internet Page: http://www.infineon.com/packages. Datasheet 10 Rev. 1.2, 2015-12-18 TLE 4275 V33 Revision History 5 Revision History Revision Date Changes 1.2 2015-12-18 Page 7 update on formula 1 and 2. Page 9 update on 3.3.13 formula in conditions column 1.1 2015-01-15 Parameter 2.1.14 MSL Min. value changed from 3 to 1. 1.0 2006-09-22 Datasheet 11 Rev. 1.2, 2015-12-18 Edition 2015-12-18 Published by Infineon Technologies AG, 81726 Munich, Germany © Infineon Technologies AG 2006. All Rights Reserved. Attention please! The information given in this data sheet shall in no event be regarded as a guarantee of conditions or characteristics (“Beschaffenheitsgarantie”). With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of noninfringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. 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