D a t a S h e e t , R e v. 1 . 0 , M ar c h 2 00 9
TLE8264-2E
U ni v e r s a l S y s t e m B as i s C h i p
H ER M ES
R ev . 1 . 0
A u to m o t i v e P o w e r
TLE8264-2E
Table of Contents
Table of Contents
1
HERMES Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3
3.1
3.2
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4
4.1
4.2
State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
State Machine Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5
5.1
5.2
5.3
5.4
General Product Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16
16
17
18
19
6
6.1
6.2
6.3
6.4
6.5
Internal Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Internal Voltage Regulator Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Internal Voltage Regulator Modes with SBC Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21
21
21
21
22
23
7
7.1
7.2
7.3
7.4
7.5
External Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Voltage Regulator Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Voltage Regulator State by SBC Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24
24
24
24
25
27
8
8.1
8.2
8.3
8.4
8.5
8.6
High Speed CAN Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
High-speed CAN Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CAN Cell Mode with SBC Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Failure Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPLIT Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
29
29
29
32
33
34
36
9
9.1
9.2
9.3
WK Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Wake-Up Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
40
40
40
42
10
10.1
10.2
10.3
10.4
10.5
10.6
LIN Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LIN Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LIN Cell Mode with SBC Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Failure Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
43
43
43
45
46
47
49
11
11.1
Supervision Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Reset Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Data Sheet
2
Rev. 1.0, 2009-03-31
TLE8264-2E
Table of Contents
11.2
11.3
Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
12
12.1
12.2
12.3
12.4
12.5
Interrupt Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Modes with SBC Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
60
60
64
64
64
65
13
13.1
13.2
13.3
13.4
13.5
13.6
Limp Home . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Limp Home output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Activation of the Limp Home Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Release of the Limp Home Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Vcc1µC undervoltage time-out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
66
66
66
68
68
68
70
14
14.1
14.2
Configuration Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Configuration select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Config Hardware Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
15
15.1
15.2
15.3
15.4
15.5
15.6
15.7
Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Corrupted data in the SPI data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Input Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Output Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Data Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Output Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
72
72
72
73
74
74
82
84
16
16.1
16.2
16.3
Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ZthJA Curve . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hints for SBC Factory Flash Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ESD Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
86
89
90
91
17
Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
18
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Data Sheet
3
Rev. 1.0, 2009-03-31
Universal System Basis Chip
HERMES
Rev. 1.00
1
TLE8264-2E
HERMES Overview
Scalable System Basis Chip Family
•
•
•
•
•
Six products for complete scalable application coverage
Complete compatibility (hardware and software) across the family
TLE8264-2E (3LIN), TLE8263-2E (2LIN) - 3 Limp Home outputs
TLE8264E (3LIN), TLE8263E (2LIN) - 1 Limp Home output
TLE8262E (1LIN), TLE8261E (no LIN) - 1 Limp Home output
Basic Features
•
•
•
•
•
•
•
•
•
•
•
Very low quiescent current in Stop and Sleep Modes
Reset input, output
Power on and scalable undervoltage reset generator
Standard 16-bit SPI interface
Overtemperature and short circuit protection
Short circuit proof to GND and battery
One universal wake-up input
Wide input voltage and temperature range
Cyclic wake in Stop Mode
Green Product (RoHS compliant)
AEC Qualified
PG-DSO-36-38
Description
The devices of the SBC family are monolithic integrated circuits in an enhanced power package with identical
software functionality and hardware features except for the number of LIN cells. The devices are designed for
CAN-LIN automotive applications e.g. body controller, gateway applications.
To support these applications, the System Basis Chip (SBC) provides the main functions, such as HS-CAN
transceiver and LIN transceivers for data transmission, low dropout voltage regulators (LDO) for an external 5 V
supply, and a 16-bit Serial Peripheral Interface (SPI) to control and monitor the device. Also implemented are a
Time-out or a Window Watchdog circuit with a reset feature, Limp Home circuitry output, and an undervoltage
reset feature.
The devices offer low power modes in order to support application that are connected permanent to the battery.
A wake-up from the low power mode is possible via a message on the buses or via the bi-level sensitive
monitoring/wake-up input as well as from the SPI command. Each wake-up source can be inhibited.
The device is designed to withstand the severe conditions of automotive applications.
Type
Package
Marking
TLE8264-2E
PG-DSO-36-38
TLE8264-2E
Data Sheet
4
Rev. 1.0, 2009-03-31
TLE8264-2E
HERMES Overview
HS CAN Transceiver
•
•
•
•
•
•
•
•
•
Compliant to ISO 11898-2 and 11898-5 as well as SAE J2284
CAN data transmission rate up to 1 MBaud
Supplied by dedicated input VccHSCAN
Low power mode management
Bus wake-up capability via CAN message
Excellent EMC performance (very high immunity and very low emission)
Bus pins are short circuit proof to ground and battery voltage
8 kV ESD gun test on CANH / CANL / SPLIT
Bus failure detection
LIN Transceiver
•
•
•
•
•
LIN2.1 conformance, LIN2.1 is back compatible to LIN1.3 and LIN2.0
SAE J2602-2 conformance
Compatible to ISO 9141 (K-L-Line)
Transmission rate up to 20 kBaud, LIN Flash Mode 115kBaud
8 kV ESD gun test on Bus pins
Voltage Regulators
•
•
•
•
•
Low-dropout voltage regulator
Vcc1µC, 200 mA, 5 V ±2% for external devices, such as microcontroller and RF receiver
Vcc2, 200 mA, 5 V ±2% for external devices or the internal HS CAN cell
Vcc3, current limitation by shunt resistor (up to 400 mA with 220 mΩ shunt resistor), 5 V ±4% with external PNP
transistor; for example: to supply additional external CAN transceivers
Vcc1µC, undervoltage Time-out
Supervision
•
•
•
•
•
Reset output with integrated pull-up resistor
Time-out or Window Watchdog, SPI configured
Watchdog Timer from 16 ms to 1024 ms
Check sum bit for Watchdog configuration
Reset due to Watchdog failure can be inhibited with Test pin (SBC SW Development Mode)
Interrupt Management
•
•
Complete enabling / disabling of interrupt sources
Timing filter mechanism to avoid multiple / infinite Interrupt signals
Limp Home
•
•
•
•
•
•
Open drain Limp Home outputs
Dedicated internal logic supply
Maximum safety architecture for Safety Operation Mode
Configurable Fail-Safe behavior
Dedicated side indicators signal 1.25Hz 50% duty cycle
Dedicated PWM signal 100Hz 20% duty cycle
Data Sheet
5
Rev. 1.0, 2009-03-31
TLE8264-2E
Block Diagram
2
Block Diagram
The simplified block diagram illustrates only the basic elements of the SBC devices. Please refer to the information
for each device in the product family for more specific hardware configurations.
V CC2
VCC1µC
V CC3ref
VS
VCC3S HUNT
VS
VCC3B ASE
VS
VS
Vcc1µC
V cc2
Vcc3
GND
Vint.
Vint.
SDI
SDO
CLK
SPI
CSN
SBC
STATE
MACHINE
LH_PL/test
Limp
Home
Limp home
LHO_SI
INT
Interrupt
Control
RO
RESET
GENERATOR
WK
TxD1
RxD1
BUS1
BUS2
TxD2
RxD2
WAKE
REGISTER
CAN cell
Data Sheet
TxD CAN
RxD CAN
CAN_H
SPLIT
CAN_L
LIN1 cell
LIN3 cell
LIN2 cell
TxD3
RxD3
BUS3
Block diagram_TLE8264-2E.vsd
GND
Figure 1
VCCH SCAN
Vs
WK
Simplified Block Diagram
6
Rev. 1.0, 2009-03-31
TLE8264-2E
Pin Configuration
3
Pin Configuration
3.1
Pin Assignments
52
/+B3/7HVW
&61
/LPSKRPH
&/.
:.
6',
6'2
/+B6,
%XV
*1'
%XV
*1'
9V
5['/,1
7['/,1
9V
5['/,1
%XV
7['/,1
9FFVKXQW
9FFEDVH
5['/,1
7['/,1
*1'
5['&$1
9FF5()
7['&$1
,17
*1'
9FF&
&$1/
9FF
63/,7
9FF+6&$1
&$1+
7/((
'62([SRVHG3DG
([SRVHG
'LH
3DG
3LQRXWBB(VYJ
Figure 2
Data Sheet
Pin Configuration
7
Rev. 1.0, 2009-03-31
TLE8264-2E
Pin Configuration
3.2
Pin Definitions and Functions
Pin
Symbol
Function
1
RO
Reset Input/Output; open drain output, integrated pull-up resistor; active low.
2
CSN
SPI Chip Select Not Input; CSN is an active low input; serial communication is
enabled by pulling the CSN terminal low; CSN input should be set to low only when
CLK is low; CSN has an internal pull-up resistor and requires CMOS logic level
inputs.
3
CLK
SPI Clock Input; clock input for shift register; CLK has an internal pull-down resistor
and requires CMOS logic level inputs.
4
SDI
SPI Data Input; receives serial data from the control device; serial data transmitted
to SDI is a 16-bit control word with the Least Significant Bit (LSB) transferred first:
the input has a pull-down resistor and requires CMOS logic level inputs; SDI will
accept data on the falling edge of the CLK signal.
5
SDO
SPI Data Output; this tri-state output transfers diagnostic data to the control device;
the output will remain tri-stated unless the device is selected by a low on Chip Select
Not (CSN).
6
GND
Ground
7
Bus3
LIN Bus 3; Bus line for the LIN interface, according to ISO 9141 and LIN
specification 2.1 as well as SAE J2602-2.
8
Vs
Power Supply Input; block to GND directly at the IC with ceramic capacitor. Ensure
to have no current flow from PIN8 to PIN9. PIN8 and PIN9 can be directly connected.
9
Vs
Power Supply Input; block to GND directly at the IC with ceramic capacitor. Ensure
to have no current flow from PIN8 to PIN9. PIN8 and PIN9 can be directly connected.
10
Bus1
LIN Bus 1; Bus line for the LIN interface, according to ISO. 9141 and LIN
specification 2.1 as well as SAE J2602-2.
11
PNP Shunt; External PNP emitter voltage.
12
Vcc3 shunt
Vcc3 base
13
GND
Ground
14
Vcc3REF
External PNP Output Voltage
15
INT
Interrupt Output, configuration Input; used as wake-up flag from SBC Stop Mode
and indicating failures. Active low. Integrated pull up. During start-up used to set the
SBC configuration. External Pull-up sets config 1/3, no external Pull-up sets config
2/4.
16
Vcc1 µc
Voltage Regulator Output; 5 V supply; to stabilize block to GND with an external
capacitor.
17
Vcc2
Voltage Regulator Output; 5 V supply; to stabilize block to GND with an external
capacitor.
18
VccHSCAN
Supply Input; for the internal HS CAN cell.
19
CANH
CAN High Line; High in dominant state.
20
SPLIT
Termination Output; to support recessive voltage level of the bus lines.
21
CANL
CAN Low Line; Low in dominant state.
22
GND
Ground
23
TxDCAN
CAN Transmit Data Input; integrated pull-up resistor.
24
RxDCAN
CAN Receive Data Output
Data Sheet
PNP Base; External PNP base voltage.
8
Rev. 1.0, 2009-03-31
TLE8264-2E
Pin Configuration
Pin
Symbol
Function
25
TxDLIN
LIN Transceiver Data input; according to ISO 9141 and LIN specification 2.1 as
well as SAE J2602-2. integrated pull-up resistor.
26
RxDLIN
LIN Transceiver Data Output; according to the ISO 9141 and LIN specification 2.1
as well as SAE J2602-2; push-pull output; LOW in dominant state.
27
TxDLIN2
LIN Transceiver Data Input; according to ISO 9141 and LIN specification 2.1 as
well as SAE J2602-2. integrated pull-up resistor.
28
RxDLIN2
LIN Transceiver Data Output; according to the ISO 9141 and LIN specification 2.1
as well as SAE J2602-2; push-pull output; LOW in dominant state.
29
TxDLIN3
LIN Transceiver Data Input; according to ISO 9141 and LIN specification 2.1 as
well as SAE J2602-2. integrated pull-up resistor.
30
RxDLIN3
LIN Transceiver Data Output; according to the ISO 9141 and LIN specification 2.1
as well as SAE J2602-2; push-pull output; LOW in dominant state.
31
GND
Ground
32
Bus2
LIN Bus 2; Bus line for the LIN interface, according to ISO 9141 and LIN
specification 2.1 as well as SAE J2602-2.
33
LH_SI
Limp Home side indicator; Side indicators 1.25Hz 50% duty cycle output; Open
drain. Active LOW.
34
WK
Monitoring / Wake-Up Input; bi-level sensitive input used to monitor signals
coming from, for example, an external switch panel; also used as wake-up input;
35
Limp Home
Fail-Safe Function Output; Open drain. Active LOW.
36
LH_PL/Test
SBC SW Development Mode entry; Connect to GND for activation; Integrated pullup resistor. Connect to VS or leave open for normal operation.
Limp Home Pulsed Light output: Brake/rear light 100Hz 20% duty cycle output;
Open drain. Active LOW.
EDP
-
Exposed Die Pad; For cooling purposes only, do not use it as an electrical ground.1)
1) The exposed die pad at the bottom of the package allows better dissipation of heat from the SBC via the PCB. The exposed
die pad is not connected to any active part of the IC and can be left floating or it can be connected to GND for the best EMC
performance.
Data Sheet
9
Rev. 1.0, 2009-03-31
TLE8264-2E
State Machine
4
State Machine
4.1
Block Description
First battery connection
(POR)
AND
config0 not active
Condition / event
SBC Init mode
(256ms max after reset relaxation)
SPI cmd
Vcc1
on
Vcc2/3
off
WD
conf
L.H.
inact
CAN
inact
LIN
inact
SBC action
SPI cmd
SPI cmd
SBC SW Flash mode
Vcc1
on
Vcc2/3
on/off
WD
fixed
Vcc1
on
Vcc2/3
on/off
WD
conf
L.H.
act/inact
CAN
Tx/Rx
LIN
Flash
mode
L.H.
act/inact
CAN
conf
LIN
conf
WD trig
SPI cmd
SPI cmd
NOT reset clamped
(high or low)
OR
NOT undervoltage
at Vcc1
Detection of falling edge at reset
pin (any mode)
OR
undervoltage reset at VCC1µC
(any mode)
SBC Sleep mode
Vcc1
off
WK event stored
LH entry condition
stored
OR
Restart entry
condition stored
L.H.
act/inact
Vcc1
on
Vcc2/3
on/off
Reset
act.
L.H.
act/inact
CAN
LIN
waked or off
waked or off
Vcc2/3
off
SBC Stop mode
WD
off
CAN
LIN
Wakable/
off
Wakable/
off
SPI cmd
Vcc1
on
Vcc2/3
on/off
L.H.
act/inact
WD
WD trig
fixed/off
CAN
LIN
wakable/
off
wakable/
off
Wake up event
SBC Restart mode
Config 1/3:
Reset clamped LOW (any
mode)
WD trig
SPI cmd
SPI cmd
OR
WD failed
1st (config1) or 2nd (config3) WD trig
failure
in Normal / Stop / SW Flash mode
SBC Normal mode
reset (initiated by SBC )
Init mode not successful
First battery connection
(POR)
AND
config0
Config 1/3:
Reset clamped HIGH during restart / init
SBC SW Development
mode
Vcc1
Vcc2/3
WD
mode set mode set mode set
CAN, LIN, WK Wake-up
OR
Release of over temperature at Vcc1
(Wake-up event stored)
(LH entry condition stored)
L.H.
CAN
LIN
mode set mode set mode set
SBC Fail-Safe mode
1st (config2) or 2nd (config4) WD trig failure
in Normal / Stop / SW Flash mode
Vcc1
off
Vcc2/3
off
WD
off
Config 2/4:
Reset clamped LOW (any
mode)
L.H.
act
CAN
sleep
LIN
sleep
SBC Factory Flash mode
Config 2/4:
Reset clamped HIGH during Restart
or Init mode
Vcc1 over temperature shutdown
OR
V S > VUV_ON & Undervoltage time
out on VCC1
Vcc1
ext.
Vcc2/3
off
WD
off
L.H.
inact.
CAN
off
LIN
off
Power mode managment.vsd
Figure 3
Data Sheet
Power Mode Management
10
Rev. 1.0, 2009-03-31
TLE8264-2E
State Machine
4.2
State Machine Description
The System Basis Chip (SBC) offers ten operating modes: Power On Reset, Init, Normal, Restart, Software Flash,
Sleep, Stop, Fail-Safe, Software Development, and Factory Flash Mode. The modes are controlled with one test
pin and via three mode select bits MS2..0, within the SPI. Additionally, the SBC allows five configurations,
accessed via two external pins and one SPI bit.
4.2.1
Configuration Description
Table 1 provides descriptions and conditions for entry to the different configurations of the SBC.
Table 1
SBC Configuration
Configuration
Description
Test pin
INT Pin
WD to
LH bit
config 0
Software Development Mode
0V
n.a
n.a
config 1
After missing the WD trigger for the first time, the state of Vcc1µC Open / VS External 0
remain unchanged, LH pin is active, SBC in Restart Mode
pull-up
config 2
After missing the WD trigger for the first time, Vcc1µC turns OFF,
LH pin is active, SBC in Fail-Safe Mode
No ext.
pull-up
config 3
After missing the WD trigger for the second time, the state of
Vcc1µC remain unchanged, LH pin is active, SBC in Restart
Mode
External 1
pull-up
config 4
After missing the WD trigger for the second time, Vcc1µC turns
OFF, LH pin is active, SBC in Fail-Safe Mode
No ext.
pull-up
0
1
In SBC SW Development Mode, Config 1 to 4 are accessible.
4.2.2
SBC Power ON Reset (POR)
At VS > VUVON, the SBC starts to operate, by reading the test pin and then by turning ON Vcc1µC. When Vcc1µC
reaches the reset threshold VRT1, the reset output remains activated for tRD1 and the SBC enters then the Init Mode.
In the event that Vs decreases below VUVOFF, the device is completely disabled. For more details on the disable
behavior of the SBC blocks, please refer to the chapter specific to each block.
4.2.3
SBC Init Mode
At entering the SBC Init Mode, the SBC starts to read the Test pin. The SBC starts-up in SBC Init Mode, and, after
powering-up, waits for the microcontroller to finish its startup and initialization sequences. Vcc2/3 are OFF and the
Watchdog is configurable but not active. CAN and LIN modules are inactive and Limp Home output is inactive.
From this transition mode, the SBC can be switched via SPI command to the desired operating mode, SBC Normal
or Software Flash Mode. If the SBC does not receive any SPI command, or receive wrong SPI command (i.e. not
send the device to SBC Normal or SBC SW Flash Mode) within a 256 ms time frame after the reset relaxation, it
will enter into SBC Restart Mode and activate the Limp Home output.
Note: In Init Mode it is recommended to send one SPI command that sets the device to Normal Mode, triggers the
watchdog the first time and sets the required watchdog settings.
Data Sheet
11
Rev. 1.0, 2009-03-31
TLE8264-2E
State Machine
4.2.4
SBC Normal Mode
SBC Normal Mode is used to transmit and receive CAN and LIN messages. In this mode, Vcc1µC is always “ON”
Vcc2 and Vcc3 can be turned-on or off by SPI command. In Normal Mode the watchdog needs to be triggered. It can
be configured via SPI, window watchdog and time-out watchdog is possible (default value is time-out 256 ms). All
the wake-up sources can be inhibited in this mode. The Limp Home output can be enabled or disabled via SPI
command. Via SPI command, the SBC can enter Sleep, Stop or Software Flash Mode. A reset is triggered by the
SBC when entering the Software Flash Mode. It is recommended to send at first SPI command the watchdog
setting. Please refer to Chapter 13.4.
4.2.5
SBC Sleep Mode
During SBC Sleep Mode, the lowest power consumption is achieved by having the main and external voltage
regulators switched-off. As the microcontroller is not supplied, the integrated Watchdog is disabled in Sleep Mode.
The last Watchdog configuration is not stored. The CAN and LIN modules are in their respective Wake-capable
or OFF modes and the Limp Home output is unchanged, as before entering the Sleep Mode. If a wake-up appears
in this mode, the SBC goes into Restart Mode automatically. In Sleep Mode, not all wake-up sources should be
inhibited, this is required to not program the device in a mode where it can not wake up. If all wake sources are
inhibited when sending the SBC to Sleep Mode, the SBC does not go to Sleep Mode, the microcontroller is
informed via the INT output, and the SPI bit “Fail SPI” is set. The first SPI output data when going to SBC Normal
Mode will always indicate the wake up source, as well as the SBC Sleep Mode to indicate where the device comes
from and why it left the state.
Note: Do not change the transceiver settings in the same SPI command that sends the SBC to Sleep Mode.
4.2.6
SBC Stop Mode
The Stop Mode is used as low power mode where the µC is supplied. In this mode the voltage regulator Vcc1µC
remains active. The other voltage regulator (Vcc2/3) can be switched on or off.
The watchdog can be used or switched off. If the watchdog is used the settings made in Normal Mode are also
valid in Stop Mode and can not be changed.
The CAN and LIN modules are not active. They can be selected to be off or used as wake-up source. If all wake
up sources are disabled, (CAN, LIN, WK, cyclic wake) the watchdog can not be disabled, the SBC stays in Normal
Mode and the watchdog continues with the old settings.
If a wake-up event occurs the INT pin is set to low. The µC can react on the interrupt and set the device into Normal
Mode via SPI. There is no automatic transition to SBC Normal Mode.
There are 4 Options for SBC Stop Mode
•
•
•
•
WD on (the watchdog needs to be served as in Normal Mode
WD off (special sequence required see Chapter 11.2.4)
Cyclic Wake up with acknowledge (interrupt is sent after set time and needs to be acknowledged by SPI read)
Cyclic Wake-up, Watchdog off (interrupt is sent after set time)
Cyclic Wake-Up Feature
SBC Stop Mode supports the cyclic wake-up feature. By default, the function is OFF. It is possible to activate the
cyclic wake-up via “Cyclic WK on/off” SPI bit. This feature is useful to monitor battery voltage, for example, during
parking of the vehicle or for tracking RF data coming via the RF receiver. The Cyclic Wake-up feature sends an
interrupt via the pin INT to the µC after the set time. The cyclic wake-up feature shares the same clock as the
Watchdog. The time base set in the SPI for the Watchdog will be used for the cyclic wake-up. The timer has to be
set before activating the function. With the cyclic wake-up feature the watchdog is not working as known from the
other modes. In the case that both functions (Watchdog and cyclic wake-up) are selected, the cyclic wake-up is
activated and each interrupt has to be acknowledged by reading the SPI Wake register before the next Cyclic
Wake-Up comes. Otherwise, the SBC goes to SBC Restart Mode.
Data Sheet
12
Rev. 1.0, 2009-03-31
TLE8264-2E
State Machine
4.2.7
SBC Software Flash Mode
SBC Software Flash Mode is similar to SBC Normal Mode regarding voltage regulators. In this mode, the Limp
Home output can be set to active LOW via SPI and the communication on CAN and LIN modules is activated to
receive flash data. In the LIN module the slope control mechanism is switched off. The Watchdog configuration is
fixed to the settings used before entering the SBC SW Flash Mode. When the device comes from SBC Normal
Mode, a reset is generated at the transition.
From the SBC Software Flash Mode, the SBC goes into SBC Restart Mode, the config setting has no influence
on the behavior. A mode change to SBC Restart Mode can be caused by a SPI command, a time-out or Window
Watchdog failure or an undervoltage reset. When leaving the SBC Software Flash Mode a reset is generated.
4.2.8
SBC Restart Mode
They are multiple reasons to enter the SBC Restart Mode and multiple SBC behaviors described in Table 2.
In any case, the purpose of the SBC Restart Mode is to reset the microcontroller.
•
•
•
•
•
From SBC SW Flash Mode, it is used to start the new downloaded code.
From SBC Normal, SBC Stop Mode and SBC SW Flash Mode it is reached in case of undervoltage on Vcc1µC,
or due to incorrect Watchdog triggering.
From SBC Sleep Mode it is used to ramp up Vcc1µC after wake
From SBC Init Mode, it is used to avoid the system to remain undefined.
From SBC Fail-safe Mode it is used to ramp up Vcc1µC after wake or cool down of Vcc1µC.
From SBC Restart Mode, the SBC goes automatically to SBC Normal Mode. The delay time tRDx is programmable
by the “Reset delay” SPI bit. The Reset output (RO) is released at the transition. SBC Restart Mode is left
automatically by the SBC without any microcontroller influence. The first SPI output data will provide information
about the reason for entering Restart Mode. The reason for entering Restart Mode is stored and kept until the
microcontroller reads the corresponding “LH0..2” or “RM0..1” SPI bits. In case of a wake up from Sleep Mode the
wake source is seen at the interrupt bits (Configuration select 000), an interrupt is not generated.
Entering or leaving the SBC Restart Mode will not result in deactivation of the Limp Home output (if activated).
The first SPI output data when going to SBC Normal Mode will always indicate the reason for the SBC Restart
event.
Data Sheet
13
Rev. 1.0, 2009-03-31
TLE8264-2E
State Machine
Table 2
SBC Restart Mode Entry Reasons and Actions
SBC Mode and Configuration Entering reason
Actions
Mode
LH output
Vcc1µC
Init Mode
Config
Init Mode time-out
ON
remains ON LOW
LH 0..2
n.a.
Reset low from
outside
Unchanged
remains ON LOW
RM 0..1
config 1/3
Reset clamped
ON
remains ON LOW
LH 0..2
n.a
undervoltage reset
unchanged
ramping up
RM 0..1
config 3
Software Flash
Sleep
WD trigger failure
config 4
Software
Development
Mode
ON
LH 0..2
OFF after 1st
remains ON LOW
ON after 2nd
RM 0..1 after 1st
LH 0..2 after 2nd
OFF after 1st
RM 0..1 after 1st2)
Reset low from
outside
Unchanged
remains ON LOW
RM 0..1
config 1/3
Reset clamped
ON
remains ON LOW
LH 0..2
n.a
undervoltage reset
unchanged
remains ON LOW
RM 0..1
n.a
SPI cmd
unchanged
remains ON LOW
RM 0..1
n.a
WD trigger failure
unchanged
remains ON LOW
RM 0..1
n.a.
Reset low from
outside
Unchanged
remains ON LOW
RM 0..1
config 1/3
Reset clamped
ON
remains ON LOW
LH 0..2
n.a
Wake-up event
unchanged
ramping up
LOW
WK bits register
n.a
undervoltage reset
unchanged
ramping up
LOW
RM 0..1
config 3
Fail-Safe
LOW
n.a.
config 1
Stop1)
SPI Out Bits
n.a
config 1
Normal1)
RO
WD trigger failure
config 4
ON
LH 0..2
OFF after 1st
remains ON LOW
ON after 2nd
RM 0..1 after 1st
LH 0..2 after 2nd
OFF after 1st
RM 0..1 after 1st2)
n.a.
Reset low from
outside
Unchanged
remains ON LOW
RM 0..1
config 1/3
Reset clamped
ON
remains ON LOW
LH 0..2
n.a.
Wake-up event
ON
ramping up
LOW
LH 0..2
n.a
undervoltage reset
unchanged
ramping up
LOW
RM 0..1
n.a.
Reset low from
outside
Unchanged
remains ON LOW
RM 0..1
config 1/3
Reset clamped
ON
remains ON LOW
LH 0..2
1) Config 2 will never enter Restart Mode in case of WD failure but directly Fail-Safe Mode
2) Goes to Fail-Safe Mode after the second consecutive failure
Data Sheet
14
Rev. 1.0, 2009-03-31
TLE8264-2E
State Machine
4.2.9
SBC Fail-Safe Mode
In SBC Fail-Safe Mode, all voltage regulators are OFF and the transceivers are in Wake-Capable Mode. The Limp
Home output is active.
Conditions to enter the SBC Fail-Safe Mode are:
•
•
•
•
Watchdog trigger failure in configuration 2 or 4
Vcc1µC undervoltage time-out in any configuration if VS is above VLHUV range.
Temperature shutdown of Vcc1µC in any configuration.
Reset clamped in Config. 2/4
In case of Vcc1µC overtemperature shutdown, the SBC will latch and wait to cool down below the thermal hysteresis,
and will go back to SBC Restart Mode.
In case of a wake-up event, the SBC will go to SBC Restart Mode (not in case of Vcc1µC overtemperature
shutdown), storing the wake-up event and resetting the Watchdog trigger failure counter. The first SPI output data
when going to SBC Normal Mode will always indicate the reason for the SBC Fail-Safe Mode.
4.2.10
SBC Software Development Mode
If the Test pin is connected to GND (Config 0 active) during powering-up, the SBC enters SBC Software
Development Mode. SBC Software Development Mode is a super set of the other modes so it is possible to use
all the modes of the SBC with the following difference. In SBC Software Development Mode, no reset is generated
and VCC1µC is not switched off due to Watchdog trigger failure. If a Watchdog trigger failure occurs, it will be
indicated by the INT output (reset bit). The SBC Fail-Safe Mode or SBC Restart Mode are not reached in case of
wrong Watchdog trigger but the other reasons to enter these modes are still valid.
4.2.11
SBC Factory Flash Mode
In this mode, the SBC is completely powered OFF and the microcontroller is supplied externally. The mode is
detected when VCC1µC is powered from external and the voltage on Vs is not powered from external. The current
flow out of Vs must be limited to the maximum rating. The external supply voltage should be below the absolute
maximum rating stated in Chapter 5.1. The reset can be driven by an external circuit, or pulled high with a pull-up
resistor.
Note: Please respect the absolute maximum ratings when the device is in SBC Factory Flash Mode.
Data Sheet
15
Rev. 1.0, 2009-03-31
TLE8264-2E
General Product Characteristics
5
General Product Characteristics
5.1
Absolute Maximum Ratings
Absolute Maximum Ratings 1)
Tj = -40 °C to +150 °C; all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Pos.
Parameter
Symbol
Limit Values
Unit
Test Conditions
–
Min.
Max.
-0.3
40
V
-0.5
5
V/µs –
-0.3
5.5
V
–
-27
40
V
–
5.1.5
VS
dVS/dt
Supply Voltage Slew Rate
Regulator Output Voltage
Vcc1µC/2/3
CAN Bus Voltage (CANH, CANL)
VCANH/L
Differential Voltage CANH, CANL, SPLIT VdiffESD
-40
40
V
CANH-CANL VUV OFF;
5.2.5
Junction Temperature
-40
150
°C
–
5.2.6
Undervoltage “OFF”
3
4
V
-1)
5.2.7
Undervoltage “ON
4.5
5.5
V
-1)
5.2.8
Supply Voltage for Limp Home
Output Active
fclkSPI
fclkSPI
Tj
VUV OFF
VUV ON
VS_LH
5.5
40
V
Pull up to VS
RLHO = 40kΩ
tpulse = 400 ms
40 V load dump;
Ri = 2Ω
1) In the case Vs < VUVOFF, the SBC is switched OFF and will restart in INIT Mode at next Vs rising.
2) During load dump, the others pins remains in their absolute maximum ratings
3) Not subject to production test, specified by design
Note: Within the functional range the IC operates as described in the circuit description. The electrical
characteristics are specified within the conditions given in the related electrical characteristics table.
Data Sheet
17
Rev. 1.0, 2009-03-31
TLE8264-2E
General Product Characteristics
5.3
Pos.
5.3.1
5.3.2
Thermal Characteristics
Parameter
Symbol
Limit Values
Min.
Typ.
Unit
Test Conditions
Max.
Junction Ambient
RthJA_1L
–
40
K/W
1) 3)
300 mm2
cooling area
Junction Ambient
RthJA_4L
–
25
K/W
2) 3)
Junction to Soldering Point
RthJSP
–
5
–
K/W
3)
2s2p + 600 mm2
cooling area
Thermal Prewarning and Shutdown Junction Temperatures;
5.3.3
VCC1µC, Thermal Pre-warning
5.3.4
VCC1µC, Thermal Prewarning
5.3.5
VCC1µC, VCC2 Thermal Shutdown
TjPW
120
145
170
°C
-3)
∆TPW
–
25
–
K
3)
TjSDVcc
150
185
200
°C
3)
ON Temperature
Hysteresis
Temperature
5.3.6
VCC1µC, VCC2 Thermal Shutdown
Hysteresis
∆TSDVcc
–
35
–
K
3)
5.3.7
VCC1µC, Ratio of SD to PW
Temperature
TjSDVcc/
–
1.20
–
–
3)
5.3.8
CAN Transmitter Thermal
Shutdown Temperature
TjSDCAN
150
–
200
°C
3)
5.3.9
CAN Transmitter Thermal
Shutdown Hysteresis
∆TCAN
–
10
–
K
3)
5.3.10
LIN Transmitter Thermal Shutdown TjSDLIN
Temperature
150
–
200
°C
3)
5.3.11
LIN Transmitter Thermal Shutdown ∆TLIN
Hysteresis
–
10
–
K
3)
TjPW
1) Specified Rthja value is according to Jedec JESD51-2,-5,-7 at natural convection on FR4 single layer. The product (chip +
package) was simulated on a 76.4 x 114.3 x 1.5 mm board.
2) According to Jedec JESD51-2,-5,-7 at natural convection on 2s2p board for 2W. Board: 76.2x114.3x1.5mm³ with 2 inner
copper layers (35µm thick)., with thermal via array under the exposed pad contacted the first inner copper layer and
600mm2 cooling are on the top layer (70µm)
3) Not subject to production test; specified by design;
Data Sheet
18
Rev. 1.0, 2009-03-31
TLE8264-2E
General Product Characteristics
5.4
Current Consumption
VS = 5.5 V to 28 V; all outputs open; Without VCC3; Tj = -40 °C to +150 °C; all voltages with respect to ground;
positive current defined flowing into pin; unless otherwise specified.
Pos.
Parameter
Symbol
Limit Values
Min.
Typ.
Max.
Unit
Test Condition
Normal Mode;
5.4.1
Current Consumption for
Internal Logic
IVS_logic
–
–
2
mA
SBC Normal Mode
ICC1µC = ICC2 = 0mA;
CAN OFF mode;
LIN OFF mode
5.4.2
IVS_CAN
Additional current
Consumption for CAN Cell
–
–
10
mA
CAN Normal Mode;
Recessive state; VCC2
connected to VCCHSCAN
VTxD = Vcc1µC;
without RL
–
–
12
mA
CAN Normal Mode;
dominant state; VCC2
connected to VCCHSCAN
VTxD = low;
without RL;
–
–
3.0
mA
LIN Normal Mode;
recessive state;
without RL;
VTxD = Vcc1µC
–
–
5.0
mA
LIN Normal Mode;
dominant state;
without RL;
VTxD = low
–
58
75
µA
SBC Stop Mode;
Vs = 13.5 V;
VCC1µC“ON”;
VCC2/3“OFF”
CAN/LIN wake capable;
Tj = 25°C
65
85
–
70
90
–
78
100
5.4.3
Additional Current
IVS_LIN
Consumption per LIN Cell
Stop Mode
5.4.4
Current Consumption
Data Sheet
IVS
19
Tj = 85°C1)
µA
SBC Stop Mode;
Vs = 13.5 V;
VCC1µC/2“ON”;
VCC3“OFF”
CAN/LIN wake capable;
Tj = 25°C
Tj = 85°C1)
Rev. 1.0, 2009-03-31
TLE8264-2E
General Product Characteristics
5.4
Current Consumption (cont’d)
VS = 5.5 V to 28 V; all outputs open; Without VCC3; Tj = -40 °C to +150 °C; all voltages with respect to ground;
positive current defined flowing into pin; unless otherwise specified.
Pos.
Parameter
Symbol
Limit Values
Min.
Unit
Test Condition
µA
SBC Sleep Mode;
Tj = 25°C
Vs = 13.5 V;
VCC1µC/2/3“OFF”
CAN/LIN wake capable;
Typ.
Max.
28
40
32
50
1
–
µA
1)
12
–
µA
1)
Sleep Mode
5.4.5
5.4.6
5.4.7
Current consumption, all
Wake Up Sources
available.
Quiescent Current
Reduction when one
Wake Capable LIN Cell
Disabled
Quiescent Current
Reduction when Wake
Capable CAN Cell
Disabled
IVS_sleep_ –
SBC
IVS_sleep_ 0.5
Tj = 85°C1)
LIN
IVS_sleep_ 5
CAN
SBC Sleep Mode;
Tj = 25°C;
VS = 13.5 V;
VCC1µC/2/3“OFF”
CAN/LIN 1_2 wake
capable; LIN3 OFF
SBC Sleep Mode;
Tj = 25°C;
VS = 13.,5 V;
VCC1µC/2/3“OFF”
LIN 1..3 wake capable;
CAN OFF
1) Not subject to production test; specified by design
Data Sheet
20
Rev. 1.0, 2009-03-31
TLE8264-2E
Internal Voltage Regulator
6
Internal Voltage Regulator
6.1
Block Description
V CC 1µC
Vs
V CC2
Vref
1
State
Machine
Overtemperature
Shutdown
Bandgap
Reference
INH
1
Vref
Charge
Pump
INTE RNA L RE GULA TOR DIA GRA M. V S D
GND
Figure 4
Functional Block Diagram
The internal voltage regulators are dual low-drop voltage regulators that can supply loads up to ICC1µC/2_max. An
input voltage up to VSMAX is regulated to Vcc1µC/2_nom = 5.0 V with a precision of ±2%. Due to its integrated reset
circuitry, featuring two SPI configurable power-on timing (tRDx) and three SPI configurable output voltages (VRTx)
monitoring, the device is well suited for microcontroller supply. The design enables stable operation even with
ceramic output capacitors down to 470nF, with ESR < 1 Ω @ f = 10 kHz. The device is designed for automotive
applications, therefore it is protected against overload, short circuit, and overtemperature conditions. Figure 4
shows the functional block diagram. If the VS voltage is lower than VUV_OFF, the DMOS of the voltage regulator is
switched to high impedance. The body diodes of the DMOS might go into conduction when VCC1µC or VCC2 > VS
(no reverse protection).
6.2
Internal Voltage Regulator Modes
It is possible to turn Vcc1µC via SBC Modes and Vcc2 activity ON or OFF via SPI command or by entering SBC
modes. The limiting current for the both regulators is ICC1µC_max/ICC2.
6.3
Internal Voltage Regulator Modes with SBC Mode
Depending on the SBC Mode in use, Vcc1µC and Vcc2 can be either ON or OFF by definition, Vcc2 can be also turned
ON or OFF, via SPI. Table 3 identifies the possible states of the voltage regulators, based on the various SBC
modes.
Data Sheet
21
Rev. 1.0, 2009-03-31
TLE8264-2E
Internal Voltage Regulator
Table 3
Internal Voltage Regulators States
SBC Mode
Vcc1µC
INIT Mode
ON
OFF
Normal Mode
ON
ON
Sleep Mode
OFF
OFF
Restart Mode
ON
unchanged
Software Flash Mode
ON
ON
OFF
Stop Mode
ON
ON
OFF
Fail-Safe Mode
OFF
OFF
6.4
Application information
6.4.1
Timing Diagram
Vcc2
OFF
Figure 5 shows the ramp up and down of the VS, and the dependency of Vcc1µC. At the first ramp up from SBC Init
Mode, the reset threshold VRT and time tRO are set to the default value. See Chapter 11.1
Vs
VUV ON
V UV OFF
t
Vcc1µC
VRTx,r
VRTx,f
t
GND
RO
SBC OFF
SBC Init
Any mode
SBC OFF
t
Figure 5
Ramp up / Down of Main Voltage Regulator
An undervoltage time-out on Vcc1µC is implemented. Refer to Chapter 13 for more information on this function.
6.4.2
Under voltage detection at Vcc2
The Vcc2 voltage regulator integrates an under voltage detection. When Vcc2 voltage goes below VUV_VCC2, the
failure is indicated by an interrupt and the failure is reported into the diagnosis frame of the SPI.
Data Sheet
22
Rev. 1.0, 2009-03-31
TLE8264-2E
Internal Voltage Regulator
6.5
Electrical Characteristics
VS = 5.5 V to 28 V; CCC1µC = CCC2 = 470 nF; all outputs open; SBC Normal Mode;
Tj = -40 °C to +150 °C; all voltages with respect to ground; positive current defined flowing into pin; unless
otherwise specified.
Pos.
Parameter
Symbol
Limit Values
Unit Test Condition
Min.
Typ.
Max.
Voltage Regulator; Pin Vcc1 µC
6.5.1
Output Voltage
VCC1µC
4.9
5.0
5.1
V
0 mA VUVON until Init Mode
is left). If the pin is low for the Init Mode time, Software Development Mode is reached. The mode is stored during
the complete time where VS is above VUVOFF. It means to leave Software Development Mode, the SBC must go
back to SBC OFF mode.
Data Sheet
67
Rev. 1.0, 2009-03-31
TLE8264-2E
Limp Home
13.3
Activation of the Limp Home Outputs
The reason to activate the Limp Home pins and the consequences are listed in Table 12 and Table 13.
Table 12
Limp Home, Function of the SBC Mode
SBC Mode
Limp Home Outputs
INIT Mode
OFF
Normal Mode
OFF
ON via SPI
Stop Mode
Unchanged
Sleep Mode
Unchanged
Restart Mode
Unchanged
Fail-Safe Mode
ON
SW Flash Mode
Unchanged
Table 13
ON if it was ON until the successful Watchdog
setting and deactivation via SPI.
Automatic Activation of Limp Home Output
SBC Mode
Reason
INIT Mode
INIT time-out (tINITTO)
Normal Mode
1st Watchdog failure (config 1/2)
2nd Watchdog failure (config 3/4)
Restart Mode
Reset output permanent short circuit to Vcc1µC
Reset output permanent short circuit to GND
Vcc1µC undervoltage time-out
Any mode
If previously turned ON in SBC Normal Mode, via SPI command
Vcc1µC thermal shutdown
13.4
Release of the Limp Home Outputs
When Limp Home is activated via SPI command, then it is released via SPI command. This is useful for diagnosis
purpose for example.
Otherwise, the Limp Home outputs are released only in SBC Normal Mode with the following conditions: After the
device has been set to SBC Restart Mode, automatically entering SBC Normal Mode, a successful Watchdog
trigger must be sent via SPI. At this point, the Limp Home outputs remain active. Then the microcontroller needs
to send by SPI command the deactivation of the Limp Home.
13.5
Vcc1µC undervoltage time-out
A Vcc1µC undervoltage time-out condition is given, when
1) the Vcc1µC output voltage is below the reset threshold (VRT1, VRT2, VRT3),
2) VS is higher then the threshold (VSthUV1, VSthUV2, VSthUV3) and
3) the condition is valid longer then the Vcc1µC under voltage time-out (tVcc1UVTO).
A Vcc1µC undervoltage time-out will sent the device into Fail-Safe Mode. Limp Home output stag will be activated
(for Vs > VLHUV)
Figure 34 gives an example of the Limp Home output activation, due to a Vcc1µC undervoltage time-out.
Data Sheet
68
Rev. 1.0, 2009-03-31
TLE8264-2E
Limp Home
Vs
VSthUVx
t
Vcc1µC
VRTx
VRTx
GND
t
RO
tVcc1UVTO
SBC Sleep
Limp home
SBC Restart
Wake Up
tRDx
SBC Normal
SBC Restart
SBC Fail safe
t
tRR
GND
t
undervoltage time out.vsd
Figure 34
Data Sheet
Vcc1µC undervoltage time-out timing
69
Rev. 1.0, 2009-03-31
TLE8264-2E
Limp Home
13.6
Electrical Characteristics
VS = 5.5 V to 28 V; Tj = -40 °C to +150 °C; SBC Normal Mode; all voltages with respect to ground; positive current
defined flowing into pin unless otherwise specified.
Pos.
Parameter
Symbol Limit Values
Min.
Typ.
Max.
–
1
–
Unit
Test Condition
–
With SPI set.
Limp Home /LH _SI;
Watchdog edge count
difference to set Limp
Home activated
nLH
13.6.2
Limp Home low output
voltage (active)
VLHLO
–
0.2
0.4
V
ILH = 1mA
13.6.3
Limp Home high output
current (inactive)
ILHHI
0
–
2
µA
VLH = 28V
13.6.4
INIT Time-out
256
–
ms
1)
13.6.5
Vcc1µC under voltage
Time-out
tINITTO
–
tVcc1UVTO 900
1024
1150
ms
13.6.6
Vs threshold for Vcc1µC
VSthUV1
5.3
–
6.3
V
VRT1 default setting
under voltage Time-out
(Vs needs to be above, to V
SthUV2
activate Vcc1µC under
VSthUV3
voltage Time-out)
4.3
–
5.3
V
4.0
–
5.0
V
VRT2 SPI option
VRT3 SPI option
4.5
–
5.5
V
–
0.2
–
V
–
13.6.1
2
13.6.7
Threshold for Limp Home VLHUV
minimum Vs
13.6.8
Limp Home Vs voltage
hysteresis
VLHUVhys –
Default Setting
LH _SI;
13.6.9
Limp Home side indicator fLHSI
frequency
1.125
1.25
1,375
Hz
–
13.6.10
Limp Home side indicator dSI
duty cycle
–
50
–
%
–
–
–
3
V
–
VTest,hys
VTest,LO
100
300
700
mV
–
1
–
–
V
–
RTest
20
40
80
kΩ
VLH_PL/Test = 0V
LH_PL/Test
13.6.11
HIGH Level Input Voltage VTest,HI
Threshold
13.6.12
Input Hysteresis
13.6.13
LOW Level Input Voltage
Threshold
13.6.14
Pull-up Resistor
SBC Init Mode
13.6.15
Limp Home pulsed light
frequency
fLH_PL
90
100
110
Hz
–
13.6.16
Limp Home pulsed light
duty cycle
dPL
-
20
-
%
–
1) Not subject to production test, specified by design.
Data Sheet
70
Rev. 1.0, 2009-03-31
TLE8264-2E
Configuration Select
14
Configuration Select
14.1
Configuration select
The Configuration select is used to set the device for two different SBC behaviors; please refer to Chapter 4.2.1
for detailed information. Depending on the requirements of the application, the Vcc1µC is switched off and the device
goes to Fail-Safe Mode in case of watchdog fail (1 or 2 fail) or reset clamped. To turn Vcc1µC OFF (Config 2/4), the
INT pin is not connected to a pull up resistor externally. In case the Vcc1µC is not switched off (Config 1/3) the INT
pin is connected to Vcc1µC with a pull up resistor. The configuration is only read during Init Mode, after that the
configuration is stored.
14.2
Config Hardware Descriptions
In Init Mode before the RO pin goes high the INT pin is pulled to low with a weak pull down resistor RCFG, the pull
up resistor RINT is switched off. When Vcc1µC is high, above the reset threshold VRT1 and before the RO pin goes
high the level on the INT pin is monitored to select the configuration. With RO going high in Init Mode the pull up
resistor RINT is switched on.
Figure 35 gives the electrical equivalents to the configuration function of the INT pin.
Vc c 1µC
Configuration logic
R INT
Interrupt logic
INT
Time
out
R CFG
INTERRUPT BLOCK_CONFIG.VSD
Figure 35
Config Logic Diagram
Electrical characteristics are listed in chapter Chapter 12.5
Data Sheet
71
Rev. 1.0, 2009-03-31
TLE8264-2E
Serial Peripheral Interface
15
Serial Peripheral Interface
15.1
SPI Description
The 16-bit wide Control Input Word is read via the data input SDI, which is synchronized with the clock input CLK
supplied by the microcontroller. The output word appears synchronously at the data output SDO (see Figure 36).
The transmission cycle begins when the chip is selected by the input CSN (Chip Select Not), LOW active. After
the CSN input returns from LOW to HIGH, the word that has been read in becomes the new control word. The
SDO output switches to tri-state status (high impedance) at this point, thereby releasing the SDO bus for other use.
The state of SDI is shifted into the input register with every falling edge on CLK. The state of SDO is shifted out of
the output register after every rising edge on CLK. The number of received input clocks is supervised by a
modulo-16 operation and the Input / Control Word is discarded in case of a mismatch. This error is flagged in the
following SPI output by a “HIGH” at the data output (SDO pin, bit FO) before the first rising edge of the clock is
received. The SPI of the SBC is not daisy chain capable.
CSN high to low: SDO is enabled. Status information transferred to output shift register
CSN
time
CSN low to high: data from shift register is transferred to output functions
CLK
time
Actual data
SDI
FI
-
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
New data
FI
0 1
+ +
time
SDI: will accept data on the falling edge of CLK signal
Actual status
SDO
FO
-
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
New status
FO
0
+
1
+
time
SDO: will change state on the rising edge of CLK signal
Figure 36
SPI Data Transfer Timing
15.2
Corrupted data in the SPI data input
When the microcontroller send a wrong SPI command to the SBC, the SBC ignores the information. Wrong SPI
command can be either a number of bits different of 16, the mode selection (MS2..0) = 000 or requesting to go to
an SBC mode which is not allowed by the state machine, for example from SBC Stop Mode to SBC SW Flash
Mode. In that case, an interrupt is generated (if not inhibited) and the bit SPI Fail is set. Since the SPI data is
corrupted, the next SPI output data will remain the former one (the information is then repeated).
Data Sheet
72
Rev. 1.0, 2009-03-31
TLE8264-2E
Serial Peripheral Interface
15.3
SPI Input Data
MSB
Input
Data
LSB
15 14 13 12 11 10
9
8
7
6
WD
refresh
Configuration Registers
3
2
CS2
CS1
CS0
MS2
Configuration Select
WK 1 WK 0
WK
WK pin WK pin LIN3
WK
LIN2
WK
LIN1
WK
CAN
000
Fail
SPI
ICC3 >
ICC3max
UV
VCC2
OT
VCC2
OT
OTP
Vcc 1µC
001
HS CAN
LIN3 LIN3 LIN 2 LIN2 LIN1 LIN1
failure failure failure failure failure failure
1
0
1
0
1
0
CAN
Bus
CAN CAN
failure failure
1
0
010
Res.
Wrong
Reset
WD set
UV
Vcc3
Reserved
WD to
LH
REGISTER
4
Res.
Res.
INTERRUPT
MASK
5
LIN
10.4k
Cyclic
L.H.
VCC2 WK PIN VCC3 Reset
WK
On/off On/Off On/off On/off Delay
On /off
CAN
1
CAN
0
Ti.
CHK
WD
Out /
SUM On/Off
Win.
LIN3
1
Set to
1
LIN 3
0
LIN2
1
LIN 2
0
RT1
RT0
LIN1
1
LIN 1
0
Window /Time out Watchdog
Timing Bit Position: 10 .. 6
LH Reserved
2 LH 1 LH 0
Test 2 Test 1 Test 0
1
MS1
0
MS0
Mode Selection
Bits
not valid
Restart
SW Flash
011
Normal
100
Sleep
101
Stop
110
Fail safe
111
Read Only
000
001
010
011
100
101
110
111
SPI data input TLE8264.vsd
Figure 37
Data Sheet
16-Bit SPI Input Data / Control Word
73
Rev. 1.0, 2009-03-31
TLE8264-2E
Serial Peripheral Interface
15.4
SPI Output Data
MSB
LSB
Output 15 14 13 12 11 10
Data
WK
state
8
7
6
Configuration Registers
INT
Status or
INTERRUPT
event
9
Res.
Wrong
Reset
WD set
Cyclic WK 1 WK 0
WK
WK WK pin WK pin LIN3
Fail
SPI
ICC3 >
ICC3max
UV
Vcc3
UV
VCC2
LIN3 LIN3 LIN 2 LIN2 LIN1 LIN1
failure failure failure failure failure failure
1
0
1
0
1
0
LIN
10.4k
CAN
0
LIN3
1
CHK
WD
SUM On/Off
Ti.
Out /
Win.
Set to
1
Res.
RM0
LH 2
LIN 3
0
LIN2
1
3
2
CS2
CS1
CS0
MS2
WK
LIN2
WK
LIN1
WK
CAN
000
OT
VCC2
OT
OTP
Vcc1µC
001
HS CAN
CAN CAN
failure failure
1
0
010
CAN
Bus
Cyclic
L.H.
VCC2 WK PIN VCC3 Reset
WK
On/off On/Off On/off On/off Delay
On /off
CAN
1
4
Configuration Select
Reserved
WD to
LH
5
LIN 2
0
RT1
RT0
LIN1
1
LIN 1
0
1
MS1
0
MS0
Mode Selection
Bits
Init
Restart
SW Flash
011
Normal
100
Sleep
101
Stop
110
Fail Safe
111
Reserved
000
001
010
011
100
101
REGISTER
RM1
Window /Time out Watchdog
Timing Bit Position: 10 .. 6
LH 1
LH 0
Test 2 Test 1 Test 0
110
111
SPI_Settings_out_TLE8264.vsd
Figure 38
16-bit SPI Output Data / Control Word
15.5
SPI Data Encoding
15.5.1
WD Refresh bit / WK state
The WD Refresh bit is used to trigger the Watchdog. The first trigger should be a 1, and then a 0. For more details,
please refer to Chapter 11.2.
The WK state bit gives the voltage level at the WK pin. A 1 indicates a high level, a 0 a low level.
Data Sheet
74
Rev. 1.0, 2009-03-31
TLE8264-2E
Serial Peripheral Interface
15.5.2
SBC Configuration Setting and Read Out
15.5.2.1
Mode selection bits and configuration select
Table 14 lists the encoding of the possible SBC mode. Except SBC Restart and Init Mode which are most of time
entered automatically, all others SBC mode are accessible on request of the microcontroller. The microcontroller
should send the correct mode selection bits to set the SBC in the respective mode. The output indicates the SBC
mode where the SBC currently is or was, depending on the situation.
Table 14
Mode Selection Bits
MS2
MS1 MS0
Data Input
Data Output
0
0
0
Not valid (the complete SPI word is ignored) Show the device was in Init previous SPI data
0
0
1
Set the SBC to SBC Restart Mode.
(In SW Flash mode only)
0
1
0
Set the SBC to Software Flash Mode
Show the device is SBC Software Flash Mode
0
1
1
Set the SBC to SBC Normal Mode
Show the device is in SBC Normal Mode
1
0
0
Set the SBC to SBC Sleep Mode
Show the device was in SBC Sleep Mode
1
0
1
Set the SBC to SBC Stop Mode
Show the device is in SBC Stop Mode
1
1
0
Set the SBC to SBC Fail-Safe Mode
Show the device was in SBC Fail-Safe Mode
(In SBC Software Development mode only)
1
1
1
Set the SBC to Read Only SPI access. The Reserved
configuration register needs to be selected.
The SPI information on SDO is provided in
the same SPI frame. No write access is
done in this mode.
Bit 15 (Watchdog) has to be served
correctly.
Show the device was in Restart previous SPI
data
Table 15 lists the eight possible configuration selection. Some are related to event or state of the different part of
the SBC, others are used to configure the SBC in the application specific set up.
Table 15
Configuration Select Encoder (for Data Input and Output)
CS2
CS1
CS0
Configuration Register Select
0
0
0
Wake Register Interrupt
0
0
1
SBC Failure Interrupt
0
1
0
Communication Failure Interrupt
0
1
1
Reserved
1
0
0
SBC Configuration Register
1
0
1
Communication Setup Register
1
1
0
Watchdog Configuration Register
1
1
1
Limp Home / Diagnosis Register
Data Sheet
75
Rev. 1.0, 2009-03-31
TLE8264-2E
Serial Peripheral Interface
15.5.2.2
Interrupt Register Encoder
Table 16 lists all interrupts the SBC can generates. The microcontroller should read the correct register to release
the INT pin. By default, all interrupt sources are enabled. The microcontroller can decide to inhibit a specific
interrupt source.
Table 16
CS
Interrupt Register encoder 1)
Bit Name
Default
Value
(INPUT)
Default
Value
Data Input
Data Output
(OUT)
Configuration select 000 (Wake register interrupt)
000
WK CAN
1
0
Interrupt enabled (1) disabled
(0) for wake event on CAN
Wake on CAN (1)
WKLINx
1
0
Interrupt enabled (1) disabled
(0) for wake event on LIN
Wake on LINx (1)
WK 1 WK pin
WK 0 WK pin
11
00
Interrupt enabled (1) disabled
(0) for wake pin event.
00 No interrupt
10 Interrupt for a LOW to HIGH
transition on WK
01 Interrupt for HIGH to LOW
transition on WK
11 Interrupt for both HIGH to
LOW and LOW to HIGH on WK
Wake on WK pin
00 No wake
10 Interrupt for a LOW to HIGH
transition on WK
01 Interrupt for HIGH to LOW
transition on WK
11 Interrupt for both HIGH to
LOW and LOW to HIGH on WK
Cyclic WK
n.a
0
n.a
Cyclic WK (1)
INT
n.a
0
n.a
Indicates that there is a status
bit or uncleared event in
configuration select 001 and/or
010. If set read the two register
Data Sheet
76
Rev. 1.0, 2009-03-31
TLE8264-2E
Serial Peripheral Interface
Table 16
CS
Interrupt Register encoder (cont’d)1)
Bit Name
Default
Value
(INPUT)
Default
Value
Data Input
Data Output
(OUT)
Configuration select 001 (SBC Failure interrupt)
001
OTP_Vcc1µC
1
0
Interrupt enabled (1) disabled Vcc1µC temperature pre warning
(0) for temperature pre-warning (1)
OT_HSCAN
1
0
Interrupt enabled (1) disabled
(0) for temperature shutdown
HS CAN temperature shutdown
(1)
OT_Vcc2
1
0
Interrupt enabled (1) disabled
(0) for temperature shutdown
Vcc2 temperature shutdown (1)
UV_Vcc3
1
0
Interrupt enabled (1) disabled Undervoltage detection on Vcc3
(0) for undervoltage detection (1)
or due to back to normal voltage
SPI Fail
1
0
Interrupt enabled (1) disabled
(0) for SPI corrupted data.
SPI input corrupted data (1)
Reset
1
0
Interrupt enabled (1) disabled
(0) for reset information
(only in SBC Software
Development Mode)
Reset (1)
(only in SBC Software
Development Mode)
Wrong WD set
1
0
Interrupt enabled (1) disabled
(0) for incorrect Watchdog
setting
Incorrect WD programming for
data output
UV Vcc2
1
0
Interrupt enabled (1) disabled Under voltage detected at Vcc2
(0) for undervoltage detection at
Vcc2
ICC3 > ICC3max
1
0
Interrupt enable (1) disabled (0) Over current detected at Vcc3
for over current at Vcc3
Configuration select 010 (Communication failure interrupt)
010
CAN failure 1
CAN failure 0
n.a
1
0
0
Interrupt enabled (1) disabled
(0) for CAN failure
CAN failure Refer to Table 17
CAN Bus
1
0
Interrupt enabled (1) disabled
(0) for CAN bus failure
CAN bus failure detected (1)
LINx failure 1
LINx failure 0
n.a
1
0
0
Interrupt enabled (1) disabled
(0) for LIN failure
LIN failure. Refer to Table 17
1) A value of 0 will set the SBC into the opposite state.
Data Sheet
77
Rev. 1.0, 2009-03-31
TLE8264-2E
Serial Peripheral Interface
15.5.2.3
CAN / LIN failure encoder
Table 17 describes the encoding of the possible internal CAN and LIN failures.
Table 17
CAN / LIN Failure Encoder
CAN / LINx 1 Failure CAN / LINx 0 Failure Fault
0
0
No failure
0
1
TxD shorted to GND or bus dominant clamped
1
0
RxD shorted to Vcc
1
1
TxD shorted to RxD
15.5.2.4
Configuration encoder
Table 18 lists the configuration register of the SBC. The microcontroller can change the settings. If no settings are
changed the default values are used. The current value can be read on the SPI Data Out.
Table 18
Configuration Encoder
Configuration Bit Name
Select
Default Default
Value
Value
(INPUT) (OUT)
State
Configuration select 100 (SBC Configuration Register)
100
Data Sheet
RT10
01
01
Reset threshold setting. Please refer to Table 19
Reset delay
1
1
Long reset window
Vcc3 ON /OFF
0
0
Vcc3 is activated (1)
WK pin ON / OFF 1
1
The wake pin will wake the SBC
Vcc2 On / Off
0
0
Vcc2 is activated (1)
LH ON / OFF
0
0
Limp Home output state. Activated (1) when entry
condition is met.
Cyclic WK On /
Off
0
0
Activation (1) of the cyclic wake
WD to LH
1
1
Watchdog failure to Limp Home active.
0 = only one Watchdog failure brings to Limp Home
activated.
1 = two consecutive Watchdog failures bring to Limp
Home activated.
78
Rev. 1.0, 2009-03-31
TLE8264-2E
Serial Peripheral Interface
Table 18
Configuration Encoder
Configuration Bit Name
Select
Default Default
Value
Value
(INPUT) (OUT)
State
Configuration select 101 (SBC communication set up register)
101
LIN 10.4k
1
1
LIN cells are in LIN Low slope Mode (1)
CAN 1.0
00
00
The CAN cell is in:
00 = CAN OFF
01 = CAN is Wake Capable
10 = CAN Receive Only Mode
11 = CAN Normal Mode
LINx 1.0
00
00
The LIN cell is in:
00 = LIN OFF
01 = LIN is Wake Capable
10 = LIN Receive Only Mode
11 = LIN Normal Mode
Configuration select 110 (SBC Watchdog register)
110
Ti. Out / Win.
1
1
Time-out Watchdog is activated
Set to 1
1
1
Bit is reserved and fix set to “1”. Set to 1 in SW.
WD ON / OFF
1
1
Watchdog is activated
CHK SUM
1
1
Check sum of the bit 13...6
In case the CHK SUM is wrong, the device remains in
previous valid state.
CHKSUM = Bit13 ⊕ … ⊕ Bit6
Configuration select 111 (Limp Home / Diagnosis register)
111
-
15.5.2.5
Reserved for input
For output, refer to Table 21, Table 22 and Table 23
Reset encoder
Table 19 lists the three possible reset thresholds. Please also refer to Chapter 11.3 to get the exact voltage
threshold.
Table 19
Reset Encoder
RT1
RT0
Threshold Selected
0
0
Not Valid. Device remains at previous threshold
0
1
VRT1 (default setting at SBC Init),
1
0
VRT2
1
1
VRT3
15.5.2.6
SBC Watchdog encoder
Table 20 list the 32 possible watchdog timer.
Data Sheet
79
Rev. 1.0, 2009-03-31
TLE8264-2E
Serial Peripheral Interface
Table 20
Watchdog Encoder
Bit 10...6
Decimal calculation (ms)
00000
0
00001
1
00010
2
...
...
...
01111
15
256 (default setting)
10000
16
10001
17
352
...
...
...
11110
30
976
11111
31
1024
15.5.3
(n+1) × 16
n = decimal value of
setting
n × 48 - 464
Timer (ms)
16
32
48
304
SBC Diagnostic encoder
The SBC offers diagnostics information. The encoding of the different possible failures are listed in the following
table. The description apply only to data output.
15.5.3.1
Reason for restart and reset
Reason for reset, without activation of the Limp Home and the way it is encoded are summed up in Table 21. The
bits are cleared by reading the register with Read-Only command. When coming from Sleep Mode or Fail Safe
Mode the bits are cleared.
Table 21
RM1
Reason to Enter SBC Restart Mode without Limp HomeLimp Home activation
RM0
Cause for entering SBC Restart Mode
0
0
No reset has occurred or Limp Home activated
0
1
Undervoltage on Vcc1µC
1
0
First Watchdog failure (config 3 and 4) or no acknowledge of the Cyclic Wake-up
1
1
SPI command in SBC Software Flash Mode or reset low from outside
Data Sheet
80
Rev. 1.0, 2009-03-31
TLE8264-2E
Serial Peripheral Interface
15.5.3.2
Limp Home failure encoder
Table 22 describes the encoding of all possible reason to activate automatically the Limp Home output. Bits are
set back to “000” when switching Limp Home off via SPI.
Table 22
LH2
Limp Home Failure Diagnosis
LH1
LH0
Failure1)
0
0
0
No failure
0
0
1
Vcc1µC undervoltage Time-out
0
1
0
One Watchdog failure (config 1 and 2)
0
1
1
Two consecutive Watchdog failures (config 3 and 4)
1
0
0
INIT Mode Time-out
1
0
1
Temperature shutdown at Vcc1µC
1
1
0
Reset clamped
1
1
1
Reserved
15.5.3.3
Test pin and failure to Limp Home configuration read out
The SBC allows to read the hardware setting of the configuration that is done via the INT pin, as well as the test
pin and the WD to LH bit. Table 23 describes the encoding of these informations.
Table 23
Test pin and SBC Configuration
Test1
Test0
Test Read Out1)
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
Vcc1µC remains ON in SBC Restart Mode after one Watchdog failure (config 1)
Vcc1µC is OFF in SBC Fail-Safe Mode after one Watchdog failure (config 2)
Vcc1µC remains ON in SBC Restart Mode after two Watchdog failures (config 3)
Vcc1µC is OFF in SBC Fail-Safe Mode after two Watchdog failures (config 4)
Software Development Mode. In case of watchdog failure Vcc1µC remains ON, no
Test2
reset is generated and Restart Mode or Fail-Safe Mode are not entered.
1
0
1
Software Development Mode. In case of watchdog failure Vcc1µC remains ON, no
reset is generated and Restart Mode or Fail-Safe Mode are not entered.
1
1
0
Software Development Mode. In case of watchdog failure Vcc1µC remains ON, no
reset is generated and Restart Mode or Fail-Safe Mode are not entered.
1
1
1
Software Development Mode. In case of watchdog failure Vcc1µC remains ON, no
reset is generated and Restart Mode or Fail-Safe Mode are not entered.
1) Refer also to Chapter 4.2.1
Data Sheet
81
Rev. 1.0, 2009-03-31
TLE8264-2E
Serial Peripheral Interface
15.6
SPI Output Data
15.6.1
First SPI output data
Since the SPI output data is sent when the SBC is receiving data, the output data are dependent of the previous
SPI command, if no Read Only command is used. Under some conditions there is no “previous command”.
Table 24 gives the first SPI output data that is sent to the microcontroller when entering SBC Normal Mode,
depending on the mode where the SBC was before receiving the first SPI command.
.
Table 24
First SPI output data frame
Previous SBC mode
Mode selection bits (MS2...0) Configuration select (CS 2..0)
Sleep mode
Sleep mode
Wake Register interrupt1)
Fail-Safe mode
Fail-Safe mode
Limp Home register1)
Restart mode when failure and config 1 / 3
Restart mode
Limp Home register1)
Restart mode when microcontroller has sent
to Restart mode
Restart mode
SBC Configuration Register
SBC Init mode
Init mode
SBC Configuration Register
1) This does not clear the bits. It will be reset when the microcontroller requests the read out
Data Sheet
82
Rev. 1.0, 2009-03-31
TLE8264-2E
Serial Peripheral Interface
15.6.2
Read Only command
In the Mode Selection Bits a Read Only can be selected. The Read Only access clears the INT bits that are
selected in the Configuration Select (some interrupt bits show a state, and can not be cleared with a SPI read).
With this SPI command no write access is done to the SBC, and the mode of the SBC is not changed. The
watchdog can also be triggered with a Read Only command.
The Read Only command delivers the information requested with the Configuration Select in the same SPI
command on the SDO pin. As all other SPI commands deliver the requested information with the next SPI
command.
Figure 39 shows an example of a Read Only access. The bits are shown with LSB first, on the left side in
difference to the register description.
DI
0
1
2
3
4
5
MS0
MS1
MS2
CS0
CS1
CS2
Mode Selection
Bits
1
DO
1
1
0
0
x
x
6
7
8
9
10 11 12 13 14 15
2
3
4
5
CS0
CS1
CS2
0
0
x
x
x
x
x
x
x
x
x
x
x
x
x
1
2
3
4
5
MS1
MS2
CS0
CS1
CS2
1
DO
1
0
x
6
7
1
x
x
1
1
x
x
x
6
7
8
9
10 11 12 13 14 15
x
x
0
1
2
3
4
5
MS1
MS2
CS0
CS1
CS2
1
1
0
0
0
9
10 11 12 13 14 15
x
x
WD
refresh
x
x
x
x
x
x
x
x
WK
state
Configuration Registers
Configuration Select
1
8
Configuration Registers
Configuration Select
MS0
Mode Selection
Bits
WK
state
Configuration Registers
Configuration Select
0
x
0
MS0
Mode Selection
Bits
WD
refresh
Configuration Registers
x
MS2
DI
10 11 12 13 14 15
x
1
0
9
x
MS1
1
8
0
0
1
7
Configuration Select
MS0
Mode Selection
Bits
6
x
x
x
TIME
Figure 39
Read Only Command
Figure 40 shows an example of an SPI write access in normal mode for comparison. The requested information
is sent out with the next SPI command.
DI
0
1
2
3
4
5
MS0
MS1
MS2
CS0
CS1
CS2
Mode Selection
Bits
1
DO
1
0
0
0
x
x
6
7
8
9
10 11 12 13 14 15
2
3
4
5
CS0
CS1
CS2
0
0
x
x
x
x
x
x
x
x
x
x
x
x
x
1
2
3
4
5
MS1
MS2
CS0
CS1
CS2
1
DO
1
0
x
1
1
WD
refresh
Configuration Registers
x
x
6
7
8
9
10 11 12 13 14 15
2
3
4
5
CS0
CS1
CS2
0
x
x
x
x
x
x
x
x
x
x
x
x
WK
state
Configuration Registers
Configuration Select
0
10 11 12 13 14 15
x
MS2
0
9
x
1
0
8
x
MS1
1
7
1
0
1
6
Configuration Select
MS0
Mode Selection
Bits
WK
state
Configuration Registers
Configuration Select
1
x
0
MS0
Mode Selection
Bits
WD
refresh
Configuration Registers
x
MS2
DI
10 11 12 13 14 15
x
1
0
9
x
MS1
1
8
0
0
1
7
Configuration Select
MS0
Mode Selection
Bits
6
x
x
x
TIME
Figure 40
Data Sheet
Write Command
83
Rev. 1.0, 2009-03-31
TLE8264-2E
Serial Peripheral Interface
15.7
Electrical Characteristics
VS = 5.5 V to 28 V; Tj = -40 °C to +150 °C; SBC Normal Mode; all voltages with respect to ground; positive current
defined flowing into pin; unless otherwise specified.
Pos.
Parameter
Symbol
Limit Values
Min.
Typ.
Max.
–
0.7 x
Unit
Test Condition
V
–
V
–
V
–1)
SPI Interface; Logic Inputs SDI, CLK and CSN
15.7.1
15.7.2
H-input Voltage Threshold VIH
–
L-input Voltage Threshold VIL
0.3 x
VCC1µC
–
–
VCC1µC
Hysteresis of input
Voltage
VIHY
15.7.4
Pull-up Resistance at pin
CSN
RICSN
20
40
80
kΩ
VCSN = 0.7 × VCC1µC
15.7.5
Pull-down Resistance at
pin SDI and CLK
RICLK/SDI 20
40
80
kΩ
VSDI/CLK = 0.2 × VCC1µC
15.7.6
Input Capacitance
at pin CSN, SDI or CLK
CI
–
10
-
pF
-1)
VSDOH
VCC1µC - VCC1µC - –
V
IDOH = -1.6 mA
15.7.3
0.12 x
VCC1µC
Logic Output SDO
15.7.7
H-output Voltage Level
0.4
0.2
–
0.2
0.4
V
IDOL = 1.6 mA
-10
–
10
µA
VCSN = VCC1µC;
0 V < VDO < VCC1
CSDO
–
10
15
pF
1)
VSDOL
15.7.8
L-output Voltage Level
15.7.9
Tri-state Leakage Current ISDOLK
15.7.10
Tri-state Input
Capacitance
Data Input Timing1)
15.7.11
Clock Period
tpCLK
250
–
–
ns
–
15.7.12
Clock High Time
tCLKH
125
–
–
ns
–
15.7.13
Clock Low Time
tCLKL
125
–
–
ns
–
15.7.14
Clock Low before CSN
Low
tbef
125
–
–
ns
–
15.7.15
CSN Setup Time
tlead
250
–
–
ns
–
15.7.16
CLK Setup Time
tlag
250
–
–
ns
–
15.7.17
Clock Low after CSN High tbeh
125
–
–
ns
–
15.7.18
SDI Set-up Time
tDISU
100
–
–
ns
–
15.7.19
SDI Hold Time
tDIHO
50
–
–
ns
–
Data Sheet
84
Rev. 1.0, 2009-03-31
TLE8264-2E
Serial Peripheral Interface
15.7
Electrical Characteristics (cont’d)
VS = 5.5 V to 28 V; Tj = -40 °C to +150 °C; SBC Normal Mode; all voltages with respect to ground; positive current
defined flowing into pin; unless otherwise specified.
Pos.
Parameter
Symbol
Limit Values
Min.
Typ.
Max.
Unit
Test Condition
15.7.20
Input Signal Rise Time
at pin SDI, CLK and CSN
trIN
–
–
50
ns
–
15.7.21
Input Signal Fall Time
at pin SDI, CLK and CSN
tfIN
–
–
50
ns
–
15.7.22
Delay Time for Mode
Change from Normal
Mode to Sleep Mode
tfIN
–
–
10
µs
–
15.7.23
CSN High Time
tCSN(high) 10
–
–
µs
-
trSDO
tfSDO
tENSDO
tDISSDO
tVASDO
–
30
80
ns
CL = 100 pF
–
30
80
ns
CL = 100 pF
–
–
50
ns
low impedance
–
–
50
ns
high impedance
–
–
60
ns
CL = 100 pF
Data Output Timing 1)
15.7.24
SDO Rise Time
15.7.25
SDO Fall Time
15.7.26
SDO Enable Time
15.7.27
SDO Disable Time
15.7.28
SDO Valid Time
1) Not subject to production test; specified by design
23
CSN
14
15
12
16
13
17
CLK
18
DI
26
DO
Figure 41
19
LSB
not defined
MSB
27
28
Flag
LSB
MSB
SPI Timing Diagram
Note: Numbers in drawing correlate to the last 2 digits of the Pos. number in the Electrical Characteristics table.
Data Sheet
85
Rev. 1.0, 2009-03-31
TLE8264-2E
Application Information
16
Application Information
Note: The following information is given only as a hint for the implementation of the device and should not be
regarded as a description or warranty of a certain functionality, condition or quality of the device.
V DD
VBAT
VS
D1
T1
R1
IC2
V IO
V CC
VBAT
C1
C3
C2
C 12
GND
VCC IC3
VS
C13
D2
R2
Bus 1
BUS1
VS
V CC3shunt
VCC3base
GND
V CC3ref
VS
VDD
C4
V cc1µC
C9
VS
D3
R3
Bus 2
BUS2
TLE8264-2
C5
VS
D4
R4
BUS3
VBAT
C10
R 12
LOGIC
State
Machine
Bus 3
C6
CSN V DD
CLK
SDI
µC
SDO
TxD LIN 1
RxD LIN1
TxD LIN 2
RxD LIN2
TxD LIN 3
RxD LIN3
TxD CAN
RxD CAN
CSN
CLK
SDO
SDI
TxD LIN 1
RxD LIN 1
TxD LIN2
RxD LIN2
TxD LIN3
RxD LIN3
TxD CAN
RxD CAN
INT
INT
Reset VSS
RO
S1
VS
WK
V DD
V CC2
WK
R9
R5
C 14
CAN cell
V CCHSCAN
VDD VBB
C 11
CANH
CANH
R7
C8
VS
Limp Home
SPLIT
T2
R8
CANL
VBAT
R 10
C7
VS
CANL
LH_SI
LH_PL/Test
T3
DEVICE GROUND
CS
SCLK
SI
SO
LHI
IN0
IN1
IN2
IN3
IN4
IN5
IC1
GND
VS
GND
D5
S2
T4
Application _information
_TLE8264 -2E.vsd
Figure 42
Data Sheet
Application Example for a Body Controller Module
86
Rev. 1.0, 2009-03-31
TLE8264-2E
Application Information
Note: This is a very simplified example of an application circuit and bill of material. The function must be verified
in the actual application.
Table 25
Ref.
Bills of material
Option Vendor
Value
Purpose
68µF optional depending on
application
Cut off battery spike
100nF
EMC
10µF ceramic cap low ESR
Stability of the VCC3
Capacitance
C1
Y
C2
Y
C3
N
C4
N
1nF OEM dependent
LIN Master Termination
C5
N
1nF OEM dependent
LIN Master Termination
C6
N
1nF OEM dependent
LIN Master Termination
C7
Y
22nF 50V
EMC
C8
Y
47nF OEM dependent
Improve SPLIT pin stability
C9
Y
10µF
Buffer of the VCC1µC depending on load.
(µC)
C10
N
100nF
Stability of the VCC1µC
C11
N
10µF CAN transceiver dependent
Buffering of the VCC2 for CAN Transceiver
C12
Y
100nF
Improve stability of the logic
C13
Y
100nF
Improve stability of the logic
C14
Y
100nF
Improve stability of the logic
220mΩ
VCC3 current measurement for ICC3
Kemet
Murata
Resistance
R1
N
400mA max
R2
Y
1kΩ / OEM dependent
LIN master termination
R3
Y
1kΩ / OEM dependent
LIN master termination
R4
Y
1kΩ / OEM dependent
LIN master termination
R5
Y
1kΩ
Wetting current of the switch
R7
Y
60Ω / OEM dependent
CAN bus termination
R8
Y
60Ω / OEM dependent
CAN bus termination
R9
Y
10kΩ
Limit the WK pin current in ISO pulses
R10
Y
500Ω
Insulation of the VDD supply
R12
Y
47kΩ
Set config 1/3. If not connected config 2/4
is selected
Data Sheet
87
Rev. 1.0, 2009-03-31
TLE8264-2E
Application Information
Table 25
Ref.
Bills of material
Option Vendor
Value
Purpose
ON Semi
MJD253
Power element of VCC3
Infineon
BCP52-16
Alternative power element of VCC3, current
limit to be adapted R1 to be changed.
Active components
T1
N
T2
N
Infineon
BCR191W
High active Limp Home
T3
N
Infineon
BCR191W
High active Limp Home
T4
N
Infineon
BCR191W
High active Limp Home
D1
N
Infineon
BAS 3010A
Reverse polarity protection
D2
N
Infineon
BAS70 06 (dual)
BAS70 (single)
Requested by LIN norm.
Protect the application in reverse polarity.
D3
N
BAS70 06 (dual)
BAS70 (single)
Requested by LIN norm.
Protect the application in reverse polarity.
D4
N
Infineon
BAS70 06 (dual)
BAS70 (single)
Requested by LIN norm.
Protect the application in reverse polarity.
µC
N
Infineon
XC2xxx
micro-controller
IC1
Y
Infineon
SPOC - BTS5672E
high side switches
IC2
Y
Infineon
TLE 6254-3G
Low speed CAN
IC3
Y
Infineon
TLE 6251DS
High speed CAN
Data Sheet
Infineon
88
Rev. 1.0, 2009-03-31
TLE8264-2E
Application Information
16.1
ZthJA Curve
60
Zth-JA(Ch4; 600)
50
Zth-JA(Ch4; 300)
Zth-JA(Ch4; 100)
Zth-JA [K/W]
40
Zth-JA(Ch4; footprint)
30
20
10
0
0,00001
0,0001
0,001
0,01
0,1
1
10
100
1000
10000
tim e (s)
Zthja curves.vsd
Figure 43
ZthJA Curve, Function of Cooling Area
600mm² cooling area
300mm² cooling area
100mm² cooling area
minimum footprint
PCB set up.vsd
Figure 44
Board Set-up
Board set-up is done according to JESD 51-3, single layer FR4 PCB 70 µm.
Data Sheet
89
Rev. 1.0, 2009-03-31
TLE8264-2E
Application Information
16.2
Hints for SBC Factory Flash Mode
The mode is used during production of the module to flash the µC. The idea is that the µC is not supplied from the
SBC but from an external 5V power supply. The reset of the µC that is connected to the RO pin of the SBC can
be driven from an external source and the SBC does not give a reset signal. Also no interrupt at the pin INT and
no signal on the SPI SDO pin is generated by the SBC. The SPI pins can be driven externally.
The mode is reached by applying 5V to the VCC1µC pin and no voltage to the Vs pin. The Vs pin will show a voltage
of about 4.5V because of the internal diode from VCC1µC to Vs. The current drawn at Vs must not exceed the
maximum rating of Ivs,max = -500mA. The function is designed for ambient temperature.
In case the Vs was supplied before going to FF Mode, the voltage on pin Vs must be set below 3 V before applying
5V to VCC1µC (discharging the C)
Not
supplied
Not
supplied
5V
Vs
VBAT
C
Reset
signal
VCC1µC
IVS
Internal
supply
The current
flowing to other
devices from
Vs should be
limited to not
exceed the
maximum
ratings.
Other
Devices
CSN
CLK
SDO
SDI
TxD LIN1
RxD LIN1
TxD LIN2
RxD LIN2
TxD LIN3
RxD LIN3
TxD CAN
RxD CAN
CSN V DD
CLK
SDI
µC
SDO
TxD LIN1
RxD LIN1
TxD LIN2
RxD LIN2
TxD LIN3
RxD LIN3
TxD CAN
RxD CAN
INT
INT
RO
Reset V SS
Application_ FF_Mode _2.vsd
Figure 45
Data Sheet
Application Hint for Factor Flash Mode
90
Rev. 1.0, 2009-03-31
TLE8264-2E
Application Information
Table 26
PIN in Factory Flash Mode
Pin
Level
Comment
Vs
typ. 4.5V
Voltage output from SBC. No voltage applied from
external.
Vcc1µC
5V ± 2%
To be applied from external
RO
Pull-up resistor
Can be driven from external
INT
Pull-up resistor
Can be driven from external if required
LH
High impedance
Can be driven from external if required
SDO
High impedance
Can be driven from external if required
CLK, SDI
Pull-down resistor
Can be driven from external if required
CSN
Pull-up resistor
Can be driven from external if required
TxDCAN, TxDLIN1,
TxDLIN2, TxDLIN3
Pull-up resistor
Can be driven from external if required
RxDCAN, RxDLIN1,
RxDLIN2, RxDLIN3
High impedance
Can be driven from external if required
16.3
ESD Tests
Tests for ESD robustness according to IEC61000-4-2 “gun test” (150pF, 330Ω) have been performed. The results
and test condition is available in a test report. The values for the test are listed in Table 27 below.
Table 27
ESD “Gun test”
Performed Test
Result
Unit
Remarks
ESD at pin CANH, CANL,
BUSx, Vs versus GND
>8
kV
positive pulse1)
ESD at pin CANH, CANL,
BUSx, Vs versus GND
< -8
kV
negative pulse
1) ESD susceptibility “ESD GUN” contact discharge (R=330Ohm C=150pF) (DIN EN 61000-4-2) tested according LIN EMC
1.3 Test Specification and ICT EMC Evaluation of CAN Transceiver. Tested by external test house (IBEE Zwickau, EMC
Test report Nr. 06-02-09a)
Data Sheet
91
Rev. 1.0, 2009-03-31
TLE8264-2E
Package Outline
Package Outline
8˚ MAX.
1.1
7.6 -0.2 1)
0.65
0.7 ±0.2
C
17 x 0.65 = 11.05
0.33 ±0.08 2)
0.23 +0.09
0.35 x 45˚
2.55 MAX.
3)
0...0.10
STAND OFF
2.45 -0.2
17
0.1 C 36x
SEATING PLANE
10.3 ±0.3
0.17 M A-B C D 36x
D
Bottom View
A
19
19
Ejector Mark
Cavity ID
36
Exposed Diepad
Y
36
18
1
18
B
X
1
Index Marking
12.8 -0.21)
Index Marking
Ejector Mark
Polish Finish
Exposed Diepad Dimensions 4)
Leadframe
X
Y
Package
PG-DSO-36-24, -41, -42 A6901-C001 7 5.1
A6901-C003 7 5.1
PG-DSO-36-38
A6901-C007 5.2 4.6
PG-DSO-36-38
PG-DSO-36-24
A6901-C008 6.0 5.4
1) Does not include plastic or metal protrusion of 0.15 max. per side
2) Does not include dambar protrusion of 0.05 max. per side
3) Distance from leads bottom (= seating plane) to exposed diepad
4) Exclunding the mold flash allowance of 0.3mm MAX per side
PG-DSO-36-24, -38, -41, -42-PO V08
Figure 46
PG-DSO-36-38 (Leadframe A6901-003);)
Note: For the SBC product family the package PG-DSO-36-38 with the leadframe A6901-C003 is used.
Green Product (RoHS compliant)
To meet the world-wide customer requirements for environmentally friendly products and to be compliant with
government regulations, the Universal System Basis Chip is available as a green product. Green products are
RoHS-Compliant (i.e Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD020).
For information about packages and types of packing, refer to the
Infineon Internet Page “Products”: http://www.infineon.com/products.
Data Sheet
92
Dimensions in mm
Rev. 1.0, 2009-03-31
TLE8264-2E
Revision History
18
Revision History
Version
Date
1.0
2009-01-30
First Rev. after Preliminary Data Sheet
1.0
2009-03-31
Editorial changes
Data Sheet
Parameter
Changes
93
Rev. 1.0, 2009-03-31
Edition 2009-03-31
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2009 Infineon Technologies AG
All Rights Reserved.
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties
and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights
of any third party.
Information
For further information on technology, delivery terms and conditions and prices, please contact the nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements, components may contain dangerous substances. For information on the types in
question, please contact the nearest Infineon Technologies Office.
Infineon Technologies components may be used in life-support devices or systems only with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
工商网监
湘ICP备2023018690号
