TLE95633QXXUMA1

TLE9563-3QX BLDC Motor System IC 1 Overview Features • Low-drop voltage regulator 5 V, 250 mA for main supply • Three half-bridge gate drivers for external N-channel MOSFETs • Adaptive MOSFET gate control: – Regulation of the MOSFET switching time – Reduced switching losses in PWM mode – High efficient constant gate charge • Control of reverse battery protection MOSFET • One low-side capable current sense amplifier (CSA) with configurable gain for protection and diagnosis • High-speed CAN transceiver supporting CAN FD communication up to 5 Mbit/s according to ISO118982:2016 including selective wake-up functionality via CAN partial networking and CAN FD tolerant mode • Configurable wake-up sources • Three high-side outputs 7 Ω typ. • Six PWM inputs – High-side and low-side PWM capable – Active free-wheeling – Up to 25 kHz PWM frequency • 32 bit serial peripheral interface (SPI) with cyclic redundancy check (CRC) • Very low quiescent current consumption in Stop Mode and Sleep Mode • Periodic cyclic sense and cyclic wake in Normal Mode, Stop Mode and Sleep Mode • Reset and interrupt output • Drain-source monitoring and open-load detection • Configurable time-out and window watchdog • Overtemperature and short circuit protection features • Leadless power package with support of optical lead tip inspection • Green Product (RoHS compliant) Datasheet www.infineon.com 1 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Overview Potential applications • Auxiliary pumps (fuel, water, etc.) • Blower motor • Engine cooling fan • Sunroof module • Transfer case Product validation Qualified for automotive applications. Product validation according to AEC-Q100. Description The TLE9563-3QX is a multifunctional system IC with integrated power supply, communication interfaces, multiple half-bridges and support features in an exposed pad PG-VQFN-48 power package. The device is designed for various motor control automotive applications. To support these applications, the BLDC Motor System IC provides the main functions, such as a 5 V lowdropout voltage regulator one HS-CAN transceiver supporting CAN FD, CAN Partial Networking (incl. FD tolerant mode), three half-bridges for BDLC motor control, one current sense amplifier and one 32 bit serial peripheral interface (SPI). The device includes diagnostic and supervision features, such as drain-source monitoring and open-load detection, short circuit protection, configurable time-out and window watchdog, as well as overtemperature protection. Type Package Marking TLE9563-3QX PG-VQFN-48 TLE9563-3QX Datasheet 2 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Table of Contents 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 3.1 3.2 3.3 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Hints for not functional pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4 4.1 4.2 4.3 4.4 General Product Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 12 14 15 15 5 5.1 5.2 5.3 5.4 5.4.1 5.4.2 5.4.3 5.4.4 5.4.5 5.4.6 5.4.7 5.5 5.5.1 5.5.2 5.5.3 5.5.4 5.5.5 5.5.6 5.5.7 5.5.8 5.6 5.6.1 5.6.2 5.6.3 5.7 5.7.1 5.7.1.1 5.7.1.2 5.7.2 5.7.3 5.8 5.9 5.9.1 System Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Short State Machine Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Device Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Description of State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . State Machine Modes Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Init Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Restart Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fail-Safe Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Software Development Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transition Between States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transition into Init Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Init Mode -> Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Normal Mode -> Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Normal Mode -> Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stop Mode -> Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sleep Mode -> Restart Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Restart Mode -> Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fail-Safe Mode -> Restart Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reaction on Detected Faults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stay in Current State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transition into Restart Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transition into Fail-Safe Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wake Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Cyclic Sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration and Operation of Cyclic Sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Cyclic Sense in Low-power Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Cyclic Wake . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VS Supply Multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Partial Networking on CAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CAN Partial Networking - Selective Wake Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 20 21 23 24 24 24 25 26 27 28 29 29 30 30 30 31 31 32 32 32 33 33 33 35 35 36 36 40 40 41 42 43 43 Datasheet 3 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC 5.9.2 5.9.2.1 5.9.2.2 5.9.2.3 5.9.2.4 5.9.3 5.9.3.1 5.9.3.2 5.9.3.3 5.9.3.4 5.9.3.5 5.9.3.6 5.9.3.7 5.9.3.8 5.9.3.9 5.9.3.10 5.9.3.11 5.9.4 5.9.4.1 5.9.4.2 5.9.4.3 5.9.4.4 5.9.4.5 5.9.5 5.9.6 5.9.7 5.9.8 5.9.8.1 5.9.8.2 5.9.9 Partial Networking Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Activation of SWK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wake-up Pattern (WUP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wake-up Frame (WUF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CAN Protocol Error Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Diagnoses Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PWRON/RESET-FLAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BUSERR-Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TXD Dominant Time-out flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . WUP Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . WUF Flag (WUF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SYSERR Flag (SYSERR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CAN Bus Timeout-Flag (CANTO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CAN Bus Silence-Flag (CANSIL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SYNC-FLAG (SYNC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SWK_SET FLAG (SWK_SET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Modes for Selective Wake (SWK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Normal Mode with SWK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stop Mode with SWK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sleep Mode with SWK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Restart Mode with SWK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fail-Safe Mode with SWK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wake-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration for SWK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CAN Flexible Data Rate (CAN FD) Tolerant Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock and Data Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuring the Clock Data Recovery for SWK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Setup of Clock and Data Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 45 46 46 47 48 48 48 48 48 48 48 49 49 49 49 49 50 50 51 52 53 54 54 54 55 57 57 58 59 6 6.1 6.2 6.3 Voltage Regulator 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 61 62 63 7 7.1 7.2 7.2.1 7.2.2 7.2.3 7.2.4 7.2.5 7.3 High-Side Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Under Voltage Switch Off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Over Voltage Switch Off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Over Current Detection and Switch Off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Open Load Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PWM, Timer and SYNC Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 65 65 65 66 66 66 66 68 8 8.1 8.2 High Speed CAN Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Datasheet 4 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC 8.2.1 8.2.2 8.2.3 8.2.4 8.2.5 8.2.6 8.2.7 8.2.8 8.3 CAN OFF Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CAN Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CAN Receive Only Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CAN Wake Capable Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CAN Bus termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TXD Time-out Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bus Dominant Clamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Undervoltage Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 71 71 72 73 73 73 74 74 9 9.1 9.2 9.2.1 9.2.2 9.2.3 9.2.4 9.3 High-Voltage Wake Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . High-Voltage Wake Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wake Input Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wake configuration for Cyclic Sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wake configuration for Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 81 82 82 82 83 83 84 10 10.1 10.2 Interrupt Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Block and Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 11 11.1 11.2 11.2.1 11.2.2 11.2.3 11.3 11.3.1 11.3.2 11.3.3 11.3.3.1 11.3.3.2 11.3.3.3 11.3.3.4 11.3.3.5 11.3.4 11.3.5 11.3.6 11.4 11.5 11.6 11.7 11.8 11.9 Gate Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 MOSFET control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Static activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Static activation of a high-side MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Static activation of a low-side MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Turn-off of the high-side and low-side MOSFETs of a half-bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 PWM operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Determination of the active and freewheeling MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Configurations in PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 PWM operation with 3 PWM inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Control signals with active free-wheeling (AFWx = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Control signals with passive free-wheeling (AFWx = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Time modulation of pre-charge and pre-discharge times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Operation at high and low duty cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Measurements of the switching times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 PWM operation with 6 PWM inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Status bits for regulation of turn-on and turn-off delay times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Gate driver current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Passive discharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Slam mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Parking braking mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Frequency modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Electrical characteristics gate driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 12 12.1 Supervision Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Reset Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Datasheet 5 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC 12.1.1 Reset Output Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.1.2 Soft Reset Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.2 Watchdog Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.2.1 Time-Out Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.2.2 Window Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.2.3 Watchdog Setting Check Sum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.2.4 Watchdog during Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.2.5 Watchdog Start in Stop Mode due to Bus Wake . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.3 VSINT Power On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.4 VSINT Under- and Overvoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.4.1 VSINT Undervoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.4.2 VSINT Overvoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.5 VS Under- and Overvoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.5.1 VS Undervoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.5.2 VS Overvoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.6 VS Under- Overvoltage for high-side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.6.1 VS Undervoltage for high-side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.6.2 VS Overvoltage for high-side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.7 VCC1 Over-/ Undervoltage and Undervoltage Prewarning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.7.1 VCC1 Undervoltage and Undervoltage Prewarning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.7.2 VCC1 Overvoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.8 VCC1 Short Circuit Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.9 VCAN Undervoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.10 Thermal Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.10.1 Individual Thermal Shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.10.2 Temperature Prewarning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.10.3 Thermal Shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.11 Bridge driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.11.1 Bridge driver supervision with activated charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.11.1.1 Drain-source voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.11.1.2 Cross-current protection and drain-source overvoltage blank time . . . . . . . . . . . . . . . . . . . . . . 12.11.1.3 OFF-state diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.11.1.4 Charge pump undervoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.11.1.5 Switching parameters of MOSFETs in PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.11.2 Low-side drain-source voltage monitoring during braking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.11.3 VS or VSINT Overvoltage braking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.12 Current sense amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.12.1 Unidirectional and bidirectional operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.12.2 Gain configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.12.3 Overcurrent Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.12.4 CSO output capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.13 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 137 138 139 140 140 141 141 142 143 143 143 144 144 144 145 145 145 146 146 147 147 147 148 148 148 148 150 150 150 151 152 153 153 153 154 154 154 155 155 157 158 13 13.1 13.2 13.3 13.3.1 166 166 167 169 170 Datasheet Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Failure Signalization in the SPI Data Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC 13.4 13.4.1 13.5 13.5.1 13.5.2 13.5.3 13.5.4 13.6 13.6.1 13.6.2 13.6.3 13.6.4 13.7 SPI Bit Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Banking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Device Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Control registers bridge driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Selective Wake Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Selective Wake trim and configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI status information registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Device Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Status registers bridge driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Selective wake status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Family and product information register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 173 175 177 197 218 232 237 239 250 262 265 266 14 14.1 14.2 14.2.1 14.2.2 14.3 14.4 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Application Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ESD Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ESD according to IEC61000-4-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ESD according to SAE J2962 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Thermal Behavior of Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Further Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 268 271 271 271 272 272 15 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 16 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 Datasheet 7 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Block Diagram 2 Block Diagram VSINT VCC1 VCC1 VS CP VS MUX(VSINT,VS) CP VCC1 Charge pump SDI Control Logic CPC1N SDO CPC1P SPI CLK CPC2N CSN CPC2P state machine CP VCC1 VS GH1 Reset watchdog SH1 GH2 Interrupt SH2 Interrupt Generation GH3 RSTN INTN/TEST VS SH3 Gate Drivers Reset Generation HSS output HS1 HSS output HS2 HSS output HS3 GL1 GL2 CSA logic GL3 MUX(VSINT,VS) VSINT SL Wake Logic PWM1/CRC PWM2 Wake-up input WK4/SYNC Wake-up input WK5 Fail Safe PWM3 PWM inputs PWM4 PWM5 PWM6 CP/VCC1 CSAP CSA CSO CSAN VCAN CANL GND TXDCAN HS CAN FD transceiver CANH RXDCAN (Transceiver GND, Pin 16) (Analog/dig. GND, Pin 6) MUX(VSINT,VS): multiplexed VSINT & VS Figure 1 Datasheet GND Block Diagram 8 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Pin Configuration Pin Configuration 3.1 Pin Assignment 36 SH3 35 GH3 34 PWM3 33 CP 32 VS 31 CPC1N 30 CPC1P 29 CPC2P 28 CPC2N 27 PWM1/CRC 26 GH1 25 SH1 3 N.U. 37 N.U. 38 PWM4 39 GL3 40 N.U. 41 WK4/SYNC 42 HS1 43 HS2 44 HS3 45 PWM5 46 PWM6 47 VSINT 48 TLE9563 PG-VQFN-48 24 SH2 23 GH2 22 PWM2 21 GL1 20 GL2 19 SL 18 CSN 17 WK5 16 GND 15 CANL 14 CANH 13 VCAN 12 RXDCAN 11 TXDCAN 10 CLK 9 CSO 8 CSAN 7 CSAP 6 GND 5 SDI 4 SDO 3 INTN/TEST 2 RSTN 1 VCC1 Figure 2 Pin Configuration 3.2 Pin Definitions and Functions Pin Symbol Function 1 VCC1 Voltage Regulator. Output voltage 1 2 RSTN Reset Output. Active LOW, internally passive pull-up with open-drain output 3 INTN/TEST Interrupt Output. Active LOW output, push-pull structure TEST. Connect to GND (via pull-down) to activate Software Development Mode 4 SDO SPI Data Output to Microcontroller (=MISO). Push-pull structure 5 SDI SPI Data Input from Microcontroller (=MOSI). Internal pull-down 6 GND Ground. Analog/digital ground 7 CSAP Not Inverting input of Current Sense Amplifier. Datasheet 9 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Pin Configuration Pin Symbol Function 8 CSAN Inverting input of Current Sense Amplifier. 9 CSO Current Sense Amplifier Output. 10 CLK SPI Clock Input. Internal passive pull-down 11 TXDCAN Transmit CAN. Internal passive pull-up 12 RXDCAN Receive CAN. Push-pull structure 13 VCAN HS-CAN Supply Input. For internal HS-CAN cell needed for CAN Normal Mode 14 CANH CAN High Bus. 15 CANL CAN Low Bus. 16 GND Ground. Transceiver ground (CAN) 17 WK5 Wake-up input 5. 18 CSN SPI Chip Select Not input. Internal passive pull-up 19 SL Source Low Side. 20 GL2 Gate Low Side 2. 21 GL1 Gate Low Side 1. 22 PWM2 PWM input 2. Internal passive pull-up 23 GH2 Gate High Side 2. 24 SH2 Source High Side 2. 25 SH1 Source High Side 1. 26 GH1 Gate High Side 1. 27 PWM1/CRC PWM input 1. Internal passive pull-down CRC. Connect to GND (via pull-down) to activate CRC functionality 28 CPC2N Negative connection to Charge Pump Capacitor 2. 29 CPC2P Positive connection to Charge Pump Capacitor 2. 30 CPC1P Positive connection to Charge Pump Capacitor 1. 31 CPC1N Negative connection to Charge Pump Capacitor 1. 32 VS Supply voltage for HSx, Bridge Drivers and Charge pump. Connected to the battery voltage after reverse protection. 33 CP Charge Pump output voltage. 34 PWM3 PWM input 3. Internal passive pull-down 35 GH3 Gate High Side 3. 36 SH3 Source High Side 3. 37 N.U. Not used. 38 N.U. Not used. 39 PWM4 PWM input 4. Internal passive pull-down 40 GL3 Gate Low Side 3. 41 N.U. Not used. 42 WK4/SYNC Wake-up input 4/Sync. 43 HS1 High Side output 1. 44 HS2 High Side output 2. Datasheet 10 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Pin Configuration Pin Symbol Function 45 HS3 High Side output 3. 46 PWM5 PWM input 5. Internal passive pull-down 47 PWM6 PWM input 6. Internal passive pull-down 48 VSINT Voltage regulator and main supply voltage. Connected to the battery voltage after reverse protection Cooling GND Tab Cooling Tab - Exposed Die Pad; For cooling purposes only, do not use as an electrical ground1) 1) The exposed die pad at the bottom of the package allows better power dissipation of heat from the device via the PCB. The exposed die pad is not connected to any active part of the IC. However, it should be connected to GND for the best EMC performance. Note: The GND pin as well as the Cooling Tab must be connected to one common GND potential. 3.3 Hints for not functional pins It must be ensured that the correct configurations are also selected, i.e. in case functions are not used that they are disabled via SPI. Unused pins should be handled as follows: • N.U.: not used; internally bonded for testing purpose; leave open. • RSVD: must be connected to GND. Datasheet 11 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC General Product Characteristics 4 General Product Characteristics 4.1 Absolute Maximum Ratings Table 1 Absolute Maximum Ratings1) Tj = -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Min. Typ. Max. Unit Note or Test Condition Number Voltages Supply Voltage VS VS, max -0.3 – 28 V – P_4.1.1 Supply Voltage VS VS, max -0.3 – 40 V Load Dump P_4.1.2 Supply Voltage VSINT VSINT, max -0.3 – 28 V – P_4.1.3 Supply Voltage VSINT VSINT, max -0.3 – 40 V Load Dump P_4.1.4 Voltage Regulator 1 VCC1, max -0.3 – 5.5 V P_4.1.7 Charge Pump Output Pin (CP) VCP, max VS - 0.8 – VS + 17 V ICP > - 200 µA if CP P_4.1.8 is disabled CPC1P, CPC2P VCPCxP, max - 0.3 – VS + 17 V P_4.1.38 CPC1N, CPC2N VCPCxN, max - 0.3 – VS + 0.3 V P_4.1.39 Bridge Driver Gate High Side VGHx, max (GHx) -8.0 – 40 V – P_4.1.11 Bridge Driver Gate Low Side VGLx, max (GLx) -8.0 – 24 V – P_4.1.12 Voltage difference between VGS GHx-SHx and between GLxSLx -0.3 – 16 V – P_4.1.13 Bridge Driver Source High (SHx) VSHx, max -8.0 – 40 V – P_4.1.14 Bridge Driver Source Low Side SL VSL, max -8.0 – 6.0 V – P_4.1.15 Current Sense Amplifier inputs (CSAP, CSAN) VCSx, max -8.0 – +8.0 V – P_4.1.16 Current Sense Amplifier Output CSO VCSx, max -0.3 – VCC1 + 0.3 V – P_4.1.17 Differential input voltage range CSAPx - CSANx VCSA,Diff -8.0 – 8.0 V – P_4.1.18 Wake Input WKx VWKx, max -0.3 – 40 V – P_4.1.19 High Side HSx VHSx, max -0.3 – VS, max + 0.3 V – P_4.1.20 CANH, CANL VBUS, max -27 – 40 V – P_4.1.22 Datasheet 12 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC General Product Characteristics Table 1 Absolute Maximum Ratings1) (cont’d) Tj = -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Min. PWM1/CRC, PWM2, PWM3, PWM4, PWM 5, PWM6 Input Pins VPWM1-2-3-4-5- -0.3 Unit Note or Test Condition Number Typ. Max. – 40 V – P_4.1.25 6, max Logic Input Pins (SDI, CLK, TXDCAN, TXDLIN) VI, max -0.3 – VCC1 + 0.3 V – P_4.1.28 CSN VCSN -0.3 – 40 V – P_4.1.29 Logic Output Pins (SDO, RSTN, INTN, RXDCAN) VO, max -0.3 – VCC1 + 0.3 V – P_4.1.30 VCAN Input Voltage VVCAN, max -0.3 – 5.5 V Junction Temperature Tj -40 – 150 °C – P_4.1.32 Storage Temperature Tstg -55 – 150 °C – P_4.1.33 VESD,11 -2 – 2 kV HBM2) P_4.1.31 Temperatures ESD Susceptibility ESD Resistivity 2)3) P_4.1.34 ESD Resistivity to GND, CANH, CANL VESD,12 -8 – 8 kV HBM P_4.1.35 ESD Resistivity to GND VESD,21 -500 – 500 V CDM4) P_4.1.36 V 4) P_4.1.37 ESD Resistivity Pin 1, VESD,22 12,13,24,25,36,37,48 (corner pins) to GND -750 – 750 CDM 1) Not subject to production test, specified by design. 2) ESD susceptibility, HBM according to ANSI/ESDA/JEDEC JS-001 (1.5 kΩ, 100 pF). 3) For ESD “GUN” Resistivity (according to IEC61000-4-2 “gun test” (150 pF, 330 Ω)), is shown in Application Information and test report will be provided from IBEE. 4) ESD susceptibility, Charged Device Model “CDM” EIA/JESD22-C101 or ESDA STM5.3.1. Notes 1. Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. Integrated protection functions are designed to prevent IC destruction under fault conditions described in the data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are not designed for continuous repetitive operation. Datasheet 13 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC General Product Characteristics 4.2 Functional Range Table 2 Functional Range1) Parameter Symbol Values Min. Typ. Max. Unit Note or Test Condition Number Supply Voltage VSINT,func VPOR,f – 28 V 2) P_4.2.1 Bridge Supply Voltage VS,func 6.0 – 28 V – P_4.2.2 CAN Supply Voltage VCAN,func 4.75 – 5.25 V – P_4.2.4 Junction Temperature Tj -40 – 150 °C – P_4.2.6 1) Not subject to production test, specified by design. 2) Including Power-On Reset, Over- and Undervoltage Protection. Note: Within the functional range the IC operates as described in the circuit description. The electrical characteristics are specified within the conditions given in the related electrical characteristics table. Device Behavior Outside of Specified Functional Range • 28 V < VSINT,func < 40 V: Device will still be functional including the state machine; the specified electrical characteristics might not be ensured anymore. The VCC1 is working properly, however, a thermal shutdown might occur due to high power dissipation. HSx switches might be turned OFF depending on HSx_OV configurations. The specified SPI communication speed is ensured; the absolute maximum ratings are not violated, however the device is not intended for continuous operation of VSINT > 28 V and a thermal shutdown might occur due to high power dissipation. The device operation at high junction temperatures for long periods might reduce the operating life time. Note: VCAN < 4.75 V: The undervoltage bit will be set in the SPI register and the transmitter will be disabled as long as the UV condition is present. Note: 5.25 V < VCAN < 5.5 V: CAN transceiver still functional. However, the communication might fail due to out-of-spec operation. • VPOR,f < VSINT < 5.5 V (given the fact that the device was powered up correctly before with VSINT > 5.5 V): Device will still be functional; the specified electrical characteristics might not be ensured anymore: – The voltage regulator will enter the low-drop operation mode. – A reset could be triggered depending on the Vrthx settings. – HSx switch behavior will depend on the respective configuration: HS_UV_SD_DIS = ‘0’ (default): HSx will be turned OFF for VS < VS,UVD and will stay OFF. HS_UV_SD_DIS = ‘1’: HSx stays on as long as possible. An unwanted overcurrent shut down may occur. OC shut down bit set and the respective HSx switch will stay OFF. – The specified SPI communication speed is ensured. Note: Datasheet VS,UV < VS < 6.0 V: the charge pump might be deactivated due to a charge pump undervoltage detection, resulting in a turn-off of the external MOSFETs. 14 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC General Product Characteristics 4.3 Thermal Resistance Table 3 Thermal Resistance1) Parameter Symbol Junction to Soldering Point Rth(JSP) Junction to Ambient Rth(JA) Values Unit Min. Typ. Max. – 7.2 – – 27 – Note or Test Condition Number K/W Exposed Pad P_4.3.1 K/W 2) P_4.3.2 1) Not subject to production test, specified by design. 2) Specified Rth(JA) value is according to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board for a power dissipation of 1.5 W; the product (chip+package) was simulated on a 76.2 x 114.3 x 1.5 mm3 with 2 inner copper layers (2 x 70 µm Cu, 2 x 35 µm C); where applicable a thermal via array under the exposed pad contacted the first inner copper layer and 300 mm2 cooling areas on the top layer and bottom layers (70 µm). 4.4 Current Consumption Table 4 Current Consumption Current consumption values are specified at Tj = 25°C, VSINT= VS = 13.5 V, all outputs open (unless otherwise specified) Parameter Symbol Values Min. Typ. Max. Unit Note or Test Condition Number INormal – 4.5 5.5 mA 1) VSINT = 5.5 V to 28 V; Tj = -40°C to +150°C; CAN=CP=off P_4.4.1 Stop Mode current consumption (low active peak threshold) IStop_1,25 – 50 65 µA 1)2) CSA=CAN3)=off; WKx=HSx=CP=off: Cyclic Wak./Sen.=off Watchdog = off; no load on VCC1; I_PEAK_TH = 0B P_4.4.2 Stop Mode current consumption (low active peak threshold) IStop_1,85 – 55 80 µA 1)2)4) Tj = 85°C; CSA=CAN3)=off; WKx=HSx=CP=off: Cyclic Wak./Sen.=off Watchdog = off; no load on VCC1; I_PEAK_TH = 0B P_4.4.3 Stop Mode current IStop_2,25 consumption (high active peak threshold) – 70 95 µA 1)2) P_4.4.4 Normal Mode Normal Mode current consumption Stop Mode Datasheet 15 CSA=CAN3)=off; WKx=HSx=CP=off: Cyclic Wak./Sen.=off Watchdog = off; no load on VCC1; I_PEAK_TH = 1B Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC General Product Characteristics Table 4 Current Consumption (cont’d) Current consumption values are specified at Tj = 25°C, VSINT= VS = 13.5 V, all outputs open (unless otherwise specified) Parameter Symbol IStop_2,85 Stop Mode current consumption (high active peak threshold) Values Min. Typ. Max. Unit Note or Test Condition Number – 75 105 µA 1)2)4) Tj = 85°C; CSA=CAN3)=off; Cyclic Wak./Sen.=off; Watchdog = off; no load on VCC1; I_PEAK_TH = 1B P_4.4.5 Sleep Mode Sleep Mode current consumption ISleep,25 – 18 30 µA 1) CSA=CAN3)=off; WKx=HSx=CP=off: Cyclic Wak./Sen.= off P_4.4.6 Sleep Mode current consumption ISleep,85 – 28 40 µA 1)4) Tj = 85°C; CSA=CAN3)=off; WKx=HSx=CP=off: Cyclic Wak./Sen.=off P_4.4.7 1)4) Feature Incremental Current Consumption Current consumption for ICAN,rec CAN module, recessive state – 2 3.5 mA P_4.4.13 Normal/Stop Mode; CAN Normal Mode; Tj = -40°C to +150°C; VCC1 connected to VCAN; VTXDCAN = VCC1; no RL on CAN Current consumption for CAN module, dominant state ICAN,dom – 3 5.0 mA 1)4) P_4.4.14 Normal/Stop Mode; CAN Normal Mode; Tj = -40°C to +150°C; VCC1 connected to VCAN; VTXDCAN = GND; no RL on CAN Current consumption for CAN module, Receive Only Mode, Normal Mode ICAN,Rec_onlyN – 0.5 0.7 mA 1)4)5) Datasheet 16 P_4.4.15 Normal Mode; CAN Receive Only Mode; Tj = -40°C to +150°C; VCC1 connected to VCAN; VTXDCAN = VCC1; no RL on CAN Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC General Product Characteristics Table 4 Current Consumption (cont’d) Current consumption values are specified at Tj = 25°C, VSINT= VS = 13.5 V, all outputs open (unless otherwise specified) Parameter Symbol Values Min. Typ. Max. Unit Note or Test Condition Number 1)4)5) Current consumption for CAN module, Receive Only Mode, Stop Mode ICAN,Rec_only – 1.4 1.5 mA P_4.4.16 Stop Mode; CAN Receive Only Mode; Tj = -40°C to +150°C; VCC1 connected to VCAN; VTXDCAN = VCC1; no RL on CAN Current consumption for CAN wake capability (tsilence expired) ICAN,wake,25 – 4.5 7 µA 1)3)6) Sleep Mode; CAN wake capable; Current consumption for CAN wake capability (tsilence expired) ICAN,wake,85 – 8 10 µA 1)3)4)6) Current consumption during ICAN,SWK,25 CAN Partial Networking frame detect mode ( RX_WK_SEL= ‘0’) – 475 550 µA 1)4) Tj = 25°C; Stop Mode; WK, CAN SWK wake capable, SWK Receiver enabled, WUF detect; no RL on CAN; P_4.4.19 Current consumption during ICAN,SWK,85 CAN Partial Networking frame detect mode ( RX_WK_SEL= ‘0’) – 500 575 µA 1)4) Tj = 85°C; Stop Mode; WK, CAN SWK wake capable, SWK Receiver enabled, WUF detect; no RL on CAN; P_4.4.20 Current consumption for each WK input IWK,wake,25 – 0.2 2 µA 1)6)7)8) Current consumption for each WK input IWK,wake,85 – 0.5 3 µA 1)4)6)7)8) Sleep Mode; Tj P_4.4.23 = 85°C; WK wake capable; no activity on WK pin; Current consumption for IStop,HS,25 first High-Side in Stop Mode – 250 375 µA 4)6)9)11)10) Datasheet 17 P_4.4.17 Sleep Mode; Tj = P_4.4.18 85°C; CAN wake capable; WK = off; Sleep Mode; WK P_4.4.22 wake capable; no activity on WK pin; Stop Mode; HS with 100% duty cycle (no load); P_4.4.24 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC General Product Characteristics Table 4 Current Consumption (cont’d) Current consumption values are specified at Tj = 25°C, VSINT= VS = 13.5 V, all outputs open (unless otherwise specified) Parameter Symbol Min. Typ. Max. Unit Note or Test Condition Current consumption for IStop,HS,85 first High-Side in Stop Mode – 250 375 µA Current consumption for cyclic sense function – IStop,CS25 Values 4)6)9)11)10) Number Stop Mode; Tj P_4.4.25 = 85°C; HS with 100% duty cycle (no load); 20 26 µA 6)9)11)12) Stop Mode; WD P_4.4.26 = off; Current consumption for cyclic sense function IStop,CS85 – 24 32 µA 4)6)9)11)12) Current consumption for watchdog active in Stop Mode IStop,WD25 – 18 23 µA 4)13) Stop Mode; Watchdog running; P_4.4.28 Current consumption for watchdog active in Stop Mode IStop,WD85 – 19 25 µA 4)13) Stop Mode; Tj = 85°C; Watchdog running; P_4.4.29 Current Sense Amplifier ICSA1 – – 4 mA 13) CSA_OFF = 0B; VCSP P_4.4.31 = VCSAP = VCSAN = 0 V; CSO_CAP = 0B; CCSO = 330 pF Current Sense Amplifier ICSA2 – – 10 mA 13) CSA_OFF = 0B; VCSP P_4.4.36 = VCSAP = VCSAN = 0 V; CSO_CAP = 1B; CCSO = 2.2 nF Current consumption in parking braking mode (LSx ON) Iparking – 10 14 µA 4)13) Stop Mode or P_4.4.32 Sleep Mode; Tj < 85°C; PARK_BRK_EN = 1B Current consumption Over voltage braking mode (LSx OFF) IOV,LS_OFF – 7 10 µA 4)13) Stop Mode or P_4.4.34 Sleep Mode; Tj < 85°C; OV_BRK_EN = 1B – 30 40 mA Normal Mode; Tj = -40°C to +150°C; CPEN = 1; All HB OFF Current consumption in VS ICP,BD for Charge Pump and Bridge Driver Stop Mode; Tj P_4.4.27 = 85°C; WD = off; P_4.4.35 1) Measured at VSINT. 2) If the load current on VCC1 will exceed the configured VCC1 active peak threshold, the current consumption will increase by typ. 2.9 mA to ensure optimum dynamic load behavior. See also Chapter 6. 3) CAN not configured in Selective Wake Mode. 4) Not subject to production test, specified by design. 5) Current consumption adder also applies for during WUF detection (frame detect mode) when CAN Partial Networking is activated. 6) Current consumption adders of features defined for Stop Mode also apply for Sleep Mode and vice versa. Wake input signals are stable (i.e. not toggling), cyclic wake/sense & watchdog are OFF (unless otherwise specified). 7) No pull-up or pull-down configuration selected. Datasheet 18 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC General Product Characteristics 8) The specified WKx current consumption adder for wake capability applies regardless how many WK inputs are activated. 9) Additional current will be drawn from VS and VSINT. 10) Typical adder of additional high-side switch activation 200 µA. 11) HSx used for cyclic sense, Timerx with 20ms period, 0.1 ms on-time, no load. In general the current consumption adder for cyclic sense in Stop Mode can be calculated with below equation: IStop,CS_typ = 18 µA + (IStop,HS,25 x ton/TPer) where the 18 uA is the base current consumption of the digital cyclic sense/wake functionality. 12) Also applies to cyclic wake but without adder from HS biasing contribution. 13) Additional current will be drawn from VSINT. Notes 1. There is no additional current consumption contribution in Normal Mode due to PWM generators or Timers. 2. The quiescent current consumption in Stop Mode and Sleep Mode will increase for VSINT < 9 V. Datasheet 19 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC System Features 5 System Features This chapter describes the system features and behavior of the TLE9563-3QX: • State machine • Device configuration • State machine modes and mode transitions • Wake-up features such as cyclic sense and cyclic wake 5.1 Short State Machine Description The BLDC Motor System IC offers six operating modes: • Init Mode: Power-up of the device and after a soft reset. • Normal Mode: The main operating mode of the device. • Stop Mode: The first-level power saving mode with the main voltage regulator VCC1 enabled. • Sleep Mode: The second-level power saving mode with VCC1 disabled. • Restart Mode: An intermediate mode after a wake event from Sleep Mode or Fail-Safe Mode or after a failure (e.g. WD failure, VCC1 under voltage reset) to bring the microcontroller into a defined state via a reset. • Fail-Safe Mode: A safe-state mode after critical failures (e.g. Temperature shutdown) to bring the system into a safe state and to ensure a proper restart of the system. A special mode, called Software Development Mode, is available during software development or debugging of the system. All above mentioned operating modes can be accessed in this mode. However, the watchdog is still running, but no reset to the microcontroller is applied. Watchdog failures are indicated over INTN pin instead. However, the watchdog reset signaling can be reactivated again in Software Development Mode. The Watchdog will start always with the Long Open Windows (t_low). The BLDC Motor System IC is controlled via a 32-bit SPI interface (refer to Chapter 13 for detailed information). The configuration as well as the diagnosis is handled via the SPI. The device offers various supervision features to support functional safety requirements. Refer to Chapter 12 for more information. Datasheet 20 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC System Features 5.2 Device Configuration Two features on the BLDC Motor System IC can be configured by hardware: • The selection of the normal device operation or the Software Development Mode. • Enabling/disabling the CRC on the SPI interface. The configurations are done monitoring the follow pins: • INTN/TEST • PWM1/CRC The hardware configuration can be done typically at device power-up, where the device is in Init Mode or (only in case of CRC setting) in Restart Mode. Software development Mode configuration detail After the RSTN is released, the INTN/TEST pin is internally pulled HIGH with a weak pull-up resistor. Therefore the default configuration is the device in normal operation. In order to configure the Software Development Mode, the following conditions have to be fulfilled: • Init Mode from power-up • VCC1>Vrtx • POR=1 • RSTN = HIGH The Software Development Mode is configured using the following scheme: • Only one external pull-down on INTN/TEST pin followed by an arbitrary SPI command, the device latches the Software Development Mode. • External pull-up or no pull-down on INTN/TEST pin enable the device in normal operation. • To enter Software Development Mode, a pull-down resistor to GND might be used. Soft. Dev. Mode OFF for tSDM_F to avoid supply glitches The INTN/TEST is externally pulled-down INTN/TEST Intn_filt Soft. Dev. Mode ON tSDM_F RSTN Mode LATCHED (first SPI frame) Entry in Software Development Mode (not latched ) Init Mode Successful latched Software Development Mode Normal Mode Time/us Intn_filt: internal filtered INTN/TEST signal Figure 3 Software Development Mode Selection Timing Intn_filt is a filtered signal from INTN/TEST, with the filter time tSMD_F (P_11.2.7). Intn_filt starts (at the rising edge if RSNT) wit the value 1. Datasheet 21 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC System Features Note: If during monitoring the INTN/TEST pin for Software Development Mode entry, the device changes the mode without SPI command, the device will not enter/stay in Software Development Mode. CRC configuration detail The CRC is configured using the following scheme: • Pull-down on PWM1/CRC enable the CRC. • No external components on PWM1/CRC disables the CRC. In order to configure the CRC, the follow conditions have to be full filled: • Init Mode (from power-up) or Restart Mode • VCC1>Vrtx • POR=1 • RSTN = LOW The configuration selection is done during the reset delay time tRD1 with a continuous filter time of tCFG_F and the configuration (depending on the voltage level at PWM1/CRC) is latched at the rising edge of RSTN. VS_INT VPOR,r t VCC1 VRT1,r t RSTN Continuous Filtering with tCFG_F tRD1 t Configuration selection monitoring period Figure 4 CRC configuration Selection Timing Diagram at the device power-up. In case of mismatch between CRC setting between the device and µC (CRC_STAT), the device can accept two recovery SPI commands (static patterns). The pattern 67AA AA0EH (addr + rw_bit = 67 ; data = AAAA ; CRC = 0E ) enables the CRC. The pattern E7AA AAC3H (addr + rw_bit = E7 ; data = AAAA ; CRC = C3) disables the CRC. The patterns shall be send only in Normal Mode. For additional details about the CRC setting and configuration, refer also to Chapter 13.3.1. Datasheet 22 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC System Features 5.3 Block Description of State Machine The state machine describes the different states of operation, the device may get into. The following figure shows the state machine flow diagram. First battery connection Config.: settings can be changed in this device mode; Fixed: settings stay as defined in Normal Mode * The Software Development Mode is a super set of state machine where the WD reset is not signaled, CAN behavior differs in Init Mode. Otherwise, there are no differences in behavior. Soft Reset CSA OFF Init Mode * (Long open window) (3) (1) After Fail-Safe Mode entry, the device will stay for at least typ. 1s in this mode (with RSTN low) after a TSD2 event and min. typ. 100ms after other Fail-Safe Events. Only then the device can leave the mode via a wake-up event. Wake events are stored during this time. (3) VCC1 ON CP OFF HSx OFF BD OFF CAN(2) OFF WD fixed Cyc. Sense Cyc. Wake OFF OFF (2) For Software Development Mode CAN is ON in Init Mode and stays ON when going from there to Normal Mode. Any SPI command (3) HB Passive off due to gate-source resistors. CSA config. Normal Mode VCC1 ON Automatic Reset is released WD starts with long open window CP config. HSx config. BD config. CAN config. WD config. Cyc. Sense Cyc. Wake config. config. SPI cmd SPI cmd WD trigger SPI cmd CSA OFF Sleep Mode VCC1 over voltage (depend from VCC1_OV_MOD setting) CSA OFF Stop Mode VCC1 OFF CP(3) OFF HSx fixed BD(3) OFF VCC1 ON CP(3) OFF HSx fixed BD(3) OFF CAN WD OFF Cyc. Sense Cyc. Wake Cyc. Wake fixed WD fixed Cyc. Sense fixed CAN fixed fixed fixed Wake cap./ OFF Wake up event CSA OFF Restart Mode Sleep Mode entry without any wake source enabled Watchdog Failure VCC1 Under voltage (RO pin is asserted) VCC1 ON/ ramping CAN woken/OFF CP(3) OFF HSx OFF BD(3) OFF WD OFF Cyc. Sense Cyc. Wake OFF OFF LS short circuit during VS_OV event After 4x consecutive VCC1 under voltage events (if VS_INT > VS_INT_UV) After 4x consecutive Watchdog failure CSA OFF Fail-Safe Mode (1) CAN, LIN, WK, wake-up event OR Release of overtemperature TSD2 after a time depending on TSD2_DEL Figure 5 VCC1 OFF CP(3) OFF HSx OFF BD(3) OFF CAN WD OFF Cyc. Sense Cyc. Wake OFF Wake cap. OFF VCC1 over voltage (depend from VCC1_OV_MOD setting) TSD2 event VCC1 Short to GND State Diagram showing the operating modes Description: • ON /OFF:= Indicate if the module is enabled or disabled either via SPI or from the device itself • config:= Settings can be changed in this mode • fixed:= Settings stay as defined in Normal Mode or Init Mode • active/inactive:= Indicate if the device activates/deactivates one specific feature • Wake capable:= Transceiver that is capable to detect one wake-up events • woken:= Transceiver that has detected one wake-up event Datasheet 23 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC System Features 5.4 State Machine Modes Description 5.4.1 Init Mode The device starts up in Init Mode after crossing the power-on reset VPOR,r threshold (see also Chapter 12.3) and the watchdog will start with a long open window (tLW) after RSTN is released (High level). In Init Mode, the device waits for the microcontroller to finish its startup and initialization sequence. CSA OFF Init Mode (Long open window) Figure 6 Init Mode Table 5 Init Mode Settings VCC1 ON CP OFF HSx OFF BD OFF CAN OFF WD fixed Cyc. Sense OFF Cyc. Wake OFF Part/Function Value Description VCC1 ON • The VCC1 is ON WD fixed • Watchdog is fixed and set with a long open window (tLW) HSx OFF • All HSx are OFF BD OFF • Bridge Drivers is OFF CP OFF • Charge Pump is OFF CSA OFF • Current Sense Amplifier is OFF CAN OFF • CAN transceiver is OFF1) Cyc Sense OFF • Cycle Sense is OFF Cyc Wake OFF • Cycle Wake is OFF 1) Exception: The CAN transceiver is ON during Software Development Mode 5.4.2 Normal Mode The Normal Mode is the standard operating mode for the device. The VCC1 is active and all features are configurable. Supervision and monitoring features are enabled. Datasheet 24 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC System Features CSA config. Normal Mode VCC1 ON CP config. HSx config. BD config. CAN config. WD config. Cyc. Sense config. Cyc. Wake config. Figure 7 Normal Mode Table 6 Normal Mode Settings Part/Function Value Description VCC1 ON • VCC1 is active WD config • Watchdog may be configured by SPI HSx config • The High Side Switches may be configured and switched ON or OFF by SPI BD/CP config • The Bridge Drivers and Charge Pump may be configured and switched ON or OFF by SPI CSA config • Current Sense Amplifier may be configurable and switched ON or OFF by SPI CAN config • CAN may be configurable and switched ON or OFF by SPI Cyc. Sense config • Cyclic sense may be configured with the HSx, WKx inputs and Timer1 or Timer2 or SYNC (WK4) Cyc. Wake config • Cyclic wake can be configured with the Timer1 or Timer 2 5.4.3 Stop Mode The Stop Mode is the first level technique to reduce the overall current consumption by setting the voltage regulator VCC1 into a low-power mode. Note: All settings have to be done before entering Stop Mode. In Stop Mode any kind of SPI WRITE commands are ignored and the SPI_FAIL bit is set, except for changing to Normal Mode, triggering a device Soft Reset, refreshing the watchdog as well as for reading and clearing the SPI status registers. Note: Datasheet A wake-up event on CAN, WKx, Low-Side short circuit detection in parking braking mode or overvoltage brake detection, could generate an interrupt on pin INTN (based on INTN masking configuration; refer to Chapter 10) however, no change of the device mode will occur. 25 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC System Features CSA OFF Stop Mode Figure 8 Stop Mode Table 7 Stop Mode Settings VCC1 ON CP OFF HSx fixed BD OFF CAN fixed WD fixed Cyc. Sense fixed Cyc. Wake fixed Part/Function Value Description VCC1 ON • VCC1 is ON WD fixed • Watchdog is fixed as configured in Normal Mode HSx fixed • HSx are fixed as configured in Normal Mode BD/CP OFF • The Bridge Drivers and Charge Pump are OFF CSA OFF • Current Sense Amplifier is OFF CAN fixed • CAN fixed as configured in Normal Mode Cyc. Sense fixed • Cyclic sense fixed as configured in Normal Mode Cyc. Wake fixed • Cyclic wake is fixed as configured in Normal Mode Note: In Stop Mode, it is possible to activate the Low-Side of Bridge Drivers (e.g. in case of parking braking mode or overvoltage brake detection). Refer to Chapter 12.11 for additional details. 5.4.4 Sleep Mode The Sleep Mode is the second level technique to reduce the overall current consumption to a minimum needed to react on wake-up events or for the device to perform autonomous actions (e.g. cyclic sense). Note: All settings have to be done before entering Sleep Mode. CSA OFF Sleep Mode VCC1 OFF CP OFF HSx fixed BD OFF CAN WD OFF Cyc. Sense fixed Cyc. Wake fixed Wake cap./ OFF Figure 9 Datasheet Sleep Mode 26 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC System Features Table 8 Sleep Mode Settings Part/Function Value Description VCC1 OFF • VCC1 is OFF WD OFF • Watchdog is OFF HSx fixed • HSx are fixed as configured in Normal Mode BD/CP OFF • The Bridge Drivers and Charge Pump are OFF CSA OFF • Current Sense Amplifier is OFF CAN Wake Cap/ • OFF Cyc. Sense fixed • Cyclic sense fixed as configured in Normal Mode Cyc. Wake fixed • Cyclic wake is fixed CAN fixed as configured (Wake Capable or OFF) Note: In Sleep Mode, it is possible to activate the Low-Side’s of Bridge Drivers (e.g. in case of parking braking mode or overvoltage braking). Refer to Chapter 12.11 for additional details. 5.4.5 Restart Mode The Restart Mode is a transition state where the RSNT pin is asserted. CSA OFF Restart Mode (RO pin is asserted) VCC1 ON/ ramping CAN woken/ OFF Figure 10 Restart Mode Table 9 Restart Mode Settings CP OFF HSx OFF BD OFF WD OFF Cyc. Sense OFF Cyc. Wake OFF Part/Function Value Description VCC1 ON/ ramping • VCC1 is ON or ramping up WD OFF • WD will be disabled if it was activated before HSx OFF • HSx will be disabled if it was activated before BD/CP OFF • The Bridge Drivers and Charge Pump are OFF CSA OFF • Current Sense Amplifier is OFF CAN Woken/ wake capable/ OFF • CAN may woken (in case of wake-up event on the Bus) or wake capable or OFF Datasheet 27 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC System Features Table 9 Restart Mode Settings (cont’d) Part/Function Value Description Cyc. Sense OFF • Cyclic sense will be disabled if it was activated before Cyc. Wake OFF • Cyclic wake will be disabled if it was activated before 5.4.6 Fail-Safe Mode The purpose of this mode is to bring the system in a safe status after a failure condition by turning OFF the VCC1 supply and powering off the microcontroller. After a wake event the system is then able to restart again. CSA OFF Fail-Safe Mode VCC1 OFF CP OFF HSx OFF BD OFF CAN WD OFF Cyc. Sense OFF Cyc. Wake OFF Wake cap. Figure 11 Fail-Safe Mode Table 10 Fail-Safe Mode Settings Part/Function Value Description VCC1 OFF • VCC1 is switched OFF WD OFF • WD is switched OFF HSx OFF • HSx are switched OFF BD/CP OFF • The Bridge Drivers and Charge Pump are OFF CSA OFF • Current Sense Amplifier is OFF CAN Wake Cap • CAN is forced to be Wake capable Cyc. Sense OFF • Cyclic sense is switched OFF Cyc. Wake OFF • Cyclic wake is switched OFF Note • In Fail-Safe Mode, the default wake sources CAN and WKx (if configured as wake inputs) are activated automatically and all wake event bits will be cleared. • The Fail-Safe Mode will be maintained until a wake event on the default wake sources occurs. To avoid any fast toggling behavior a filter time of typ. 100ms (tFS,min) is implemented. Wake events during this time will be stored and will automatically lead to entering Restart Mode after the filter time. In case of an VCC1 overtemperature shutdown (TSD2) the Restart Mode will be reached automatically after a filter time of typ. 1s (tTSD2) without the need of a wake event once the device temperature has fallen below the TSD2 threshold. • The parking braking mode is automatically disabled in Fail-Safe Mode. Datasheet 28 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC System Features 5.4.7 Software Development Mode The Software Development Mode is a dedicated device configuration especially useful for software development. Compared to the default device user mode operation, this mode is a super set of the state machine. The device will start also in Init Mode and it is possible to use all the modes and functions with following differences: • Restart Mode or Fail-Safe Mode (depending on the configuration) is not reached due to watchdog failure but the other reasons to enter these modes are still valid. • CAN default value in Init Mode and entering Normal Mode from Init Mode is ON instead of OFF. Table 11 Normal Mode Settings (Software Development Mode active) Part/Function Default State Description VCC1 ON • VCC1 is active WD ON • WD is on, but will not trigger transition to Fail-Safe Mode or Restart Mode HSx OFF • The High Side Switches may be configured and switched ON or OFF by SPI BD/CP OFF • The Bridge Drivers and Charge Pump may be configured and switched ON or OFF by SPI CAN ON • CAN may be configurable and switched ON or OFF by SPI Cyc. Sense OFF • Can be configured Cyc. Wake OFF • Can be configured Software Development Mode entry For timing and configuration details, refer to Chapter 5.2. Note • After Init Mode, the pull-up is released as the INTN/TEST pin acts as output then to drive the INTN signal. • If the device enters Fail-Safe Mode due to VCC1 short circuit to GND during the Init Mode, the Software Development Mode will not be entered and can only be reached at the next power-up of the device after the VCC1 short circuit is removed. • The absolute maximum ratings of the pin INTN must be observed. To increase the robustness of this pin during debugging or programming a series resistor between INTN and the connector can be added. Watchdog in Software Development Mode The Watchdog is enabled in Software Development Mode as default state. One INTN event is generated due to wrong watchdog trigger. It is possible to deactivate the integrated Watchdog module using the WD_SDM_DISABLE bit. After disabling the Watchdog, no INTN events are generated and the WD_FAIL bit will also not be set anymore in case of a trigger failure. It is also possible only to mask / unmask the INTN event of the WD in Software Development Mode by using the bit WD_SDM. In case of unmasking, a WD trigger fail will only lead to WD_FAIL bit set. 5.5 Transition Between States This chapter describes the transition between the modes triggered by power-up, SPI commands or wake-up events. Datasheet 29 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC System Features 5.5.1 Transition into Init Mode The device goes into Init Mode in case of a power-up or after sending a soft-reset in Normal or Stop Mode. Prerequisites: • Power OFF • Device in Normal Mode or Stop Mode with follow conditions: – VSINT > VPOR,r – RSTN High Triggering Events: • A Soft Reset command (MODE = ‘11’). All SPI registers will be changed to their respective Soft Reset values. Note • In case of Soft Reset command, a hardware RSTN event can be generated depending on the configuration. An external Reset will be generated in case of SOFT_RESET_RO = 0B . In case of SOFT_RESET_RO = 1B, no RSTN hardware event is generated in case of Soft Reset. • At power-up, the SPI bit VCC1_UV will not be set as long as VCC1 is below the VRT,x threshold and if VSINT is below the VSINT,UV threshold. The RSTN pin will be kept LOW as long as VCC1 is below the selected VRT1,r threshold. The reset delay counter will start after VRT1,r threshold is reached. After the first threshold crossing of VCC1 > VRT1,R and RSTN transition from low to high, all subsequent undervoltage events will lead to Restart Mode. • Wake events are ignored during Init Mode and will be lost. • The bit VSINT_UV will only be updated in Init Mode once RSTN resumes a high level. 5.5.2 Init Mode -> Normal Mode This transition moves the device in the mode where all configurations are accessable via SPI command. Prerequisites: • VSINT > VPOR,r • Init Mode • RSTN High Triggering Events: • Any valid SPI command (from SPI protocol point of view) will bring the device to Normal Mode (i.e. any register can be written, cleared and read) during the long open window where the watchdog has to be triggered (refer also Chapter 13.2). The CRC is not taken into account for this transition. • For example: – A SPI Sleep Mode command will still bring the device into Normal Mode. However, as this is an invalid state transition, the SPI bit SPI_FAIL is set. – Any invalid SPI command (from content point of view) will still bring the device into Normal Mode. The SPI bit SPI_FAIL is set. Note • It is recommended to use the first SPI command to trigger and to configure the watchdog. 5.5.3 Normal Mode -> Stop Mode This transition is intended as first measure to reduce the current consumption. All the device features needed in Stop Mode shall be configured in Normal Mode. Datasheet 30 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC System Features Prerequisites: • VCC1>Vrtx • Device in Normal Mode Triggering Events: • State transition is only initiated by specific SPI command. Note • An interrupt is triggered on the pin INTN when Stop Mode is entered and not all wake source signalization flags were cleared. • If high-side switches are kept enabled during Stop Mode, then the device current consumption will increase. • It is not possible to switch directly from Stop Mode to Sleep Mode. Doing so will also set the SPI_FAIL flag and will bring the device into Restart Mode. 5.5.4 Normal Mode -> Sleep Mode This transition is intended to reduce as much as possible the current consumption keeping active only wakeup sources. All wake-up sources configurations shall be done in Normal Mode. Prerequisites: • VCC1>Vrtx • Device in Normal Mode • All wake source signalization flags were cleared (including the LSxDSOV_BRK bit) • At least one wake-up source activated Triggering Events: • State transition is only initiated by specific SPI command. Note • If the HSx outputs are kept enabled during Sleep Mode, then the device current consumption will increase (see Chapter 4.4). • The Cyclic Sense function will not work properly anymore in case of a failure event (e.g. overcurrent, over temperature, reset) because the configured HSx and Timers will be disabled. • If VCC1_UV or VCC1_OV (with Config to go to Restart Mode) occurs at the border of the Sleep Mode entry: The device will go immeditaley into Restart Mode. • If TSD2 or VCC1_OV (with Config to go to Fail-Safe Mode) occurs at the border of the Sleep Mode entry: The device will enter immediately Fail-Safe Mode. • As soon as the Sleep Mode command is sent, the Reset will go low. • It is not possible to switch all wake sources off in Sleep Mode. Doing so will set the SPI_FAIL flag and will bring the device into Restart Mode. 5.5.5 Stop Mode -> Normal Mode This transition is intented to set the device in Normal Mode where all the device integrated features are availbale and configurable. Prerequisites: • VCC1>Vrtx Datasheet 31 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC System Features • Device in Stop Mode Triggering Events: • State transition is only initiated by SPI command. Note • None 5.5.6 Sleep Mode -> Restart Mode This transition is the consequence of a detection of wake-up event by the device. This transition is used to ramp up VCC1 after a wake in a defined way. Prerequisites: • Device in Sleep Mode • At least one wake-up source active Triggering Events: • A wake-up event on CAN, WKx, Cyclic Sense, Cyclic Wake. • Bridge driver low-side short circuit detected during overvoltage braking or in parking braking mode. Note • It is not possible to switch off all wake sources in Sleep Mode. Doing so will set the SPI_FAIL flag and will bring the device into Restart Mode. • RSTN is pulled low during Restart Mode. • The Restart Mode entry is signalled in the SPI register DEV_STAT. • The wake-up events are flaged in WK_STAT register or DSOV register. 5.5.7 Restart Mode -> Normal Mode From Restart Mode, the device goes automatically to Normal Mode. Prerequisites: • Device in Sleep Mode or Fail-Safe Mode Triggering Events: • Automatic • Reset is released Note • The watchdog timer will start with a long open window starting from the moment of the rising edge of RSTN and the watchdog period setting in the register WD_CTRL will be changed to the respective default value. 5.5.8 Fail-Safe Mode -> Restart Mode This transition is similar to device from Sleep Mode to Restart Mode and consequence of a detection of wakeup event by the device. This transition is used to ramp up VCC1 after a wake in a defined way. Prerequisites: • Device in Fail-Safe Mode Triggering Events: Datasheet 32 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC System Features • A wake-up event on CAN, WKx, TSD2 (released over temperature TDS2 after tTSD2). • Bridge Driver Low Side short circuit detected during VS/VSINT overvoltage braking mode or in parking braking mode. Note: After leaving Fail-Safe Mode, the FAILURE bit in DEV_STAT register is set. 5.6 Reaction on Detected Faults The device can react at some critical events either signalling the specific failure or changing the device mode. The chapter describes actions taken from the device in case of critical events in particular related the device mode change. 5.6.1 Stay in Current State The following failures will not trigger any device mode changes, but will indicate the failures by an INTN event (depending from the Interrupt Masking) and in dedicated status registers: • Failures on CAN • Failures in Bridge Driver and/or Charge Pump • Failures on HSx 5.6.2 Transition into Restart Mode The Restart Mode can be entered in case of failure as shown in following figure. VCC1 over voltage (depend from VCC1_OV_MOD setting) Restart Mode Sleep Mode entry without any wake source enabled Watchdog Failure VCC1 Under voltage (RO pin is asserted) VCC1 ON/ ramping CAN woken/OFF Figure 12 CSA OFF CP OFF HSx OFF BD OFF WD OFF Cyc. Sense Cyc. Wake OFF OFF Move into Restart Mode Prerequisites • In case of wake-up event from Sleep Mode or Fail Safe Mode • In case of Normal Mode • In case of Stop Mode Trigger Events • VCC1 Undervoltage in case of Normal Mode or Stop Mode. • Watchdog trigger failure in case of Normal Mode or Stop Mode. • VCC1 Overvoltage (based on VCC1_OV_MOD) in case of Normal Mode or Stop Mode. Datasheet 33 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC System Features • Sleep Mode entry without any wake-up sources enabled in Normal Mode or Stop Mode. Note • None Datasheet 34 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC System Features 5.6.3 Transition into Fail-Safe Mode The Fail-Safe Mode can be entered in case of critical event as shown in the following figure. After 4x consecutive VCC1 under voltage events (if VS_INT > VS_INT_UV) After 4x consecutive Watchdog failure CSA OFF Fail-Safe Mode VCC1 OFF CP OFF HSx OFF BD OFF CAN WD OFF Cyc. Sense Cyc. Wake OFF Wake cap. Figure 13 OFF VCC1 over voltage (depend from VCC1_OV_MOD setting) TSD2 event VCC1 Short to GND Move into Fail-Safe Mode Prerequisites: • Critical events on VCC1 • Watchdog trigger failures Trigger Events: • Device thermal shutdown (TSD2) (see also Chapter 12.10.3). • VCC1 is shorted to GND (see also Chapter 12.8). • VCC1 over voltage (based on VCC1_OV_MOD). • 4 consecutive Watchdog trigger failure. • 4 consecutive VCC1 under voltage events. 5.7 Wake Features Following wake sources are implemented in the device: • Static Sense: WKx inputs are permanently active as wake sources. • Cyclic Sense: WKx inputs only active during on-time of cyclic sense period. Internal timers are activating HSx during on-time for sensing the WKx inputs. • Cyclic Wake: wake controlled by internal timers, wake inputs are not used for cyclic wake. • CAN wake: Wake-up via Bus pattern or frame (refer to Chapter 8.2.4 and Chapter 5.9). Note: Datasheet Differences of 'cyclic sense' and 'cyclic wake': In both cases a timer is active. With 'cyclic sense' one of the high-side drivers is switched on periodically and supplies some external circuits connected to the WK inputs. For the design, this means that the WK input states are only sampled at the end of the selected HS on-phase which is set by the corresponding SPI settings for GPIO HS and the timer. 'Cyclic wake' means that the timer is a wake source and thus generates periodic interrupts as long as it is enabled. 35 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC System Features 5.7.1 Cyclic Sense The cyclic sense feature is intended to reduce the quiescent current of the device and the application. In the cyclic sense configuration, one high-side driver is switched on periodically controlled by TIMER_CTRL or WK4/SYNC pin. One high-side driver supplies external circuitries e.g. switches and/or resistor arrays, which are connected to one wake input WKx (see Figure 14). Any edge change of the WKx input signal during the ontime of the cyclic sense period causes a wake event. Depending on the device mode, either the INTN is pulled low (Normal Mode and Stop Mode) or the device is woken enabling the VCC1 (after Sleep Mode). HSx HSx HS_CTRL 10k 10k WKx WKx Signal TIMER_CTRL Period / On-Time Switching Circuitry INTN STATE MACHINE to uC Figure 14 Cyclic Sense Working Principle 5.7.1.1 Configuration and Operation of Cyclic Sense The correct sequence to configure the cyclic sense is shown in Figure 15. All the configurations have to be performed before the on-time is set in the TIMER_CTRL registers. The settings “OFF / LOW” and “OFF / HIGH” define the voltage level of the respective HS driver before the start of the cyclic sense. The intention of this selection is to avoid an unintentional wake due to a voltage level change at the start of the cyclic sense. Cyclic Sense will start as soon as the respective on-time has been selected independently from the assignment of the HS and filter configuration. The correct configuration sequence is as follows: • Configure the initial level. • Mapping of a Timer to the respective HSx outputs. • Configuring the respective filter timing and WK pins. • Configuring the timer period and on-time. Datasheet 36 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC System Features Cyclic Sense Configuration Assign TIMERx_ON to OFF/Low or OFF/High in TIMER_CTRL Timer1, Timer2 Assign Timer to selected HSx switch in HS_CTRL Timer1, Timer2 WKx with above selected timer Enable WKx as wake source with configured Timer in WK_CTRL Select WKx pull-up / pull-down configuration in WK_CTRL No pull-up/-down, pull-down or pullup selected, automatic switching Select Timer Period and desired On-Time in TIMER_CTRL Period: 10, 20, 50, 100, 200ms, 1s, 2s On-Time: 0.1, 0.3, 1.0, 10, 20ms A new timer configuration will become active immediately, i.e. as soon as CSN goes high Cyclic Sense starts / ends by setting / clearing On-time Figure 15 Datasheet Cyclic Sense: Configuration and Sequence 37 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC System Features Cyclic Sense Configuration Assign WK4 as SYNC input on WK_CTRL Assign SYNC to selected HSx switch in HS_CTRL Enable WKx as wake source with configured SYNC in WK_CTRL Select WKx pull-up / pull-down configuration in WK_CTRL WKx except WK4 with SYNC No pull-up/-down, pull-down or pullup selected, automatic switching Cyclic Sense starts / ends by sensing SYNC rise/fall edge Figure 16 Cyclic Sense: Configuration and Sequence in case of SYNC usage Note • All configurations of period and on-time can be selected. However, recommended on-times for cyclic sense are 0.1ms, 0.3ms and 1ms for quiescent current saving reasons. The SPI_FAIL will be set if the ontime is longer than the period. • If the sequence is not ensured before entering Sleep Mode, then the cyclic sense function might not work properly, e.g. an interrupt could be missed or an unintentional interrupt could be triggered. However, if cyclic sense is the only wake source and it is not configured properly, then Restart Mode will be entered immediately because no valid wake source was set. • During the HSx on phase in cyclic-sensing, the WKx level is sampled only once (one sample point). In case, a level change will appear during HSx on phase, but before the sampling, as the sampling will happen at the end of the on time, the level change will not be detected and has to wait for the next sensing-cycle. A wake event caused by cyclic-sensing will also set the corresponding bit WKx_WU. During Cyclic Sense, WK_LVL_STAT is updated only with the sampled voltage levels of the WKx pin in Normal Mode or Stop Mode. The functionality of the sampling and different scenarios are depicted in Figure 17 to Figure 19. The behavior in Stop Mode and Sleep Mode is identical except that in Normal Mode and Stop Mode INTN will be triggered to signal a change of WKx input level and in Sleep Mode, VCC1 will power-up instead. A wake event will be triggered regardless if the bit WKx_WU is already set. Datasheet 38 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC System Features Cyclic Sense HSx static ON Period HSx Filter time tFWK1 Filter time tFWK1 On Time t 1st sample taken as reference Figure 17 Wake detection possible on 2nd sample Cyclic Sense Timing HSx Filter time High Low Switch Spike open closed WKx High Low n-1 INTN n Learning Cycle WKn-1= Low n+1 WKn= Low WKn = WKn-1 no wake event High WKn = WKn+1 = Low (but ignored because change during filter time) WKn = WKn+1 no wake event n+2 WKn+2= High WKn+2 ≠WKn+1 wake event Low INTN & WK Bit Set Start of Cyclic Sense Figure 18 Datasheet Cyclic Sense Example Timing for Stop Mode, HSx starts LOW, GND based WKx input 39 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC System Features HSx Filter time High Low Switch Spike open closed WKx High Low n-1 n Learning Cycle WKn-1= Low VCC1 High n+1 WKn= Low WKn = WKn-1 no wake event WKn = WKn+1 = Low (but ignored because change during filter time), WKn = WKn+1 no wake event Transition to Normal via Restart Mode Sleep Mode Low WK Bit Set Start of Cyclic Sense Figure 19 n+2 WKn+2= High WKn+2 ≠WKn+1 wake event Cyclic Sense Example Timing for Sleep Mode, HSx starts with ON, GND based WKx input The cyclic sense function will be disabled in case of following conditions: • in case Fail-Safe Mode is entered, the HSx switch will be disabled and the WKx pin will be changed to static sensing. An unintended wake-up event could be triggered when the WKx input is changed to static sensing. • In Normal Mode, Stop Mode, or Sleep Mode in case of an overcurrent, or overtemperature, or under- or overvoltage event, the respective HS switch will be disabled. 5.7.1.2 Cyclic Sense in Low-power Mode If cyclic sense is intended for Stop Mode or Sleep Mode, it is necessary to activate cyclic sense in Normal Mode before going to the low-power mode. A wake event due to cyclic sense will set the bit WKx_WU. In Stop Mode a wake event will trigger an interrupt, in Sleep Mode the wake event will send the device via Restart Mode to Normal Mode. Before returning to Sleep Mode, the wake status registers WK_STAT and DSOV must be cleared. Trying to go to Sleep Mode with uncleared wake flags will lead to a direct wake-up from Sleep Mode by going via Restart Mode to Normal Mode and triggering of RSTN. 5.7.2 Cyclic Wake For the cyclic wake feature one timer is configured as internal wake-up source and will periodically trigger an interrupt on INTN in Normal Mode and Stop Mode. During Sleep Mode, the timer triggers and wakes up the device again. The device enters via Restart Mode the Normal Mode. The correct sequence to configure the cyclic wake is shown in Figure 20. The sequence is as follows: Datasheet 40 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC System Features Cyclic Wake Configuration Disable Timer1 and Timer2 as a wake source in TIMER_CTRL To avoid unintentional interrupts Select Timer1 or Timer2 as a wake source in TIMER_CTRL No interrupt will be generated, if the timer is not enabled as a wake source Select Timer Period and any On-Time in TIMER_CTRL Periods: 10, 20, 50, 100, 200ms, 1s, 2s On-times: any (OFF/LOW & OFF/HIGH are not allowed) Cyclic Wake starts / ends by setting / clearing On-time INTN is pulled low at every rising edge of On-time except first one Figure 20 Cyclic Wake: Configuration and Sequence Note: The on-time is only used to enable the cyclic wake function regardless of the value of the on time, i.e. the on time value has no meaning to the cyclic wake function as long as it is not ‘000’ or ‘110’ or ‘111’. As in cyclic sense, the cyclic wake function will start as soon as the on-time is configured. An interrupt is generated for every start of the on-time except for the very first time when the timer is started. 5.7.3 Internal Timers Two integrated timers can be used to control the below features: • Cyclic Wake, i.e. to wake up the microcontroller periodically in Normal Mode, Stop Mode and Sleep Mode. • Cyclic Sense, i.e. to perform cyclic sensing using the wake input WKx and the HSx by mapping the timer accordingly via the HS_CTRL register. Datasheet 41 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC System Features 5.8 VS Supply Multiplexing VMAX SWITCH + - VSINT 1 INTERNAL SUPPLY MUX VS Figure 21 0 VS Supply Multiplexing The internal supply voltage is multiplexed from VSINT and VS, choosing continuously the larger of both. In case of transient low VBAT, the buffered supply voltage takes over the internal supply, avoiding loss of power. Note: Datasheet Only the internal digital logic of the device is supplied by the VMAX SWITCH. In case of a power loss of either VS or VSINT, the internal register values will not be lost. 42 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC 5.9 Partial Networking on CAN 5.9.1 CAN Partial Networking - Selective Wake Feature The CAN partial networking feature can be activated for Normal Mode, in Sleep Mode and in Stop Mode. For Sleep Mode the partial networking has to be activated before sending the device to Sleep Mode. For Stop Mode the Partial Networking has to be activated before going to Stop Mode. There are 2 detection mechanism available: • WUP (Wake-Up Pattern) this is a CAN wake, that reacts on the CAN dominant time, with 2 dominant signals. • WUF (Wake-Up frame) this is the wake-up on a CAN frame that matches the programmed message filter configured in the device via SPI. The default baudrate is set to 500 kBaud. Besides the commonly used baudrates of 125 kBaud and 250 kBaud, other baudrates up to 1 MBaud can be selected (see Chapter 13 for more details). Datasheet 43 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC 5.9.2 Partial Networking Function The CAN partial networking modes are shown in the following figure. CAN OFF SPI SPI CAN WK Mode without PN CAN Receive Only Mode CAN Normal Mode SPI SPI SPI CAN PN Config Check CAN Wakable Mode CAN Woken Up 1) Sleep Mode: Device goes to Restart Mode, RxD is low, SPI bits are set Stop Mode: Device stays in Stop Mode, Interrupt is triggered, RxD is low, SPI bits are set (only in case of CAN WK or SWK Mode, not in Receive Only with SWK or CAN Normal Mode with SWK) Enable/ Disable max. 4 CAN frames CAN Wake WUP CAN Wake WUP CAN WUP detection 1 Normal Mode: Device stays in Normal Mode, Interrupt is triggered, SPI bits are set, RxD is low (only in case of CAN WK or SWK Mode, not in Receive Only with SWK or CAN Normal Mode with SWK) tsilence CAN Protocoll Error Counter CAN WUF detection CAN frame error detection valid rearming not valid Tsilent N>0 1) CFG_VAL is cleared in Reastart Mode N=0 CAN WUF N=0 N-1 N+ N>32 Error counter overvlow SYSERR SYSERR Figure 22 Datasheet CAN WUP detection 2 CAN Selective Wake State Diagram 44 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC 5.9.2.1 Activation of SWK The following figure shows the principal of the SWK activation. Normal Mode SW not enabled CAN OFF SYNC = 1 CAN_x Enable CAN Handle wake event (incl. CAN mode toggling) Enabling CAN (not OFF) enables also the selective wake block. Block gets synchronous to the CAN bus. If one CAN Frame is received the bit SYNC = 1 is set Set SWK wake data. e.g. ID, ID_Mask, DATA Setting the data can also be done as first task Clear WK_STAT To avoid invalid configuration Set CFG_VAL = 1 Bit set to confirm by the microcontroller that valid data are programmed. Clear SYSERR To activate Selective Wake SYSERR 1 In case SWK not enabled: CAN Normal with SW -> CAN Normal CAN Rx Only with SW -> CAN Rx Only CAN Wakable with SW -> CAN Wakable SWK not enabled 0 Selective Wake is now enabled (INT is generated in case of WUF) CAN Mode must be toggled before (re-)enabling wake capable mode Enable a CAN Mode with SWK via CAN_x Bits SWK_SET = 1, WUP & WUF = 0, SYNC = 1 Check SWK_STAT Check & Clear WK_STAT Select low-power mode via MODE Bits To ensure that no wake-up event has taken place in meantime MODE = 10 MODE = 01 Sleep Mode Stop Mode Wake-up: VCC1 Power-up change to Normal Mode In case of WUF detection: CAN_WU = 1; WUF = 1; CFG_VAL = 0; SWK_SET = 0 INT generation stays in Stop Mode Notes: - Tsilence handling not shown in drawing - SYNC will only be set once CAN is „rearmed“ and at least one CAN frame was sent successfully Figure 23 Datasheet Flow for activation of SWK 45 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC 5.9.2.2 Wake-up Pattern (WUP) A WUP is signaled on the bus by two consecutive dominant bus levels for at least tWake1, each separated by a recessive bus level. Entering low -power mode , when selective wake-up function is disabled or not supported Ini Bus recessive > t WAKE1 Bias off Wait Bias off Bus dominant > tWAKE1 optional: tWAKE2 expired 1 Bias off Bus recessive > tWAKE1 optional: tWAKE2 expired 2 Bias off Bus dominant > tWAKE1 Entering CAN Normal or CAN Recive Only 3 tSilence expired AND Device in low-power mode Bias on Bus dominant > t WAKE1 Bus recessive > t WAKE1 4 tSilence expired AND device in low-power mode Bias on Figure 24 WUP detection following the definition in ISO11898-2:2016 5.9.2.3 Wake-up Frame (WUF) The wake-up frame is defined in ISO11898-2:2016. Only CAN frames according ISO11989-1 are considered as potential wake-up frames. A bus wake-up shall be performed, if selective wake-up function is enabled and a "valid WUF" has been received. The transceiver may ignore up to four consecutive CAN data frames that start after switching on the bias. A received frame is a “valid WUF” in case all of the following conditions are met: • The ID of the received frame is exactly matching a configured ID in the relevant bit positions. The relevant bit positions are given by an ID mask. The ID and the ID mask might have either 11 bits or 29 bits. • The DLC of the received frame is exactly matching the configured DLC. Datasheet 46 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC • In case DLC is greater than 0, the data field of the received frame has at least one bit set in a bit position, where also in the configured data mask in the corresponding bit position the bit is set. • No error exists according to ISO11898-2:2016 except errors which are signalled in the ACK field and EOF field. 5.9.2.4 CAN Protocol Error Counter The counter is incremented, when a bit stuffing, CRC or form error according to ISO11898-2:2016 is detected. If a frame has been received that is valid up to the end of the CRC field and the counter is not zero, the counter is decremented. If the counter has reached a value of 31, the following actions is performed on the next increment of this counter: • The selective wake function is disabled. • The CAN transceiver is woken. • SYSERR is set and the error counter value = 32 can be read. On each increment or decrement of the counter the decoder unit waits for at least 6 and most 10 recessive bits before considering a dominant bit as new start of frame. The error counter is enabled: • Whenever the CAN is in CAN Normal Mode, CAN Receive Only Mode or in WUF detection state. The error counter is cleared under the following conditions: • At the transition from WUF detection to WUP detection 1 (after tSILENCE expiration, while SWK is correctly enabled). • When WUF detection state is entered (in this way the counter will start from 0 when SWK is enabled). • At CAN rearming (when exiting the woken state). • When the CAN mode bits are selected ‘000’, ‘100’ (CAN off) or 0’01’ (Wake capable without SWK function enabled). • While CAN_FD_EN = ‘1’ and DIS_ERR_CNT = ‘1’ (the counter is cleared and stays cleared when these two bits are set in the SPI registers). The Error Counter is frozen: • After a wake-up being in woken state. The counter value can be read out of the bits ECNT. Datasheet 47 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC 5.9.3 Diagnoses Flags 5.9.3.1 PWRON/RESET-FLAG The power-on reset can be detected and read by the POR bit in the Status register. The VS power on resets all register in the device to reset value. SWK is not configured. 5.9.3.2 BUSERR-Flag Bus Dominant Time-out detection is implemented and signaled by CAN_Fail_x in register BUS_STAT. 5.9.3.3 TXD Dominant Time-out flag TXD Dominant timeout is shown in the SPI bit CAN_FAIL_x in register BUS_STAT. 5.9.3.4 WUP Flag The WUP bit in the SWK_STAT register shows that a Wake-Up Pattern (WUP) has caused a wake of the CAN transceiver. It can also indicate an internal mode change from WUP detection 1 state to WUF detection after a valid WUP. In the following case the bit is set: • SWK is activated: due to tSILENCE, the CAN changes into the state WUP detection 1. If a WUP is detected in this state, then the WUP bit is set. • SWK is deactivated: the WUP bit is set if a WUP wakes up the CAN. In addition, the CAN_WU bit is set. • In case WUP is detected during WUP detection 2 state (after a SYSERR) the bits WUP and CAN_WU are set. The WUP bit is cleared automatically by the device at the next rearming of the CAN transceiver. Note: It is possible that WUF and WUP bit are set at the same time if a WUF causes a wake out of SWK, by setting the interrupt or by restart out of Sleep Mode. The reason is because the CAN has been in WUP detection 1 state during the time of CAN SWK Mode (because of tSILENCE). See also Figure 22. 5.9.3.5 WUF Flag (WUF) The WUF bit in the SWK_STAT register shows that a Wake-Up frame (WUF) has caused a wake of the CAN block. In Sleep Mode this wake causes a transition to Restart Mode, in Normal Mode and in Stop Mode it causes an interrupt. Also in case of this wake the bit CAN_WU in the register WK_STAT is set. The WUF bit is cleared automatically by the device at the next rearming of the CAN SWK function. 5.9.3.6 SYSERR Flag (SYSERR) The bit SYSERR is set in case of an configuration error and in case of an error counter overflow. The bit is only updated (set to ‘1’) if a CAN mode with SWK is enabled via CAN_x. An interrupt is triggered on INTN every time SYSERR is set if the BUS_STAT is not masked. When programming selective wake via CAN_x, SYSERR = ‘0’ signals that the SWK function has been enabled. The bit can be cleared via SPI. The bit is ‘0’ after Power on Reset of the device. Datasheet 48 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC 5.9.3.7 Configuration Error A configuration error sets the SYSERR bit to ‘1’. A configuration check is performed when enabling SWK via the bits CAN_x. If the check is successful SWK is enabled, the bit SYSERR is set to ‘0’. In Normal Mode it is also possible to detect a Configuration Error while SWK is enabled. This will occur if the CFG_VAL bit is cleared, e.g. by changing the SWK registers (from address 011 0001 to address 011 1010). In Stop Mode and Sleep Mode this is not possible as the SWK registers can not be changed. Configuration Check: In Restart Mode, the CFG_VAL bit is cleared by the device. If the Restart Mode was not triggered by a WUF wake up from Sleep Mode and the CAN was with SWK enabled, than the SYSERR bit will be set. The SYSERR bit has to be cleared by the microcontroller. The SYSERR bit cannot be cleared when CAN_2 is ‘1’ and below conditions occur: • Data valid bit not set by microcontroller, i.e. CFG_VAL is not set to ‘1’. The CFG_VAL bit is reset after SWK wake and needs to be set by the microcontroller before activation SWK again. • CFG_VAL bit reset by the device when data are changed via SPI programming. (Only possible in Normal Mode) Note: The SWK configuration is still valid if only the SWK_CTRL register is modified. 5.9.3.8 CAN Bus Timeout-Flag (CANTO) In CAN WUF detection and CAN WUP detection 2 state the bit CANTO is set to ‘1’ if the time tSILENCE expires. The bit can be cleared by the microcontroller. If the interrupt function for CANTO is enabled then an interrupt is generated in Stop Mode or Normal Mode when the CANTO set to ‘1’. The interrupt is enabled by setting the bit CANTO_ MASK to ‘1’. Each CANTO event will trigger a interrupt even if the CANTO bit is not cleared. There is no wake out of Sleep Mode because of CAN time-out. 5.9.3.9 CAN Bus Silence-Flag (CANSIL) In CAN WUF detection and CAN WUP detection 2 state the bit CANSIL is set to ‘1’ if the time tSILENCE expires. The CANSIL bit is set back to ‘0’ with a WUP. With this bit the microcontroller can monitor if there is activity on the CAN bus while being in CAN SWK Mode. The bit can be read in Stop Mode and Normal Mode. 5.9.3.10 SYNC-FLAG (SYNC) The bit SYNC shows that SWK is working and synchronous to the CAN bus. To get a SYNC bit set it is required to enable the CAN to CAN Normal Mode or in CAN Receive Only Mode or in WUF detection. However - for WUF detection, the CAN SWK Mode must be enabled. The bit is set to ‘1’ if a valid CAN frame has been received (no CRC error and no stuffing error). It is set back to ‘0’ if a CAN protocol error is detected. When switching into CAN SWK Mode the SYNC bit indicates to the microcontroller that the frame detection is running and the next CAN frame can be detected as a WUF, CAN wake-up can now be handled by the device. It is possible to enter a low-power mode with SWK even if the bit is not set to ‘1’, as this is necessary in case of a silent bus. 5.9.3.11 SWK_SET FLAG (SWK_SET) The SWK_SET bit is set to signalize the following states (see also Figure 22): • When SWK was correctly enabled in WUF Detection state. • When SWK was correctly enabled when in WUP Detection 1 state. • After a SYSERR before a wake event in WUP Detection 2 state. Datasheet 49 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC The bit is cleared under following conditions: • After a wake-up (ECNT overflow, WUP in WUP detection 2, WUF in WUF detection). • If CAN_2 is cleared. 5.9.4 Modes for Selective Wake (SWK) The device mode is selected via the MODE bits as described in Chapter 5.3. The mode of the CAN transceiver needs to be selected in Normal Mode. The CAN mode is programed the bits CAN_0, CAN_1 and CAN_2. In the low-power modes (Stop, Sleep) the CAN mode can not be changed via SPI. The detailed state machine diagram including the CAN selective wake feature is shown in Figure 5. The application must now distinguish between the normal CAN operation an the selective wake function: • CAN WK Mode: This is the normal CAN wake capable mode without the selective wake function. • CAN SWK Mode: This is the CAN wake capable mode with the selective wake function enabled. Figure 25 shows the possible CAN transceiver modes. CAN OFF Mode CAN Normal Mode (no SWK) CAN WK Mode CAN Receive-Only Mode SPI CAN_x CAN Wakable Mode with SWK Config. Check OK Not OK CAN SWK CAN Normal mode with SWK CAN RX Only Mode with SWK CAN Normal mode CAN RX Only Mode Config. Check CAN WK Figure 25 CAN SWK State Diagram 5.9.4.1 Normal Mode with SWK OK Not OK CAN SWK Config. Check CAN WK OK Not OK CAN SWK CAN WK In Normal Mode the CAN Transceiver can be switched into the following CAN modes: • CAN OFF Mode • CAN WK Mode (without SWK) • CAN SWK Mode • CAN Receive Only Mode (No SWK activated) • CAN Receive Only Mode with SWK Datasheet 50 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC • CAN Normal Mode (No SWK activated) • CAN Normal Mode with SWK In the CAN Normal Mode with SWK the CAN Transceiver works as in Normal Mode, so bus data is received through RXD, data is transmitted through TXD and sent to the bus. In addition the SWK block is active. It monitors the data on the CAN bus, updates the error counter and sets the CANSIL flag if there is no communication on the bus. It will generate an CAN Wake interrupt in case a WUF is detected (RXD is not pulled to low in this configuration). In CAN Receive Only Mode with SWK, CAN data can be received on RXD and SWK is active, no data can be sent to the bus. The bit SYSERR = ‘0’ indicates that the SWK function is enabled, and no frame error counter overflow is detected. Table 12 CAN modes selected via SPI in Normal Mode CAN mode CAN_2 CAN_1 CAN_0 CAN OFF Mode 0 0 0 CAN WK Mode (no SWK) 0 0 1 CAN Receive Only Mode (no SWK) 0 1 0 CAN Normal Mode (no SWK) 0 1 1 CAN OFF Mode 1 0 0 CAN SWK Mode 1 0 1 CAN Receive Only Mode with SWK 1 1 0 CAN Normal Mode with SWK 1 1 1 When reading back CAN_x the programmed mode is shown in Normal Mode. To read the real CAN mode the bits SYSERR, SWK_SET and CAN have to be evaluated. A change out of Normal Mode can change the CAN_0 and CAN_1 bits. 5.9.4.2 Stop Mode with SWK In Stop Mode the CAN transceiver can be operated with the following CAN modes: • CAN OFF Mode • CAN WK Mode (no SWK) • CAN SWK Mode • CAN Receive Only Mode (no SWK) • CAN Receive Only Mode with SWK • CAN Normal Mode (no SWK) • CAN Normal Mode with SWK To enable CAN SWK Mode the CAN has to be switched to “CAN Normal Mode with SWK”, “CAN Receive Only Mode with SWK” or to “CAN SWK Mode” in Normal Mode before sending the device to Stop Mode. The bit SYSERR = ‘0’ indicates that the SWK function is enabled. The table shows the change of CAN mode when switching from Normal Mode to Stop Mode. Note: Datasheet CAN Receive Only Mode in Stop Mode is implemented to also enable pretended networking (Partial networking done in the microcontroller). 51 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Table 13 CAN modes change when switching from Normal Mode to Stop Mode Programmed CAN mode in Normal Mode CAN_x bits SYSERR bit CAN mode in Stop Mode CAN_x bits CAN OFF Mode 000 0 CAN OFF Mode 000 CAN WK Mode (no SWK) 001 0 CAN WK Mode (no SWK) 001 CAN Receive Only Mode (no SWK) 010 0 CAN Receive Only Mode (no SWK) 010 CAN Normal Mode (no SWK) 011 0 CAN Normal Mode (no SWK) 011 CAN OFF Mode 100 0 CAN OFF Mode 100 CAN SWK Mode 101 0 CAN SWK Mode 101 CAN SWK Mode 101 1 CAN WK Mode (no SWK) 101 CAN Receive Only Mode with SWK 110 0 CAN Receive Only Mode with SWK 110 CAN Receive Only Mode with SWK 110 1 CAN Receive Only Mode (no SWK) 110 CAN Normal Mode with SWK 111 0 CAN Normal Mode with SWK 111 CAN Normal Mode with SWK 111 1 CAN Normal Mode (no SWK) 111 Note: When SYSERR is set then WUF frames will not be detected, i.e. the selective wake function is not activated (no SWK), but the MSB of CAN mode is not changed in the register. 5.9.4.3 Sleep Mode with SWK In Sleep Mode the CAN Transceiver can be switched into the following CAN modes: • CAN OFF Mode • CAN WK Mode (without SWK) • CAN SWK Mode To enable “CAN SWK Mode” the CAN has to be switched to “CAN Normal Mode with SWK”, “CAN Receive Only Mode with SWK” or to “CAN SWK Mode” in Normal Mode before sending the device to Sleep Mode. The table shows the change of CAN mode when switching from Normal Mode to Sleep Mode. A wake from Sleep Mode with Selective Wake (Valid WUF) leads to Restart Mode. In Restart Mode the CFG_VAL bit will be cleared by the device, the SYSERR bit is not set. In the register CAN_x the programmed CAN SWK Mode (101) can be read. To enable the CAN SWK Mode again and to enter Sleep Mode the following sequence can be used; Program a CAN mode different from CAN SWK Mode (101, 110, 111), set the CFG_VAL, CLEAR SYSERR bit, Set CAN_x bits to CAN SWK Mode (101), switch the device to Sleep Mode. To enable the CAN WK Mode or CAN SWK Mode again after a wake on CAN a rearming is required for the CAN transceiver to be wake capable again. The rearming is done by programming the CAN into a different mode with the CAN_x bit and back into the CAN WK Mode or CAN SWK Mode. To avoid lock-up when switching the device into Sleep Mode with an already woken CAN transceiver, the device does an automatic rearming of the CAN transceiver when switching into Sleep Mode. So after switching into Sleep Mode the CAN transceiver is either in CAN SWK Mode or CAN WK Mode depending on CAN_x setting and SYSERR bit (If CAN is switched to off mode it is also off in Sleep Mode). Datasheet 52 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Table 14 CAN modes change when switching to Sleep Mode Programmed CAN mode in Normal CAN_x Mode bits SYSERR bit CAN mode in Sleep Mode CAN_x bits CAN OFF Mode 000 0 CAN OFF Mode 000 CAN WK Mode (no SWK) 001 0 CAN WK Mode (no SWK) 001 CAN Receive Only Mode (no SWK) 010 0 CAN WK Mode (no SWK) 001 CAN Normal Mode (no SWK) 011 0 CAN WK Mode (no SWK) 001 CAN OFF Mode 100 0 CAN OFF Mode 100 CAN SWK Mode 101 0 CAN SWK Mode 101 CAN SWK Mode 101 1 CAN WK Mode (no SWK) 101 CAN Receive Only Mode with SWK 110 0 CAN SWK Mode 101 CAN Receive Only Mode with SWK 110 1 CAN WK Mode (no SWK) 101 CAN Normal Mode with SWK 111 0 CAN SWK Mode 101 CAN Normal Mode with SWK 111 1 CAN WK Mode (no SWK) 101 5.9.4.4 Restart Mode with SWK If Restart Mode is entered the transceiver can change the CAN mode. During Restart or after Restart the following modes are possible: • CAN OFF Mode • CAN WK Mode (either still wake cable or already woken up) • CAN SWK Mode (WUF Wake from Sleep) Table 15 CAN modes change in case of Restart out of Normal Mode Programmed CAN mode in Normal Mode CAN_x bits SYSERR bit CAN mode in and after Restart Mode CAN_x bits SYSERR bit CAN OFF Mode 000 0 CAN OFF Mode 000 0 CAN WK Mode (no SWK) 001 0 CAN WK Mode (no SWK) 001 0 CAN Receive Only Mode (no SWK) 010 0 CAN WK Mode (no SWK) 001 0 CAN Normal Mode (no SWK) 011 0 CAN WK Mode (no SWK) 001 0 CAN OFF Mode 100 0 CAN OFF Mode 100 0 CAN SWK Mode 101 0 CAN WK Mode (no SWK) 101 1 CAN SWK Mode 101 1 CAN WK Mode (no SWK) 101 1 CAN Receive Only Mode with SWK 110 0 CAN WK Mode (no SWK) 101 1 CAN Receive Only Mode with SWK 110 1 CAN WK Mode (no SWK) 101 1 CAN Normal Mode with SWK 111 0 CAN WK Mode (no SWK) 101 1 CAN Normal Mode with SWK 111 1 CAN WK Mode (no SWK) 101 1 The various reasons for entering Restart Mode and the respective status flag settings are shown in Table 16. Datasheet 53 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Table 16 CAN modes change in case of Restart out of Sleep Mode CAN mode in Sleep Mode CAN mode in and after Restart Mode CAN_ SYS x ERR CAN_ WUP WU WUF ECNT_ Reason for Restart x CAN OFF Mode CAN off 000 0 0 0 0 0 Wake on other wake source CAN WK Mode CAN woken up 001 0 1 1 0 0 Wake (WUP) on CAN CAN WK Mode CAN WK Mode 001 0 0 0 0 0 Wake on other wake source CAN SWK Mode CAN woken up 101 0 1 0/11) 1 x Wake (WUF) on CAN CAN SWK Mode, CAN woken up 101 1 1 0/12) 0 100000 Wake due to error counter overflow CAN SWK selected, CAN WK active CAN woken up. 101 1 1 1 0 0 Wake (WUP) on CAN, config check was not pass CAN SWK Mode CAN WK Mode 1 0 0/1 0 x Wake on other wake source 101 1) In case there is a WUF detection within tSILENCE then the WUP bit will not be set. Otherwise it will always be set together with the WUF bit. 2) In some cases the WUP bit might stay cleared even after tSILENCE, e.g. when the error counter expires without detecting a wake-up pattern. 5.9.4.5 Fail-Safe Mode with SWK When Fail-Safe Mode is entered the CAN transceiver is automatically set into CAN WK Mode (wake capable) without the selective wake function. 5.9.5 Wake-up A wake-up via CAN leads to a restart out of Sleep Mode and to an interrupt in Normal Mode, and in Stop Mode. After the wake event the bit CAN_WU is set, and the details about the wake can be read out of the bits WUP, WUF, SYSERR, and ECNT. 5.9.6 Configuration for SWK The CAN protocol handler settings can be configured in following registers: • SWK_BTL1_CTRL defines the number of time quanta in a bit time. This number depends also on the internal clock settings performed in the register SWK_CDR_CTRL. • SWK_BTL1_CTRL defines the sampling point position. • The respective receiver during frame detection mode can be selected via the bit RX_WK_SEL. • The clock and data recovery (see also Chapter 5.9.8) can be configured in the registers SWK_CDR_CTRL and SWK_CDR_LIMIT. The actual configuration for selective wake is done via the Selective Wake Control Registers SWK_IDx_CTRL, SWK_MASK_IDx_CTRL, SWK_DLC_CTRL, SWK_DATAx_CTRL. Datasheet 54 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC The oscillator has the option to be trimmed by the microcontroller. To measure the oscillator, the SPI bit OSC_CAL needs to be set to 1 and a defined pulse needs to be given to the TXDCAN pin by the microcontroller (e.g. 1µs pulse, CAN needs to be switched off before). The device measures the length of the pulse by counting the time with the integrated oscillator. The counter value can be read out of the register SWK_OSC_CAL_H_STATE and SWK_OSC_CAL_L_STATE. To change the oscillator the trimming function needs to be enabled by setting the bits TRIM_EN_x = 11 (and OSC_CAL = 1). The oscillator can then be adjusted by writing into the register SWK_OSC_TRIM_CTRL. To finish the trimming, the bits TRIM_EN_x need to be set back to “00”. 5.9.7 CAN Flexible Data Rate (CAN FD) Tolerant Mode The CAN FD tolerant mode can be activated by setting the bit CAN_FD_EN = ‘1’ in the register SWK_CAN_FD_CTRL. With this mode the internal CAN frame decoding will be stopped for CAN FD frame formats: • The high baudrate part of a CAN FD frame will be ignored. • No Error Handling (Bit Stuffing, CRC checking, Form Errors) will be applied to remaining CAN frame fields (Data Field, CRC Field, …). • No wake up is done on CAN FD frames. The internal CAN frame decoder will be ready for new CAN frame reception when the End of frame (EOF) of a CAN FD frame is detected.The identification for a CAN FD frame is based on the EDL Bit, which is sent in the Control Field of a CAN FD frame: • EDL Bit = 1 identifies the current frame as an CAN FD frame and will stop further decoding on it. • EDL Bit = 0 identifies the current frame as CAN 2.0 frame and processing of the frame will be continued. In this way it is possible to send mixed CAN frame formats without affecting the selective wake functionality by error counter increment and subsequent misleading wake up. In addition to the CAN_FD_EN bit also a filter setting must be provided for the CAN FD tolerant mode. This filter setting defines the minimum dominant time for a CAN FD dominant bit which will be considered as a dominant bit from the CAN FD frame decoder. This value must be aligned with the selected high baudrate of the data field in the CAN network. To support programming via CAN during CAN FD mode a dedicated SPI bit DIS_ERR_ CNT is available to avoid an overflow of the implemented error counter (see also Chapter 5.9.2.4). The behavior of the error counter depends on the setting of the bits DIS_ERR_ CNT and CAN_FD_EN and is show in below table: Table 17 Error Counter Behavior DIS_ERR_ CNT setting CAN_FD_EN setting Error Counter Behavior 0 0 Error Counter counts up when a CAN FD frame or an incorrect/corrupted CAN frame is received; counts down when a CAN frame is received properly (as specified in ISO11898-2:2016) 1 0 Error Counter counts up when a CAN FD frame or an incorrect/corrupted CAN frame is received; counts down when a CAN frame is received properly (as specified in ISO11898-2:2016) Datasheet 55 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Table 17 Error Counter Behavior (cont’d) DIS_ERR_ CNT setting CAN_FD_EN setting Error Counter Behavior 0 1 Error Counter counts up when an incorrect/corrupted CAN frame is received; counts down when correct, including CAN FD frame, is received 1 1 Error Counter is and stays cleared to avoid an overflow during programming via CAN The DIS_ERR_ CNT bit is automatically cleared at tSILENCE expiration. Datasheet 56 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC 5.9.8 Clock and Data Recovery In order to compensate possible deviations on the CAN oscillator frequency caused by assembly and lifetime effects, the device features an integrated clock and data recovery (CDR). It is recommended to always enable the CDR feature during SWK operation. 5.9.8.1 Configuring the Clock Data Recovery for SWK The Clock and Data Recovery can be optionally enabled or disabled with the CDR_EN bit in the SWK_CDR_CTRL SPI register. In case the feature is enabled, the CAN bit stream will be measured and the internal clock used for the CAN frame decoding will be updated accordingly. Before the Clock and Data Recovery can be used it must be configured properly related to the used baud rate and filtering characteristics (see Chapter 5.9.8.2). It is strongly recommended not to enable/disable the Clock Recovery during a active CAN Communication. To ensure this, it is recommended to enable/disable it during CAN off (BUS_CTRL; CAN[2:0] = 000). CDR 80 Mhz Oscilator (analog) Aquisition Filter Sampling Point Calculation CAN Protocoll Handler RX CAN Receiver (analog) Figure 26 Datasheet Clock and Data Recovery Block Diagram 57 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC 5.9.8.2 Setup of Clock and Data Recovery It is strongly recommended to enable the clock and data recovery feature only when the setup of the clock and data recovery is finished. The following sequence should be followed for enabling the clock and data recovery feature: • Step 1: Switch CAN to off and CDR_EN to off Write SPI Register BUS_CTRL (CAN[2:0] = 000). • Step 2: Configure CDR Input clock frequency Write SPI Register SWK_CDR_CTRL (SEL_OSC_CLK[1:0]). • Step 3: Configure Bit timing Logic Write SPI Register SWK_BTL1_CTRL and adjust SWK_CDR_LIMIT according to Table 91. • Step 4: Enable Clock and Data Recovery Choose filter settings for Clock and Data recovery. Write SPI Register SWK_CDR_CTRL with CDR_EN = 1. Additional hints for the CDR configuration and operation: • Even if the CDR is disabled, when the baud rate is changed, the settings of SEL_OSC_CLK in the register SWK_CDR_CTRL and SWK_BTL1_CTRL have to be updated accordingly. • The SWK_CDR_LIMIT registers has to be also updated when the baud rate or clock frequency is changed (the CDR is discarding all the acquisitions and looses all acquired information, if the limits are reached - the SWK_BTL1_CTRL value is reloaded as starting point for the next acquisitions). • When updating the CDR registers, it is recommended to disable the CDR and to enable it again only after the new settings are updated. • The SWK_BTL1_CTRL register represents the sampling point position. It is recommended to be used at default value: 11 0011 (~80%). Datasheet 58 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC 5.9.9 Electrical Characteristics Table 18 Electrical Characteristics VSINT = 5.5 V to 28 V; Tj = -40°C to +150°C; 4.75 V < VCAN < 5.25 V; RL = 60 Ω; CAN Normal Mode; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Min. Typ. Max. Unit Note or Test Condition 1) Number CAN Partial Network Timing Bus Bias reaction time tbias – – 250 µs Load RL = 60 Ω, P_5.10.2 CL = 100 pF, CGND = 100 pF Wake-up reaction time (WUP or WUF) tWU_WUP/WUF – – 100 µs 1)2)3) Wake-up P_5.10.3 reaction time after a valid WUP or WUF; Min. Bit Time tBit_min – – µs 1)4) Datasheet 1 59 P_5.10.4 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Table 18 Electrical Characteristics (cont’d) VSINT = 5.5 V to 28 V; Tj = -40°C to +150°C; 4.75 V < VCAN < 5.25 V; RL = 60 Ω; CAN Normal Mode; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Min. Typ. Max. Unit Note or Test Condition 6) Number CAN FD Tolerance5) SOF acceptance nBits_idle 6 – 10 bits Number of P_5.10.5 recessive bits before a new SOF shall be accepted Dominant signals which are ignored (up to 2MBit/s) tFD_Glitch_4 0 - 5 % 6)7)8) of P_5.10.6 arbitration bit time; to be configured viaFD_FILTER; Dominant signals which are ignored (up to 5MBit/s) tFD_Glitch_10 0 - 2.5 % 6)8)9) of arbitration P_5.10.7 bit time; to be configured viaFD_FILTER; Signals which are detected as a dominant data bit after the FDF bit and before EOF bit (up to 2MBit/s) tFD_DOM_4 17.5 - - % 6)7)8) of arbitration P_5.10.8 bit time; to be configured viaFD_FILTER; Signals which are detected as a dominant data bit after the FDF bit and before EOF bit (up to 5MBit/s) tFD_DOM_10 8.75 - - % 6)8)9) of arbitration P_5.10.9 bit time; to be configured viaFD_FILTER; 1) Not subject to production test, tolerance defined by internal oscillator tolerance. 2) Wake-up is signalized via INTN pin activation in Stop Mode and via VCC1 ramping up with wake from Sleep Mode. 3) For WUP: time starts with end of last dominant phase of WUP; for WUF: time starts with end of CRC delimiter of the WUF. 4) The minimum bit time corresponds to a maximum bit rate of 1 Mbit/s. The lower end of the bit rate depends on the protocol IC or the permanent dominant detection circuitry preventing a permanently dominant clamped bus. 5) Applies for an arbitration rate of up to 500 kbps until the FDF bit is detected. 6) Not subject to production test; specified by design. 7) A data phase bit rate less or equal to four times of the arbitration bit rate or 2 Mbit/s, whichever is lower. 8) Parameter applies only for the Normal Mode CAN receiver (RX_WK_sel = 1). 9) A data phase bit rate less or equal to four times of the arbitration bit rate or 5 Mbit/s, whichever is lower. Datasheet 60 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Voltage Regulator 1 6 Voltage Regulator 1 6.1 Block Description VCC1 VSINT Vref 1 Overtemperature Shutdown Bandgap Reference State Machine INH GND Figure 27 Module Block Diagram Functional Features • 5 V low-drop voltage regulator. • Undervoltage monitoring with adjustable reset level and VCC1 undervoltage prewarning (refer to Chapter 12.7 and Chapter 12.8 for more information). • Short circuit detection and switch off with undervoltage fail threshold, device enters Fail-Safe Mode. • Effective capacitance must be ≥ 1 µF at nominal voltage output for stability. A 2.2 µF ceramic capacitor (MLCC) is recommended for best transient response. • Output current capability up to IVCC1,lim. Datasheet 61 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Voltage Regulator 1 6.2 Functional Description The Voltage Regulator 1 (=VCC1) is “ON” in Normal Mode and Stop Mode and is disabled in Sleep Mode and in Fail-Safe Mode. The regulator can provide an output current up to IVCC1,lim. For low-quiescent current reasons, the output voltage tolerance is decreased in Stop Mode because only the less accurate low-power mode regulator will be active for small loads. If the load current on VCC1 exceeds the selected threshold (IVCC1,Ipeak1,r or IVCC1,Ipeak2,r) then the high-power mode regulator will be also activated to support an optimum dynamic load behavior. The current consumption will then increase (approx. 2.8 mA additional quiescent current). The device mode stays unchanged. If the load current on VCC1 falls below the selected threshold (IVCC1,Ipeak1,f or IVCC1,Ipeak2,f), then the low-quiescent current mode is resumed again by disabling the high-power mode regulator. Both regulators (low-power mode and high-power mode) are active in Normal Mode. Two different active peak thresholds can be selected via SPI: • I_PEAK_TH = ‘0’(default): the lower VCC1 active peak threshold 1 is selected with lowest quiescent current consumption in Stop Mode. • I_PEAK_TH = ‘1’: the higher VCC1 active peak threshold 2 is selected with an increased quiescent current consumption in Stop Mode. Datasheet 62 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Voltage Regulator 1 6.3 Electrical Characteristics Table 19 Electrical Characteristics VSINT = 5.5 V to 28 V; Tj = -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified). Parameter Min. Typ. Max. Unit Note or Test Condition Output Voltage including Line VCC1,out1 and Load Regulation 4.9 5.0 5.1 V 1) Output Voltage including Line VCC1,out2 and Load Regulation (Full Load Current Range) 4.9 5.0 5.1 V 1) Normal Mode; 6 V < VSINT < 28 V; 10 µA < IVCC1 < 250 mA P_6.3.2 Output Voltage including Line VCC1,out3 and Load Regulation (Higher Accuracy Rage) 4.95 – 5.05 V 2) Normal Mode; 20 mA < IVCC1 < 80 mA; 8 V < VSINT < 18 V; 25°C < Tj < 150°C P_6.3.3 Output Voltage including Line VCC1,out4 and Load Regulation (low-power mode) 4.9 5.05 5.2 V Stop Mode; 10 µA < IVCC1 < IVCC1,Ipeak P_6.3.4 Output Drop Voltage VCC1,d1 – 200 400 mV IVCC1 = 50 mA, VSINT = 5 V P_6.3.9 Output Drop Voltage VCC1,d2 – 300 500 mV IVCC1 = 150 mA, VSINT = 5 V P_6.3.10 VCC1 Active Peak Threshold 1 IVCC1,Ipeak1,r (Transition threshold between low-power and highpower mode regulator) – 3.25 5.0 mA 2) ICC1 rising; VSINT = 13.5 V; I_PEAK_TH = ‘0’ P_6.3.17 VCC1 Active Peak Threshold 1 IVCC1,Ipeak1,f (Transition threshold between high-power and lowpower mode regulator) 1.2 1.7 – mA 2) ICC1 falling; VSINT = 13.5V; I_PEAK_TH = ‘0’ P_6.3.18 VCC1 Active Peak Threshold 2 IVCC1,Ipeak2,r (Transition threshold between low-power and highpower mode regulator) 6 – 20 mA 2) ICC1 rising; VSINT = 13.5 V; I_PEAK_TH = ‘1’ P_6.3.19 VCC1 Active Peak Threshold 2 IVCC1,Ipeak2,f (Transition threshold between high-power and lowpower mode regulator) 5 – 15 mA 2) ICC1 falling; VSINT = 13.5V; I_PEAK_TH = ‘1’ P_6.3.20 Overcurrent Limitation 260 360 500 mA current following out of P_6.3.21 pin, VCC1= 0V 2) Datasheet Symbol IVCC1,lim Values 63 Number Normal Mode; 10 µA < P_6.3.1 IVCC1 < 150 mA; Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Voltage Regulator 1 Table 19 Electrical Characteristics (cont’d) VSINT = 5.5 V to 28 V; Tj = -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified). Parameter Symbol Min. Typ. Max. Unit Note or Test Condition Minimum Output Capacitance CVCC1,min for stability 13) – – µF 2) P_6.3.22 Maximum Output Capacitance – – 47 µF 2) P_6.3.23 CVCC1,max Values Number 1) In Stop Mode, the specified output voltage tolerance applies when IVCC1 has exceeded the selected active peak threshold (IVCC1,Ipeak1,r or IVCC1,Ipeak2,r) but with increased current consumption. 2) Not subject to production test, specified by design. 3) Value is meant to be an effective value at rated output voltage level. Datasheet 64 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC High-Side Switch 7 High-Side Switch 7.1 Block Description VS HSx HS Gate Control Overcurrent Detection Open Load (On) Figure 28 High-Side Module Block Diagram Features • All HSx supplied by VS • Under voltage switch off configurable via SPI. • Dedicated over voltage switch off per each HSx in Normal Mode- configurable via SPI. • Overvoltage switch off in Stop Mode and Sleep Mode- configurable via SPI. • Overcurrent detection and switch off. • Open load detection in ON-state. • PWM capability with internal or external timers configurable via SPI. • Switch recovery after removal of OV or UV condition configurable via SPI. 7.2 Functional Description The High-Side switches can be used for control of LEDs, as supply for the wake inputs and for other loads (except inductive load). The High-Side outputs can be controlled either directly via SPI by the integrated timers or by the integrated PWM generators or by external sync signal (using WK4/SYNC pin). The high-side outputs are supplied by VS pin. The topology supports improved cranking condition behavior. The configuration of the High-Sides (Permanent On, PWM, cyclic sense, etc.) drivers must be done in Normal Mode. The configuration is taken over in Stop Mode or Sleep Mode and cannot be modified. When entering Restart Mode or Fail-Safe Mode the HSx outputs are disabled. 7.2.1 Under Voltage Switch Off All HS drivers in on-state are switched off in case of under voltage on VS. The feature can be disabled by setting the SPI bit HS_UV_SD_DIS . Datasheet 65 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC High-Side Switch After release of under voltage condition, the HSx switch goes back to programmed state in which it was configured via SPI. This behavior is only valid if the bit HS_UV_REC is set. Otherwise the switches will stay off and the respective SPI control bits are cleared. The under voltage is signaled in the bit HS_UV, no other error bits are set. 7.2.2 Over Voltage Switch Off The HS drivers in on-state are switched off in case of over voltage on VS.. In Normal Mode the HSx can be kept in on-state above the VS overvoltage threshold if the HSx_OV_SDN_DIS bit is set. In Stop Mode or Sleep Modes all HS drivers can be kept in on-state if HS_OV_SDS_DIS bit is set. When the HSx are configured to switch off in case of over voltage condition, after release of over voltage condition, the HS switch goes back to programmed state in which it was configured via SPI. This behavior is only valid if the respective bit HSx_OV_REC is set. Otherwise the switch will stay off and the respective SPI control bits are cleared. This configuration is available for each HSx. The over voltage is signaled in the bit HS_OV, no other error bits are set. 7.2.3 Over Current Detection and Switch Off If the load current exceeds the over current shutdown threshold for a time longer then the over current shutdown filter time the output is switched off. The over current condition and the switch off is signaled with the respective HSx_OC_OT bit in the register HS_OL_OC_OT_STAT. The HSx configuration is then reset to 000 by the device. To activate the High-Side again the HSx configuration has to be set to ON (001) or be programmed to a timer function. It is recommended to clear the over current bit before activation the High-Side switch, as the bits are not cleared automatically by the device. 7.2.4 Open Load Detection Open load detection on the High-Side outputs is done during on state of the output. If the current in the activated output falls below the open load detection current threshold, the open load is detected and signaled via the respective bit HS1_OL, HS2_OL, HS3_OL, or HS4_OL in the register HS_OL_OC_OT_STAT. The HighSide output stays activated.. If the open load condition disappears the Open Load bit in the SPI can be cleared. The bits are not cleared automatically by the device. 7.2.5 PWM, Timer and SYNC Function Each integrated HSx can be configured in different ways, in particular: • Static OFF • Static ON • Timer 1 • Timer 2 • Internal generator PWM1 • Internal generator PWM2 • Internal generator PWM3 • Internal generator PWM4 • SYNC (via WK4) Note: Datasheet PWMx mentioned in this chapter refer to the internal PWM generators, which are configured by the registers HS_CTRL and PWM_CTRL. They can be used to control the internal high-side switches HSx. 66 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC High-Side Switch Note: PWMx mentioned in this chapter do not refer to the PWMx pins. The PWMx pins are used for the PWM operation of the bridge drivers, to control the external MOSFETs. Static configuration (ON/OFF) This configuration set the HSx permanently ON or OFF. This configuration is available in Normal Mode, Stop Mode and Sleep Mode. The configuration shall be done via SPI. Timer configuration (TIMER1 or TIMER2) Two Timers are dedicated to control the ON phase of dedicated HS outputs. The Timers are mapped to the dedicated HS outputs. Period and the duty cycle can be independently configured with via SPI. PWM configuration (PWM1..PWM4) Several internal PWM generators are dedicated to generate a PWM signal on the HSx output, e.g. for brightness adjustment or compensation of supply voltage fluctuation. The PWM generators are mapped to the dedicated HS outputs, and the duty cycle can be independently configured with a 10-bit resolution via SPI (PWM_CTRL). Two different frequencies can be selected independently for every PWM generator in the register PWM_CTRL. In order to assign and configure the PWMx to specific HSX, the follow steps have to be followed: • Configure duty cycle and frequency for respective PWM generator in PWM_CTRL. • Assign PWM generator to respective HS switch(es) in HSx_CTRL. • The PWM generation will start right after the HSx is assigned to the PWM generator (HS_CTRL) . Note: The min. on-time during PWM is limited by the actual on- and off-time of the respective HS switch, e.g. the PWM setting ‘00 0000 0001’ could not be realized. SYNC configuration (using WK4) Another possible configuration is to use the WK4 (set as SYNC pin) and mapped to one dedicated HSx output. The configuration of the WK4/SYNC bit is done using the WK_EN bits. If the WK_EN=10B (SYNC selected), all bits in WK4 bank are ignored and wake-up capability on WK4 is not available. Only after the WK4/SYNC configuration, the HSx can be configured for SYNC usage (HSx = 1000B). Datasheet 67 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC High-Side Switch 7.3 Table 20 Electrical Characteristics Electrical Characteristics VSINT = 5.5 V to 28 V; Tj = -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Min. Typ. Max. Unit Note or Test Condition Number Output HS1, HS2, HS3, HS4 Static Drain-Source ON Resistance HSx RON,HS25 – 7 – Ω Ids = 60 mA, Tj < 25°C P_7.3.1 Static Drain-Source ON Resistance HSx RON,HS150 – 11.5 16 Ω Ids = 60 mA, Tj < 150°C P_7.3.2 Leakage Current HSx / per channel Ileak,HS – – 2 µA 1) 0 V < VHSx < VS_HS; Tj < 85°C P_7.3.3 Output Slew Rate (rising) SRraise,HS 0.8 – 2.5 V/µs 1) 20 to 80% VS = 6 to 18 V RL = 220 Ω P_7.3.4 Output Slew Rate (falling) SRfall,HS -2.5 – -0.8 V/µs 1) 80 to 20% VS = 6 to 18 V RL = 220 Ω P_7.3.5 Switch-on time HSx tON,HS 3 – 30 µs CSN = HIGH to 0.8 × VS; RL = 220 Ω; VS = 6 to 18 V P_7.3.6 Switch-off time HSx tOFF,HS 3 – 30 µs CSN = HIGH to 0.2 × VS; RL = 220 Ω; VS = 6 to 18 V P_7.3.7 Short Circuit Shutdown Current ISD,HS 150 245 300 mA VS = 6 to 20 V P_7.3.8 Short Circuit Shutdown Filter Time tSD,HS 12 16 22 µs 2) P_7.3.9 Open Load Detection Current IOL,HS 0.4 – 2 mA hysteresis included P_7.3.10 Open Load Detection hysteresis IOL,HS,hys – 0.45 – mA 1) P_7.3.11 Open Load Detection Filter Time tOL,HS 160 220 270 µs 2) P_7.3.12 1) Not subject to production test, specified by design. 2) Not subject to production test, tolerance defined by internal oscillator tolerance. Datasheet 68 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC High Speed CAN Transceiver 8 High Speed CAN Transceiver 8.1 Block Description VCAN SPI Mode Control CANH CANL VCC1 RTD Driver Output Stage Temp.Protection TXDCAN + timeout To SPI diagnostic VCAN VCC 1 MUX RXDCAN Receiver Vs Wake Receiver Figure 29 Functional Block Diagram 8.2 Functional Description The Controller Area Network (CAN) transceiver part of the device provides High-Speed (HS) differential mode data transmission (up to 2 Mbaud/s) and reception in automotive and industrial applications. It works as an interface between the CAN protocol controller and the physical bus lines compatible to ISO11898-2:2016 and SAE J2284. The CAN FD transceiver offers low-power modes to reduce current consumption. This supports networks with partially powered down nodes. To support software diagnostic functions, a CAN Receive Only Mode is implemented. It is designed to provide excellent passive behavior when the transceiver is switched off (mixed networks, clamp 15/30 applications). A wake-up from the CAN Wake Capable Mode is possible via a message on the bus. Thus, the microcontroller can be powered down or idled and is woken up by the CAN bus activities. The CAN transceiver is designed to withstand the severe conditions of automotive applications and to support 12 V applications. Datasheet 69 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC High Speed CAN Transceiver The transceiver can also be configured to Wake Capable in order to save current and to ensure a safe transition from Normal Mode to Sleep Mode (to avoid loosing messages). Figure 30 shows the possible transceiver mode transition when changing the device mode. Device Mode CAN Transceiver Mode Stop Mode Receive Only Wake Capable Normal Mode OFF Normal Mode Receive Only Wake Capable Normal Mode OFF Sleep Mode Wake Capable OFF Restart Mode Woken1 OFF Fail-Safe Mode Wake Capable 1 after a wake event on CAN Bus Behavior after Restart Mode - not coming from Sleep Mode due to a wake up of the respective transceiver: If the transceivers had been configured to Normal Mode, or Receive Only Mode, then the mode will be changed to Wake Capable. If it was Wake Capable, then it will remain Wake Capable. If it had been OFF before Restart Mode, then it will remain OFF. Behavior in Software Development Mode: CAN default value in INIT MODE and entering Normal Mode from Init Mode is ON instead of OFF. Figure 30 CAN Mode Control Diagram CAN FD Support CAN FD stands for ‘CAN with Flexible Data Rate’. It is based on the well established CAN protocol as specified in ISO11898-2:2016. CAN FD still uses the CAN bus arbitration method. The benefit is that the bit rate can be increased by switching to a shorter bit time at the end of the arbitration process and then to return to the longer bit time at the CRC delimiter, before the receivers transmit their acknowledge bits. See also Figure 31. In addition, the effective data rate is increased by allowing longer data fields. CAN FD allows the transmission of up to 64 data bytes compared to the 8 data bytes from the standard CAN. Figure 31 Datasheet Standard CAN message CAN Header CAN FD with reduced bit time CAN Header Data phase (Byte 0 – Byte 7) Data phase (Byte 0 – Byte 7) CAN Footer CAN Footer Example: - 11bit identifier + 8Byte data - Arbitration Phase 500kbps - Data Phase 2Mbps à average bit rate 1.14Mbps Bit Rate Increase with CAN FD vs. Standard CAN 70 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC High Speed CAN Transceiver Not only the physical layer must support CAN FD but also the CAN controller. In case the CAN controller is not able to support CAN FD then the respective CAN node must at least tolerate CAN FD communication. This CAN FD tolerant mode is realized in the physical layer. 8.2.1 CAN OFF Mode The CAN OFF Mode is the default mode after power-up of the device. It is available in all device modes and is intended to completely stop CAN activities or when CAN communication is not needed. In CAN OFF Mode, a wake-up event on the bus will be ignored. 8.2.2 CAN Normal Mode The CAN Transceiver is enabled via SPI in Normal Mode. CAN Normal Mode is designed for normal data transmission/reception within the HS-CAN network. The mode is available in Normal Mode and in Stop Mode. The bus biasing is set to VCAN/2. Transmission The signal from the microcontroller is applied to the TXDCAN input of the device. The bus driver switches the CANH/L output stages to transfer this input signal to the CAN bus lines. Enabling sequence The CAN transceiver requires an enabling time tCAN,EN before a message can be sent on the bus. This means that the TXDCAN signal can only be pulled low after the enabling time. If this is not ensured, then the TXDCAN needs to be set back to high (=recessive) until the enabling time is completed. Only the next dominant bit will be transmitted on the bus. Figure 32 shows different scenarios and explanations for CAN enabling. VTXDCAN CAN Mode t CAN,EN t CAN ,EN t t CAN,EN CAN NORMAL CAN OFF t VCANDIFF Dominant Recessive Correct sequence , Bus is enabled after tCAN, EN Figure 32 tCAN, EN not ensured , no transmission on bus recessive TXDCAN level required bevor start of transmission tCAN, EN not ensured , no transmission on bus recessive TXDCAN level required t CAN Transceiver Enabling Sequence Reduced Electromagnetic Emission To reduce electromagnetic emissions (EME), the bus driver controls CANH/L slopes symmetrically. Reception Analog CAN bus signals are converted into digital signals at RXDCAN via the differential input receiver. 8.2.3 CAN Receive Only Mode In CAN Receive Only Mode (RX only), the driver stage is de-activated but reception is still operational. This mode is accessible by an SPI command in Normal Mode and in Stop Mode. Datasheet 71 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC High Speed CAN Transceiver Note: The transceiver is still properly working in CAN Receive Only Mode even if VCAN is not available because of an independent receiver supply. 8.2.4 CAN Wake Capable Mode This mode can be used in Stop Mode, Sleep Mode, Restart Mode and Normal Mode by programming via SPI and it is used to monitor bus activities. It is automatically accessed in Fail-Safe Mode. A wake-up signal on the bus results in a change of behavior of the device, as described in Table 21. As a signalization to the microcontroller, the RXDCAN pin is set low and will stay low until the CAN transceiver is changed to any other mode. After a wake-up event, the transceiver can be switched to CAN Normal Mode via SPI for bus communication. As shown in Figure 33, a wake-up pattern (WUP) is signaled on the bus by two consecutive dominant bus levels for at least tWake1 (wake-up time) and less than tWake2, each separated by a recessive bus level of greater than tWake1 and shorter than tWake2. Entering CAN wake capable Ini Bus recessive > tWAKE1 Bias off Wait Bias off Bus dominant > tWAKE1 optional: tWAKE2 expired 1 Bias off Bus recessive > tWAKE1 optional: tWAKE2 expired 2 Bias off Bus dominant > tWAKE1 Entering CAN Normal or CAN Recive Only Figure 33 3 Bias on CAN Wake-up Pattern Detection according to the Definition in ISO11898-2:2016 Rearming the Transceiver for Wake Capability After a BUS wake-up event, the transceiver is woken. However, the CAN transceiver mode bits will still show wake capable (=‘01’) so that the RXDCAN signal will be pulled low. There are two possibilities how the CAN transceiver’s wake capable mode is enabled again after a wake-up event: • The CAN transceiver mode must be toggled, i.e. switched from CAN Wake Capable Mode to CAN Normal Mode, CAN Receive Only Mode or CAN OFF Mode, before switching to CAN Wake Capable Mode again. • Rearming is done automatically when the device is changed to Stop Mode, Sleep Mode or Fail-Safe Mode to ensure wake-up capability. Datasheet 72 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC High Speed CAN Transceiver Wake-Up in Stop Mode and Normal Mode In Stop Mode, if a wake-up is detected, it is always signaled by the INTN output and in the WK_STAT SPI register. It is also signaled by RXDCAN pulled to low. The same applies for the Normal Mode. The microcontroller should set the device from Stop Mode to Normal Mode, there is no automatic transition to Normal Mode. For functional safety reasons, the watchdog will be automatically enabled in Stop Mode after a bus wake-up event in case it was disabled before (if bit WD_EN_ WK_BUS was configured to high before). Wake-Up in Sleep Mode Wake-up is possible via a CAN message. The wake-up automatically transfers the device into the Restart Mode and from there to Normal Mode the corresponding RXDCAN pin is set to low. The microcontroller is able to detect the low signal on RXDCAN and to read the wake source out of the WK_STAT register via SPI. No interrupt is generated when coming out of Sleep Mode. The microcontroller can now for example switch the CAN transceiver into CAN Normal Mode via SPI to start communication. Table 21 Action due to CAN Bus Wake-Up Mode Mode after Wake VCC1 INTN RXDCAN Normal Mode Normal Mode On Low Low Stop Mode Stop Mode On Low Low Sleep Mode Restart Mode Ramping Up High Low Restart Mode Restart Mode On High Low Fail-Safe Mode Restart Mode Ramping Up High Low 8.2.5 CAN Bus termination In accordance with the CAN configuration, four types of bus terminations are allow: • CAN Normal Mode: VCAN/2 termination. • CAN Receive Only Mode: VCAN/2 termination in case that VCAN is nominal supply. when VCAN UV is detected, the termination is 2.5 V. • CAN Wake Capable Mode: GND termination: after wake-up, the termination is 2.5 V. • CAN OFF Mode: no termination necessary (bus floating). When entering CAN Wake Capable Mode the termination is only connected to GND after the t_silence time has expired. 8.2.6 TXD Time-out Feature If the TXDCAN signal is dominant for a time t > tTXDCAN_TO, in CAN Normal Mode, the TXDCAN time-out function deactivates the transmission of the signal at the bus setting the TXDCAN pin to recessive. This is implemented to prevent the bus from being blocked permanently due to an error. The transmitter is disabled and thus switched to recessive state. The CAN SPI control bits (CAN on BUS_CTRL) remain unchanged and the failure is stored in the SPI flag CAN_FAIL. The CAN transmitter stage is activated again after the dominant time-out condition is removed and the transceiver is automatically switched back to CAN Normal Mode. 8.2.7 Bus Dominant Clamping If the CAN bus is dominant for a time t > tBUS_CAN_TO, when CAN is configured as CAN Normal Mode or CAN Receive Only Mode, a bus dominant clamping is detected and the SPI bit CAN_FAIL is set. The transceiver configuration stays unchanged. In order to avoid that a bus dominant clamping is detected due to a TXD timeout the bus dominant clamping filter time tBUS_CAN_TO > tTXDCAN_TO. Datasheet 73 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC High Speed CAN Transceiver 8.2.8 Undervoltage Detection The voltage at the CAN supply pin is monitored in CAN Normal Mode and CAN Receive Only Mode. In case of VCAN undervoltage a signalization via SPI bit VCAN_UV is triggered and the TLE9563-3QX disables the transmitter stage. If the CAN supply reaches a higher level than the undervoltage detection threshold (VCAN > VCAN_UV), the transceiver is automatically switched back to CAN Normal Mode. The undervoltage detection is enabled if the mode bit CAN_1 = ‘1’, i.e. in CAN Normal or CAN Receive Only Mode. . 8.3 Electrical Characteristics Table 22 Electrical Characteristics Tj = -40°C to +150°C; VSINT = 5.5 V to 28 V; VCAN = 4.75 V to 5.25 V; RL = 60 Ω; CAN Normal Mode; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. Differential Receiver Vdiff,rd_N Threshold Voltage, recessive to dominant edge – 0.80 0.90 V Vdiff = VCANH - VCANL; -12 V ≤ VCM(CAN) ≤ 12 V; CAN Normal Mode P_8.3.1 Differential Receiver Vdiff,dr_N Threshold Voltage, dominant to recessive edge 0.50 0.60 – V Vdiff = VCANH -VCANL; -12 V ≤ VCM(CAN) ≤ 12 V; CAN Normal Mode P_8.3.2 Dominant state differential input voltage range Vdiff_D_range 0.9 – 8.0 V Vdiff = VCANH - VCANL; -12 V ≤ VCM(CAN) ≤ +12 V; CAN Normal Mode P_8.3.60 Common Mode Range CMR -12 – 12 V 4) P_8.3.3 Recessive state differential input voltage range Vdiff_R_range -3.0 – 0.5 V Vdiff = VCANH - VCANL; -12 V ≤ VCM(CAN) ≤ +12 V; CAN Normal Mode P_8.3.61 Maximum Differential Bus Voltage Vdiff,max -5 – 10 V 4) P_8.3.4 CANH, CANL Input Resistance Ri 20 40 50 kΩ CAN Normal / Wake Capable Mode; Recessive state -2V ≤ VCANH/L ≤ +7V P_8.3.5 Differential Input Resistance Rdiff 40 80 100 kΩ CAN Normal / Wake Capable Mode; Recessive state -2V ≤ VCANH/L ≤ +7V P_8.3.6 Input Resistance Deviation between CANH and CANL -3 – 3 % 4) P_8.3.7 CAN Bus Receiver Datasheet DRi 74 Recessive state VCANH = VCANL = 5V Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC High Speed CAN Transceiver Table 22 Electrical Characteristics (cont’d) Tj = -40°C to +150°C; VSINT = 5.5 V to 28 V; VCAN = 4.75 V to 5.25 V; RL = 60 Ω; CAN Normal Mode; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Min. Typ. Max. Unit Note or Test Condition Number Input Capacitance CANH, CANL versus GND Cin – 20 40 pF 1) P_8.3.8 Differential Input Capacitance Cdiff – 10 20 pF 1) P_8.3.9 Vdiff, rd_W Wake-up Receiver Threshold Voltage, recessive to dominant edge – 0.8 1.15 V -12 V ≤ VCM(CAN) ≤ 12 V; CAN Wake Capable Mode P_8.3.10 Wake-up Receiver Dominant Vdiff,D_range_ state differential input W voltage range 1.15 – 8.0 V -12 V ≤ VCM(CAN) ≤ +12 V; CAN Wake Capable Mode P_8.3.62 Wake-up Receiver Vdiff, dr_W Threshold Voltage, dominant to recessive edge 0.4 0.7 V -12 V ≤ VCM(CAN) ≤ 12 V; CAN Wake Capable Mode P_8.3.11 Wake-up Receiver Recessive Vdiff,R_range_W -3.0 state differential input voltage range VTXDCAN = 5 V VTXDCAN = 5 V – 0.4 V -12 V ≤ VCM(CAN) ≤ +12 V; CAN Wake Capable Mode P_8.3.63 CAN Bus Transmitter CANH/CANL Recessive Output Voltage (CAN Normal Mode) VCANL/H_NM 2.0 – 3.0 V CAN Normal Mode VTXDCAN = Vcc1; no load P_8.3.12 CANH/CANL Recessive Output Voltage (CAN Wake Capable Mode) VCANL/H_LP -0.1 – 0.1 V CAN Wake Capable Mode; VTXDCAN = Vcc1; no load P_8.3.13 CANH, CANL Recessive Output Voltage Difference Vdiff = VCANH - VCANL (CAN Normal Mode) Vdiff_r_N -500 – 50 mV CAN Normal Mode; VTXDCAN = Vcc1; no load P_8.3.14 CANH, CANL Recessive Output Voltage Difference Vdiff = VCANH - VCANL (CAN Wake Capable Mode) Vdiff_r_W -200 – 200 mV CAN Wake Capable Mode; VTXDCAN = Vcc1; no load P_8.3.15 CANL Dominant Output Voltage VCANL 0.5 – 2.25 V 4) P_8.3.16 Datasheet 75 CAN Normal Mode; VTXDCAN = 0 V; VCAN = 5 V; 50 Ω ≤ RL ≤ 65 Ω Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC High Speed CAN Transceiver Table 22 Electrical Characteristics (cont’d) Tj = -40°C to +150°C; VSINT = 5.5 V to 28 V; VCAN = 4.75 V to 5.25 V; RL = 60 Ω; CAN Normal Mode; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Min. Typ. Max. Unit Note or Test Condition Number CANH Dominant Output Voltage VCANH 2.75 – 4.5 V 4) CAN Normal Mode; VTXDCAN = 0 V; VCAN = 5 V; 50 Ω ≤ RL ≤ 65 Ω P_8.3.17 CANH, CANL Dominant Output Voltage Difference Vdiff = VCANH - VCANL Vdiff_d_N 1.5 2.0 2.5 V 4) CAN Normal Mode; VTXDCAN = 0 V; VCAN = 5 V; 50 Ω ≤ RL ≤ 65 Ω P_8.3.18 CANH, CANL Dominant Output Voltage Difference (resistance during arbitration) Vdiff = VCANH - VCANL Vdiff_d_N 1.5 – 5.0 V 4) CAN Normal Mode; P_8.3.19 VTXDCAN = 0 V; VCAN = 5 V; RL = 2240 Ω CANH, CANL output voltage Vdiff_slope_rd difference slope, recessive to dominant – – 70 V/us 4) P_8.3.54 30% to 70% of measured differential bus voltage, CL = 100 pF, RL = 60 Ω CANH, CANL output voltage Vdiff_slope_dr difference slope, dominant to recessive – – 70 V/us 4) P_8.3.55 70% to 30% of measured differential bus voltage, CL = 100 pF, RL = 60 Ω Driver Symmetry VSYM = VCANH + VCANL VSYM 4.5 – 5.5 V 2) CAN Normal Mode; P_8.3.21 VTXDCAN = 0 V / 5 V; VCAN = 5 V; CSPLIT = 4.7 nF; 50 Ω ≤ RL ≤ 60 Ω; CANH Short Circuit Current ICANHsc -115 -80 -50 mA CAN Normal Mode; VCANHshort = -3 V P_8.3.22 CANL Short Circuit Current ICANLsc 50 80 115 mA CAN Normal Mode; VCANLshort = 18 V; P_8.3.23 Leakage Current ICANH,lk ICANL,lk – 5 7.5 µA VS = VCAN = 0 V; 0 V ≤ VCANH,L ≤ 5 V; 3) Rtest = 0 / 47kΩ P_8.3.24 High level Output Voltage VRXDCAN,H 0.8 × VCC1 – – V CAN Normal Mode; IRXDCAN = -2 mA P_8.3.26 Low Level Output Voltage VRXDCAN,L – – 0.2 × Vcc1 V CAN Normal Mode; IRXDCAN = 2 mA P_8.3.27 Receiver Output RXDCAN Datasheet 76 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC High Speed CAN Transceiver Table 22 Electrical Characteristics (cont’d) Tj = -40°C to +150°C; VSINT = 5.5 V to 28 V; VCAN = 4.75 V to 5.25 V; RL = 60 Ω; CAN Normal Mode; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Min. Typ. Max. Unit Note or Test Condition Number Transmission Input TXDCAN High Level Input Voltage Threshold VTXDCAN,H – – 0.7 × Vcc1 V CAN Normal Mode; recessive state P_8.3.28 Low Level Input Voltage Threshold VTXDCAN,L 0.3 × Vcc1 – – V CAN Normal Mode; dominant state P_8.3.29 TXDCAN Input Hysteresis VTXDCAN,hys – 0.12 × Vcc1 – V 4) P_8.3.30 TXDCAN Pull-up Resistance RTXDCAN 20 50 80 kΩ - P_8.3.31 pF 4) P_8.3.64 6) TXDCAN input capacitance CAN Transceiver Enabling Time CTXDCAN tCAN,EN – 8 6 10 12 18 µs CSN = high to first valid transmitted TXDCAN dominant P_8.3.32 Dynamic CAN-Transceiver Characteristics Min. Dominant Time for Bus tWake1 Wake-up 0.5 – 1.8 µs -12 V ≤ VCM(CAN) ≤ 12 V; CAN Wake Capable Mode P_8.3.33 Wake-up Time-out, Recessive Bus tWake2 0.8 – 10 ms 6) CAN Wake Capable Mode P_8.3.34 Loop delay (recessive to dominant) tLOOP,f – 150 255 ns 2) CAN Normal Mode; CL = 100 pF; RL = 60 Ω; VCAN = 5 V; CRXDCAN = 15 pF P_8.3.35 Loop delay (dominant to recessive) tLOOP,r – 150 255 ns 2) CAN Normal Mode; CL = 100 pF; RL = 60 Ω; VCAN = 5 V; CRXDCAN = 15 pF P_8.3.36 Propagation Delay TXDCAN low to bus dominant td(L),T – 50 140 ns CAN Normal Mode; CL = 100 pF; RL = 60 Ω; VCAN = 5 V P_8.3.37 Propagation Delay TXDCAN high to bus recessive td(H),T – 50 140 ns CAN Normal Mode; CL = 100 pF; RL = 60 Ω; VCAN = 5 V P_8.3.38 Datasheet 77 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC High Speed CAN Transceiver Table 22 Electrical Characteristics (cont’d) Tj = -40°C to +150°C; VSINT = 5.5 V to 28 V; VCAN = 4.75 V to 5.25 V; RL = 60 Ω; CAN Normal Mode; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Min. Typ. Max. Unit Note or Test Condition Number Propagation Delay bus dominant to RXDCAN low td(L),R – 100 – ns CAN Normal Mode; CL = 100 pF; RL = 60 Ω; VCAN = 5 V; CRXDCAN = 15 pF P_8.3.39 Propagation Delay bus recessive to RXDCAN high td(H),R – 100 – ns CAN Normal Mode; CL = 100 pF; RL = 60 Ω; VCAN = 5 V; CRXDCAN = 15 pF P_8.3.40 Received Recessive bit width tbit(RXD) 400 – 550 ns P_8.3.42 CAN Normal Mode; CL = 100 pF; RL = 60 Ω ; VCAN = 5 V; CRXDCAN = 15 pF; tbit(TXD) = 500 ns; Parameter definition in according to Figure 35. Transmitted Recessive bit width 435 – 530 ns P_8.3.43 CAN Normal Mode; CL = 100 pF; RL = 60 Ω; VCAN = 5 V; CRXDCAN = 15 pF; tbit(TXD) = 500 ns; Parameter definition in according to Figure 35. -65 – 40 ns P_8.3.44 CAN Normal Mode; CL = 100 pF; RL = 60 Ω; VCAN = 5 V; CRXDCAN = 15 pF; tbit(TXD) = 500 ns; Parameter definition in according to Figure 35. tbit(BUS) Receiver timing symmetry5) ∆tRec Datasheet 78 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC High Speed CAN Transceiver Table 22 Electrical Characteristics (cont’d) Tj = -40°C to +150°C; VSINT = 5.5 V to 28 V; VCAN = 4.75 V to 5.25 V; RL = 60 Ω; CAN Normal Mode; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. Received Recessive bit width tbit(RXD) 120 – 220 ns P_8.3.45 CAN Normal Mode; CL = 100 pF; RL = 60 Ω ; VCAN = 5 V; CRXDCAN = 15 pF; tbit(TXD) = 200 ns; Parameter definition in according to Figure 35. Transmitted Recessive bit width 155 – 210 ns P_8.3.46 CAN Normal Mode; CL = 100 pF; RL = 60 Ω; VCAN = 5 V; CRXDCAN = 15 pF; tbit(TXD) = 200 ns; Parameter definition in according to Figure 35. Receiver timing symmetry ∆t ∆tRec Rec = t_bit(RXD) - t_bit(Bus) -45 – 15 ns P_8.3.47 CAN Normal Mode; CL = 100 pF; RL = 60 Ω; VCAN = 5 V; CRXDCAN = 15 pF; tbit(TXD) = 200 ns; Parameter definition in according to Figure 35. TXDCAN Permanent Dominant Time-out tTXDCAN_TO 1.6 2.0 2.4 ms 6) P_8.3.48 BUS Permanent Dominant Time-out tBUS_CAN_TO 2.0 2.5 3.0 ms 6) P_8.3.49 Timeout for bus inactivity tSILENCE 0.6 – 1.2 s 6) P_8.3.50 µs 6) P_8.3.51 Bus Bias reaction time tbit(BUS) tBias – – 250 CAN Normal Mode CAN Normal Mode 1) Not subject to production test, specified by design, S2P - Method; f = 10 MHz 2) VSYM shall be observed during dominant and recessive state and also during the transition dominant to recessive and vice versa while TXD is simulated by a square signal (50% duty cycle) with a frequency of up to 1 MHz (2MBit/s). 3) Rtests between (Vs /VCAN) and 0V (GND). 4) Not subject to production test, specified by design. 5) ∆tRec = tbit(RXD) - tbit(BUS). 6) Not subject to production test, tolerance defined by internal oscillator tolerance. Datasheet 79 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC High Speed CAN Transceiver VTXDCAN Vcc1 GND V DIFF t d(L),T V diff, rd_N V diff, dr_N t d (L),R VRXDCAN Vcc1 t t d(H),T t t d (H),R t LOOP,f tLOOP,r 0.8 x Vcc1 0.2 x Vcc1 GND Figure 34 Timing Diagrams for Dynamic Characteristics 70% TXDCAN 30% 5x tBit(TXD) tBit(TXD) Vdiff=CANH-CANL 500mV tLoop_f 900mV tBit(Bus) 70% RXDCAN 30% tLoop_r Figure 35 Datasheet tBit(RXD) From ISO11898-2:2016: tloop, tbit(TXD), tbit(Bus), tbit(RXD) definitions 80 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC High-Voltage Wake Input 9 High-Voltage Wake Input 9.1 Block Description Internal Supply IPU_WK + WKx IPD_WK t WK VRef Logic Figure 36 Wake Input Block Diagram Features • High-Voltage inputs with a 3 V (typ.) threshold voltage except WK5 (0.5 × VS). • Wake-up capability for power saving modes. • Edge sensitive wake feature low to high and high to low. • Pull-up and Pull-down current sources except for WK5 (pull-up fixed), configurable via SPI. • Selectable configuration for static sense or cyclic sense. • In Normal Mode and Stop Mode the level of the WKx pin can be read via SPI unless WK4 is configured as SYNC. • Synchronization with HSx via WK4 (for cyclic sense). Datasheet 81 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC High-Voltage Wake Input 9.2 High-Voltage Wake Function 9.2.1 Functional Description The wake inputs pin are edge-sensitive inputs with a switching threshold of typically 3 V except WK5. Both transitions, high to low and low to high, result in a signalization by the device. The signalization occurs either in triggering the interrupt in Normal Mode and Stop Mode or by a wake up of the device in Sleep Mode and FailSafe Mode. Two different wake detection modes can be selected via SPI: • Static sense: WK inputs are always active. • Cyclic sense: WK inputs are only active for a certain time period (see Chapter 5.7.1). A filter time tFWKx is implemented to avoid an unintentional wake-up due to transients or EMC disturbances in static sense configuration. The filter time (tFWKx) is triggered by a level change crossing the switching threshold and a wake signal is recognized if the input level will not cross again the threshold during the selected filter time. Figure 37 shows a typical wake-up timing and filtering of transient pulses. VWKx VWKTh,f VWKth,f t VINTN tFWK tFWK tINTN t No Wake Event Figure 37 Wake Event Wake-up Filter Timing for Static Sense The wake-up capability for the WKx pin can be enabled or disabled via SPI command. A wake event via the WKx pin can always be read in the register WK_STAT at the bit WK5_WU. The actual voltage level of the WKx pin (low or high) can always be read in Normal Mode, Stop Mode and Init Mode in the register WK_LVL_STAT. During Cyclic Sense, the register shows the sampled levels of the respective WKx pin. 9.2.2 Wake Input Configuration To ensure a defined and stable voltage levels at the internal comparator input it is possible to configure integrated current sources via the SPI register WK_CTRL. Datasheet 82 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC High-Voltage Wake Input Table 23 Pull-Up / Pull-Down Resistor (not valid for WK5) WKx_PUPD_ WKx_PUPD_ Current Sources Note 1 0 0 0 no current source WK input is floating if left open (default setting) 0 1 pull-down WK input internally pulled to GND 1 0 pull-up WK input internally pulled to internal 5V supply 1 1 Automatic switching If a high level is detected at the WK input the pull-up source is activated, if low level is detected the pull down is activated. Note: If a WK input is not used, the respective WK input must be tied to GND on board to avoid unintended floating state of the pin. One additional configuration is related the filter time of each Wake-up module. The bits WK_FILT permit to set the filter time in static sensing or in cyclic sensing. Note: When the device mode is changed to normal (from INIT), in case of static sense, if the WK pin is set, the WK_STAT register is set in this time (also the interrupt pin). 9.2.3 Wake configuration for Cyclic Sense The wake-up inputs can also be used for cyclical sensing signals during low-power modes. For this function the WKx input performs a cyclic sensing of the voltage level during the on-time of specific HSx. A transition of the voltage level will trigger a wake-up event. See also Chapter 5.7.1 for more details. 9.2.4 Wake configuration for Synchronization The WK4 pin can be configured as SYNC input for driving the HSx. Prerequisite to configure the WK4 as SYNC input is that the WK4 has to be OFF. The configuration of the WK4/SYNC bit is done using the WK_EN bits. if the WK_EN=10B (SYNC selected), all bits in WK4 bank are ignored and wake-up capability on WK4 is not available. Note: Datasheet If WKx is the only wake source available and is configured with cyclic sense with SYNC (WKx_FILT = 100), trying to go to Sleep Mode is not possible (restart mode is entered) because SYNC is driven by the microcontroller which is not supplied in Sleep Mode. 83 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC High-Voltage Wake Input 9.3 Electrical Characteristics Table 24 Electrical Characteristics VSINT = 5.5 V to 28 V; Tj = -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Min. Typ. Max. Unit Note or Test Condition Number WK4 Input Pin Characteristics Wake-up/monitoring threshold voltage falling VWKx_th,f 2.5 3 3.5 V without external serial resistor RS P_10.3.1 Wake-up/monitoring threshold voltage rising VWKx_th,r 3 3.5 4 V without external serial resistor RS P_10.3.2 Threshold hysteresis VWKx_th,hys 0.4 0.6 0.85 V without external serial resistor RS P_10.3.3 WK pin Pull-up Current IPU_WKx -20 -10 -3 µA VWKx = 4 V P_10.3.4 WK pin Pull-down Current IPD_WKx 3 10 20 µA VWKx = 2.5 V P_10.3.5 Input leakage current ILK,lx -2 2 µA 0 V < VWKx < 40 V; Pull-up / Pull-down disabled P_10.3.6 WK5 Input Pin Characteristics Wake-up/monitoring threshold voltage falling VWK5_th,f 0.4 x VS 0.45 x VS - V P_10.3.7 Wake-up/monitoring threshold voltage rising VWK5_th,r - 0.6 x VS V P_10.3.8 Threshold hysteresis VWK5_th,hy 0.07 × VS s 0.1 × VS 0.175 × V VS P_10.3.9 Pull-up resistance on WK5 RWK5,pull- 30 47 kΩ P_10.3.10 20 0.55 x VS up WK4 as SYNC input pin LOW input voltage threshold WK4SYNC_ 0.3 × VCC1 th,L - - V P_10.3.11 HIGH input voltage threshold WK4SYNC_ - - 0.7 × VCC1 V P_10.3.12 Pull-down resistance on WK/SYNC th,H RSYNC 20 40 80 kΩ VSYNC = 1 V P_10.3.13 tFWK1 12 16 22 µs 1) P_10.3.16 µs 1) P_10.3.17 Timing Wake-up filter time 1 Wake-up filter time 2 tFWK2 50 64 80 1) Not subject to production test, tolerance defined by internal oscillator tolerance. Datasheet 84 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Interrupt Function 10 Interrupt Function 10.1 Block and Functional Description Vcc1 Interrupt logic Time out INTN INTERRUPT BLOCK.VSD Figure 38 Interrupt Block Diagram The interrupt is used to signalize special events in real time to the microcontroller. The interrupt block is designed as a push/pull output stage as shown in Figure 38. An interrupt is triggered and the INTN pin is pulled low (active low) for tINTN in Normal Mode and Stop Mode and it is released again once tINTN is expired. The minimum high-time of INTN between two consecutive interrupts is tINTND. An interrupt does not cause a device mode change. Two different interrupt generation methods are implemented: • Interrupt Mask: One dedicated register (INT_MASK) is intended to enable or disable set of interrupt sources. The interrupt sources follow the SPI Status Information Field. In details: – SUPPLY_STAT: “OR” of all bits on SUP_STAT register except POR, VCC1_UV, VCC1_SC, VCC1_OV – TEMP_STAT: “OR” of all bits on THERM_STAT register except TSD2 – BUS_STAT: “OR” of all bits on BUS_STAT register – HS_STAT: “OR” of all bits on HS_OL_OC_OT_STAT register – BD_STAT: “OR” of all bits on DSOV register – SPI_CRC_FAIL: or between SPI_FAIL and CRC_FAIL bits on DEV_STAT register. • Wake-up events: all wake-up events stored in the wake status SPI register WK_STAT only in case the corresponding input was configured as wake-up source. The wake-up sources are: – via CAN (wake-up pattern or wake-up frame) – via WK pin – via TIMERx (cyclic wake) – via LSx_DSOV_BRK if any of the brake-feature is enabled The methods are both available at the same time. Note: Datasheet The errors which will cause Restart or Fail-Safe Mode (VCC1_UV, VCC1_SC, VCC1_OV, TSD2) are the exceptions of an INTN generation. Also the bit POR will not generate interrupts. If the above mentioned bits are not cleared after the device is back in Normal Mode or Stop Mode, the INTN is periodically generated (Register based cyclic interrupt generation). 85 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Interrupt Function Note: Periodical interrupts are only generated by CRC fail and SPI fail from DEV_STAT register. Note: During Restart Mode the SPI is blocked and the microcontroller is in reset. Therefore the INTN will not be in Restart Mode, which is the same behavior in Fail-Safe Mode or Sleep Mode. In addition to this behavior, INTN will be triggered when Stop Mode is entered and not all wake source bits were cleared in the WK_STAT register and also the LSx_DSOV_BRK bits in the DSOV register.. The SPI status registers are updated at every falling edge of the INTN pulse. All interrupt events are stored in the respective register until the register is cleared via SPI command. A second SPI read after reading out the respective status register is optional but recommended to verify that the interrupt event is not present anymore. The interrupt behavior is shown in Figure 39. The INTN pin is also used during Init Mode to select the Software Development Mode entry. See Chapter 5.2 for further information. In case of pending INTN event (SPI Status registers are not cleared after INTN event), additional periodical INTN events are generated as shown in Figure 40. The periodical INTN events generation can be disabled via SPI command using INTN_CYC_EN bit. WKx CAN INTN tINTD tINTN Scenario 1 SPI Read & Clear Scenario 2 Update of WK_STAT register SPI Read & Clear WK_STAT contents Update of WK_STAT register optional WKx no WK CAN no WK WK + CAN no WK No SPI Read & Clear Command sent Figure 39 Interrupt Signalization Behavior Note: For two or more interrupt events at the same time, when INTN pin is low the same time, it will not start multiple toggling. Datasheet 86 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Interrupt Function WKx INTN tINTN tINTN_PULSE tINTN tINTN_PULSE Update of WK_STAT register SPI Read & Clear No SPI Read & Clear Command sent No SPI Read & Clear Command sent WK_STAT contents WKx WKx Figure 40 Datasheet Interrupt Signalization Behavior in case of pending INTN events 87 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Interrupt Function 10.2 Electrical Characteristics Table 25 Electrical Characteristics VSINT = 5.5 V to 28 V; Tj = -40°C to +150°C; Normal Mode; all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified. Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. INTN High Output Voltage VINTN,H 0.8 × VCC1 – – V 1) IINTN = -2 mA; INTN = off P_11.2.1 INTN Low Output Voltage VINTN,L – – 0.2 × VCC1 V 1) IINTN = 2mA; INTN = on P_11.2.2 INTN Pulse Width 80 100 120 µs 2) P_11.2.3 Interrupt Output; Pin INTN tINTN INTN Pulse Minimum Delay Time tINTND Pulse in case of pending INTN tINTN_PUL 4 80 100 120 µs 2) between consecutive pulses P_11.2.4 5 6 ms 2) between consecutive pulses P_11.2.5 60 100 kΩ VINTN = 5 V P_11.2.6 µs 2) P_11.2.7 SE SDM Select; Pin INTN Config Pull-up Resistance RSDM Config Select Filter Time tSDM_F 30 50 64 80 1) Output Voltage Value also determines device configuration during Init Mode. 2) Not subject to production test, tolerance defined by internal oscillator tolerance. Datasheet 88 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Gate Drivers 11 Gate Drivers The TLE9563-3QX integrates six floating gate drivers capable of controlling a wide range of N-channel MOSFETs. They are configured as three high-sides and three low-sides, building three half-bridges. VCP VS GHx VDSMONTH IPDDIAG Current-Steering DACs ISINK_BRAKE IPUDIAG Highside Gate-Driver SHx Logic High-Speed Comparators VCP GLx Lowside Gate-Driver VDSMONTH Current-Steering DACs Figure 41 SL Half-bridge gate driver - Block diagram This section describes the MOSFET control in static activation and during PWM operation. Note: PWMx mentioned in this chapter refer to the PWMx pins and signal used by the bridge driver to control the external MOSFETs. Note: In this chapter PWMx do not refer to the internal PWM generators used to control the internal highside switches HSx. 11.1 MOSFET control Depending on the configuration bits HBxMODE[1:0] (refer to HBMODE), CPEN, each high-side and low-side MOSFETs can be: Datasheet 89 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Gate Drivers • Kept off with the passive discharge. • Kept off actively. • Activated (statically, no PWM, HBx_PWM_EN = 0). • Activated in PWM mode (HBx_PWM_EN = 1). Refer to Table 26 for details. Table 26 Half-bridge mode selection CPEN HBxMODE[1:0]1) Configuration of HSx/LSx1) CPEN = 0 Don’t care All MOSFETs are kept off by the passive discharge CPEN = 1 00B HBx MOSFETs are kept off by the passive discharge CPEN = 1 01B LSx MOSFET is ON, HSx MOSFET is actively kept OFF CPEN = 1 10B HSx MOSFET is ON, LSx MOSFET is actively kept OFF CPEN = 1 11B LSx and HSx MOSFETs are actively kept OFF with IHOLD 1) x = 1 … 3 11.2 Static activation In this section, we consider the static activation of the high-side and low-side MOSFET of the half-bridge x: HBx_PWM_EN= 0 (in ST_ICHG) and CPEN = 1. The low-side or high-side MOSFET of HBx is statically activated (no PWM) by setting HBxMODE[1:0] to respectively (0,1) or (1,0). The configured active cross-current protection and the Drain-Source overvoltage blank times for the HalfBridge x are noted tHBxCCP ACTIVE and tHBxBLANK ACTIVE. The charge and discharge currents applied to the static controlled Half-Bridge x are noted ICHGSTx (ST_ICHG). IHARDOFF is the maximum current that the gate drivers can sink (150 mA typ.). This current is used to keep a MOSFET off, when the opposite MOSFET of the same half-bridge is being turned on. This feature reduces the risk of parasitic cross-current conduction. ICHGSTx is the current sourced, respectively sunk, by the gate driver to turn-on the high-side x or low-side x. ICHGSTx is configured in the control register ST_ICHG. Table 27 Static charge currents ICHGSTx[3:0] Nom. charge current [mA] Nom. discharge current [mA] Max. deviation to typ. values 0000B 0.5 (ICHG0) 0.5 (IDCHG0) +/- 60% 0001B 1.8 (ICHG4) 1.8 (IDCHG4) +/- 60 % 0010B 4.7 (ICHG8) 4.7 (IDCHG8) +/- 60 % 0011B 9.4 (ICHG12) 9.4 (IDCHG12) +/- 60 % 0100B 15.3 (ICHG16) 15.1 (IDCHG16) +/- 40 % 0101B 23 (ICHG20) 22.5 (IDCHG20) +/- 40 % Datasheet 90 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Gate Drivers Table 27 Static charge currents (cont’d) ICHGSTx[3:0] Nom. charge current [mA] Nom. discharge current [mA] Max. deviation to typ. values 0110B 31.6 (ICHG24) 30.9 (IDCHG24) +/- 40 % 0111B 41.6 (ICHG28) 40.8 (IDCHG28) +/- 40% 1000B 52.5 (ICHG32) 51.5 (IDCHG32) +/- 30 % 1001B 63.6 (ICHG36) 62.4 (IDCHG36) +/- 30 % 1010B 75.2 (ICHG40) 73.7 (IDCHG40) +/- 30 % 1011B 87.1 (ICHG44) 85.5 (IDCHG44) +/- 30 % 1100B 99.5 (ICHG48) 97.7 (IDCHG48) +/- 30 % 1101B 112.2 (ICHG52) 110.8 (IDCHG52) +/- 30 % 1110B 125.3 (ICHG56) 124.5 (IDCHG56) +/- 30 % 1111B 139 (ICHG60) 138.7 (IDCHG60) +/- 30 % IHOLD is the hold current used to keep the gate of the external MOSFETs in the desired state. This parameter is configurable with the IHOLD control bit in GENCTRL. If the control bit IHOLD = 0: • A MOSFET is kept ON with the current ICHG15. • A MOSFET is kept OFF with the current IDCHG15. If the control bit IHOLD = 1: • A MOSFET is kept ON with the current ICHG20. • A MOSFET is kept OFF with the current IDCHG20. 11.2.1 Static activation of a high-side MOSFET Turn-on with cross-current protection If LSx is ON (HBxMODE[1:0] = 01B), before the activation of HSx (HBxMODE[1:0] = 10B) then the high-side MOSFET is turned on after a cross-current protection time (refer to Figure 42): • After the CSN rising edge and for the duration tHBxCCP ACTIVE : – The high-side MOSFET is kept OFF with the current -ICHGSTx. – The gate of the low-side MOSFET is discharged with the current -ICHGSTx. • At the end of tHBxCCP ACTIVE and for the duration tHBxBLANK ACTIVE + tFVDS: – The gate of the high-side MOSFET is charged with the current ICHGSTx. – Low-side MOSFET is kept OFF with the current -IHARDOFF (hard off phase). • At the end of tFVDS: – The drive current of the high-side MOSFET is reduced to IHOLD. – The drive current of the low-side MOSFET is set to -IHOLD. Datasheet 91 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Gate Drivers CSN Previous State HSx OFF LSx ON SPI Frame accepted Turn on HSx New State HSx ON LSx OFF à à à t VS tHBxCCP Active IGHx HSx GHx ICHGSTx tHBxBLANK Active 0 t IGHx HSx internal drive signal SHx LSx GLx SL tFVDS IGLx ICHGSTx IHOLD -IHOLD t -ICHGSTx IGLx t -ICHGSTx LSx internal drive signal IHOLD -IHOLD t -ICHGSTx Hard off -IHARDOFF Figure 42 Note: Datasheet Turn-on of a high-side MOSFET with cross-current protection The CSN rising edge must be synchronized with the device logic. Therefore SPI commands are executed with a delay of up to 3 µs after the CSN rising edge. 92 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Gate Drivers Turn-on without cross-current protection If LSx is OFF (HBxMODE[1:0] = 11B), before the activation of HSx (HBxMODE[1:0] = 10B), then the high-side MOSFET is turned on without cross-current protection (refer to Figure 43): • right after the CSN rising edge and for a duration tHBxBLANK ACTIVE + tFVDS: – The gate of the high-side MOSFET is charged with the current ICHGSTx. – The low-side MOSFET is kept OFF with the current -IHARDOFF. • At the end of tFVDS: – The drive current of the high-side MOSFET is reduced to IHOLD. – The drive current of the low-side MOSFET is set to -IHOLD. SPI Frame accepted Turn on HSx Previous State HSx OFF LSx OFF à à à CSN New State HSx ON LSx OFF t tHBxBLANK Active IGHx tFVDS ICHGSTx 0 t HSx internal drive signal VS HSx ICHGSTx IHOLD -IHOLD t GHx IGHx IGLx SHx 0 t LSx GLx SL IGLx LSx internal drive signal IHOLD -IHOLD t Hard off -IHARDOFF Figure 43 Note: Datasheet Turn-on of a high-side MOSFET without cross-current protection The CSN rising edge must be synchronized with the device logic. Therefore SPI commands are executed with a delay of up to 3 µs after the CSN rising edge. 93 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Gate Drivers 11.2.2 Static activation of a low-side MOSFET The description of the static activation of a low-side x differs from the description of Chapter 11.2.1 only by exchanging high-side x and low-side x. 11.2.3 Turn-off of the high-side and low-side MOSFETs of a half-bridge When the TLE9563-3QX receives a SPI command to turn-off both the high-side and low-side MOSFETs of the half-bridge x (HBxMODE[1:0] = (0,0) or (1,1)): • The gate of HSx and LSx are discharged with the current -ICHGSTx for the duration tHBxCCP ACTIVE (Figure 44). • At the end of tHBxCCP ACTIVE, the drive current of HSx and LSx are reduced to -IHOLD. SPI Frame accepted Turn off HSx and LSx VS CSN HSx t GHx IGHx IGHx SHx LSx GLx SL 0 t -ICHGSTx IGLx HSx internal drive signal IHOLD -IHOLD tHBxCCP Active t -ICHGSTx IGLx t LSx internal drive signal -IHOLD t -ICHGSTx Figure 44 Note: Datasheet Turn-off of the high-side and low-side MOSFETs of a half-bridge The CSN rising edge must be synchronized with the device logic. Therefore SPI commands are executed with a delay of up to 3 µs after the CSN rising edge. 94 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Gate Drivers 11.3 PWM operation The half-bridge can be controlled in PWM using either three or six PWM inputs. The TLE9563-3QX offers the possibility to detect the active and the freewheeling (FW) MOSFET in each halfbridge. 11.3.1 Determination of the active and freewheeling MOSFET If EN_GEN_CHECK = 1, right before each MOSFET activation, the device detects which MOSFET of the halfbridge is the active MOSFET and which MOSFET is the free-wheeling (FW) MOSFET: • If VSHx > VS - VSHH: The high-side MOSFET is the FW MOSFET and the low-side MOSFET is the active MOSFET. • If VSHx < VSHL: Then the low-side MOSFET is the FW MOSFET and the high-side MOSFET is the active MOSFET. • If VSHL < VSHx < VSHH: No clear distinction between the active FW MOSFET and the active MOSFET. The next MOSFET to be turned on is turned on as if it was the active MOSFET. If EN_GEN_CHECK = 0, the detection of the active and FW MOSFET is disabled. The PWM MOSFET is considered as the active MOSFET. Figure 45 shows the detection of the active and of the FW MOSFET. HS and LS off Freewheeling through high-side MOSFET body diode VSHx > VSHH HS = FW MOSFET LS = Active MOSFET HS and LS are off Freewheeling through low-side MOSFET body diode VSHx < VSHL LS = FW MOSFET HS = Active MOSFET VCP VCP VS VS GHx Highside Gate-Driver GHx Highside Gate-Driver SHx SHx VSHH VSHH High-Speed Comparators High-Speed Comparators VSHL VSHL VCP VCP Lowside Gate-Driver GLx Lowside Gate-Driver SL SL Figure 45 11.3.2 GLx Detection of the active and FW MOSFET - Principle Configurations in PWM mode The following sections describe the different control schemes in PWM mode. Datasheet 95 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Gate Drivers Active gate control (AGC) The active gate control is configured by the control bits AGC[1:0]. The control scheme during the pre-charge and pre-discharge phases of: • The active MOSFET (EN_GEN_CHECK=1). • The PWM MOSFET (EN_GEN_CHECK=0). can be selected. The following settings are possible: • Adaptive gate control (AGC[1:0] = (1,0) or (1,1), see GENCTRL): In this mode a pre-charge current and a predischarge current are applied to the gate of the controlled MOSFET. These currents are used to regulate effective the turn-on and turn-off delays to the respective target values. • No adaptive gate control (AGC[1;0] = (0,0)): in this mode, the pre-charge and pre-discharge phases are deactivated. • No adaptive gate control (AGC[1;0] = (0,1)). In this mode: – During the pre-charge phase, the MOSFET is discharged with the configured current IPCHGINIT (HB_PCHG_INIT). – During the pre-discharge phase, the MOSFET is discharged with the configured current IPDCHGINIT (HB_PCHG_INIT). Note: It is recommended to configure tPCHGx < tHBxBLANK Active and tPDCHGx < tHBxCCP Active (Refer to TPRECHG and CCP_BLK) independently from the AGC settings. Active free-wheeling (AFW) The active free-wheeling is activated for HBx if these conditions are fulfilled: • AFWx = 1 (HBMODE) • HBx_PWM_EN = 1 (HBMODE) • PWM_NB = 0 If AFWx = 1, a cross-current protection time is applied to HBx (set by CCP_BLK) during the PWM operation. If AFWx = 0, no cross current protection is applied to HBx during the PWM operation. The active free-wheeling reduces the power dissipation of the free-wheeling MOSFET. If an active MOSFET is OFF, the opposite MOSFET of the same half-bridge is actively turned on. Refer to Figure 49 and Figure 50. Datasheet 96 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Gate Drivers Post-charge A post-charge is initiated if POCHGDIS is set to 0 (GENCTRL) to reach the minimum MOSFET Rdson: • POCHGDIS = 0: After the charge phase, the control signal for the charge current of LSx is increased by one current step at every bridge driver clock cycle (BDFREQ) to ICHGMAXx. Refer to Figure 46 • POCHGDIS = 1: The post-charge phase is disabled. The charge current is kept to the ICHGx Turn-on of: PWM MOSFET if EN_GEN_CHECK = 0 Active MOSFET if EN_GEN_CHECK =1 Precharge IGS Turn-off of: PWM MOSFET if EN_GEN_CHECK = 0 Active MOSFET if EN_GEN_CHECK =1 Post-charge tPCHGx Predischarge ICHGMAXx IPRECHGx tPDCHGx ICHGx t 0 - IDCHGx tBLANK active - IPREDCHGx tHBxCPP active PWM overview - AGC = 10B or 11B, POCHGDIS=0 (post-charge enabled) Figure 46 Turn-on of: PWM MOSFET if EN_GEN_CHECK = 0 Active MOSFET if EN_GEN_CHECK =1 IGS Turn-off of: PWM MOSFET if EN_GEN_CHECK = 0 Active MOSFET if EN_GEN_CHECK =1 Precharge tPCHGx Predischarge tPDCHGx IPRECHGx ICHGx t 0 - IDCHGx tBLANK Active - IPREDCHGx tHBxCPP Active Figure 47 PWM overview - AGC = 10B or 11B, POCHGDIS=1 (post-charge disabled) Table 28 Abbreviations for adaptive turn-on and turn-off phases in PWM configuration Abbreviation Definition Suffix x Related to the half-bridge x. VGS_HSx Gate-Source voltage of high-side MOSFET x. IGS_HSx Gate current of high-side MOSFET x. IGS_HSx is positive when the current flows out of GHx. VGS_LSx Gate-Source voltage of low-side MOSFET x. IGS_LSx Gate current of low-side MOSFET x. IGS_LSx is positive when the current flows out of GLx. tPWM_SYNCH Synchronization delay between external and internal PWM signal. tHBxCCP ACTIVE Active cross-current protection time of HBx. See control register CCP_BLK. tHBxBLANK ACTIVE Active Drain-source overvoltage blank time of HBx. See control register and CCP_BLK. tHBxCCP FW Freewheeling cross-current protection time of HBx. See control register CCP_BLK. Datasheet 97 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Gate Drivers Table 28 Abbreviations for adaptive turn-on and turn-off phases in PWM configuration (cont’d) Abbreviation Definition tHBxBLANK FW Freewheeling drain-source overvoltage blank time of HBx. See control register and CCP_BLK. PWMz External PWM signal applied to the input pin PWMz. ICHGMAXx Maximum drive current of the half-bridge x during the pre-charge and pre-discharge phases. See control register HB_ICHG_MAX. IPRECHGx and IPREDCHGx are limited to ICHGMAXx. IPRECHGx Pre-charge current sourced by the gate driver to the active MOSFET of the half-bridge x during tPCHGx (TPRECHG). Internal and self-adaptive parameter (if AGC[1:0] = (1,0) or (1,1), GENCTRL). IPRECHGx is clamped between ICHG0 (0.5 mA typ.) and ICHGMAXx. IPCHGINITx Initial value of IPRECHGx. Refer to HB_PCHG_INIT. IPREDCHGx Pre-discharge-current sunk by the gate driver mapped to the half-bridge x during tPDCHGx. Internal and self-adaptive parameter (if AGC[1:0] = (1,0) or (1,1), GENCTRL). IPREDCHGx is clamped between IDCHG0 (0.5 mA typ.) and ICHGMAXx. IPDCHGINITx Initial value of IPREDCHGx. Refer to HB_PCHG_INIT. ICHGx Current sourced by the gate driver to the active MOSFET of the half-bridge x during the charge phase. See control register HB_ICHG. IDCHGx Current sunk by the gate driver to turn-off the active MOSFET of the half-bridge x during the discharge phase. See control register HB_ICHG. ICHGFWx Current sourced or sunk by the gate driver to turn on / turn off the freewheeling MOSFET of the half-bridge x . See control register HB_ICHG. tPCHGx Duration of the pre-charge phase of half-bridge x. tPCHGx is configurable by SPI. See control register TPRECHG. tPDCHGx Duration of the pre-discharge phase of half-bridge x. tPDCHGx is configurable by SPI. See control register TPRECHG. tDONx Turn-on delay of the active MOSFET of HBx. tDOFFx Turn-off delay of the active MOSFET of HBx. IHOLD Hold current sourced or sunk by the gate driver to keep the MOSFET in the desired state. See IHOLD control bit in GENCTRL. IHARDOFF IHARDOFF is the maximum current that the gate drivers can sink. It corresponds to the discharge current when IDCHGx[5:0] = 63D (150 mA typ.). TFVDS Drain-Source overvoltage filter time. See LS_VDS. 11.3.3 PWM operation with 3 PWM inputs Each half bridge are controlled by one input if PWM_NB = 0 (see CSA) and HBx_PWM_EN (see HBMODE): • PWM1/CRC controls HB1 • PWM3 controls HB2 • PWM5 controls HB3 Datasheet 98 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Gate Drivers CP µC_PWM1 VS PWM1 HS1 CP PWM2 Control LS1 µC_PWM3 SL CP VS PWM3 HS2 CP PWM4 LS2 SL CP VS µC_PWM5 PWM5 HS3 CP PWM6 LS3 SL Figure 48 Half-bridge PWM control with three PWM inputs, PWM_NB = 0 Table 29 Half-bridge PWM settings with 3 PWM inputs PWM_NB HBxPWM_ EN1) HBxMODE1) AFW Half-bridge x settings1) 0 Don’t care 00B Don’t care LSx and HSx MOSFETs are kept OFF by the passive discharge 0 1 01B 0 PWM signal applied to LSx PWM signal = 1: LSx, ON, HSx OFF PWM signal = 0: LSx OFF, HS x OFF 0 1 10B 1 PWM signal applied to HSx PWM signal= 1: HSx, ON, LSx OFF PWM signal = 0: HSx OFF, LS x ON 0 Don’t care 11B Don’t care LSx and HSx MOSFETs are actively kept OFF 1) x = 1 to 3 11.3.3.1 Control signals with active free-wheeling (AFWx = 1) This section describes the MOSFET control signals with active freewheeling and HS PWM: • The HS PWM MOSFET is the active MOSFET (Chapter 11.3.3.1.1). • The HS PWM MOSFET is the free-wheeling MOSFET (Chapter 11.3.3.1.2). 11.3.3.1.1 The PWM MOSFET is the active MOSFET This section shows the control signals of the MOSFET when the PWM is the active MOSFET. Datasheet 99 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Gate Drivers External PWM signal tPWM_SYNCH t Synchronized intern. PWM signal VSHx < VSHL right before activation of HSx HSx detected as active MOSFET tHBxCCP FW IGS_HSx Charge phase t Postcharge Phase tPCHGx ICHGMAXx IPRECHGx HS MOSFET (Active MOSFET) ICHGx 0 t HSx internal drive signal tHBxBLANK Active tFVDS ICHGMAXx IPRECHGx IHOLD ICHGx IHOLD ICHGx t 0 - IHOLD VGS_HSx t VSHx tRISEx VS VSHH tDONx VSHL VSHH VSHL t IDS_HSDx IPHASE t LS MOSFET (FW MOSFET) LSx internal drive signal tHBxCCP FW IHOLD t - IHOLD - IHOLD Hard off - ICHGFWx - IHARDOFF Figure 49 Datasheet Turn-on of an active MOSFET in PWM mode with active gate control, HS PWM, HS as active MOSFET, LS as FW MOSFET. PWM_NB =0 (one PWM input per HB), HBxMODE = 10B (HS PWM), AGC = 01B or 10B (Active Gate Control), EN_GEN_CHECK=1 (detection of active / FW MOSFET), AFWx = 1 (active freewheeling for HBx is activated) 100 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Gate Drivers External PWM signal t Synchronized intern. PWM signal tPWM_SYNCH t tPDCHGx VSHx < VSHL right before activation of LSx LSx detected as FW MOSFET HSx internal drive signal Discharge phase HS MOSFET (Active) IHOLD t 0 - IHOLD - IDCHGx - IHOLD - IDCHGx - IPREDCHGx Hard off tHBxCCP Active - IHARDOFF VGS_HSx t VSHx VS VSHH VSHL tFALLx tDOFFx VSHH VSHL t IDS_HSDx IPHASE LS MOSFET (FW) t tHBx_BLANK FW LSx internal drive signal tFVDS ICHGFWx IHOLD IHOLD t - IHOLD Figure 50 Datasheet Turn-off of an active MOSFET in PWM mode with active gate control, HS PWM, HS as active MOSFET, LS as FW MOSFET. PWM_NB =0 (one PWM input per HB), HBxMODE = 10B (HS PWM), AGC = 01B or 10B (Active Gate Control), EN_GEN_CHECK=1 (detection of active / FW MOSFET), AFWx = 1 (active freewheeling for HBx is activated) 101 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Gate Drivers 11.3.3.1.2 The PWM MOSFET is the free-wheeling MOSFET This section shows the control signals of the MOSFET when the PWM is the free-wheeling MOSFET. External PWMz t tPWM_SYNCH Synchronized intern. PWMz t IGS_LSx Discharge phase tPDCHGx t 0 Low-side = Active MOSFET - IDCHGx - IPREDCHGx tHBxCCP Active for cross current protection LSx internal drive signal IHOLD t 0 - IHOLD - IDCHGx - IHOLD - IDCHGx - IPREDCHGx Hard off - IHARDOFF tFVDS VGS_LSx t VSHx tDOFFx tFALLx VS VSHH VSHH VSHL VSHL t Detection of the active MOSFET (EN_GEN_CHECK= 1). VSH > VSHH: LS MOSFET is the active MOSFET IDS_LSDx IPHASE t IGS_HSx High-side = FW MOSFET and PWM MOSFET ICHGFWx t tHBxBLANK FW HSx internal drive signal tFVDS ICHGFWx IHOLD IHOLD t - IHOLD Figure 51 Datasheet \G Di \fi \BLDC PWM rising edge - PWM mode with active gate control, HS PWM (HBxMODE = 10B) , LS as active MOSFET, HS as FW MOSFET. PWM_NB =0 (one PWM input per HB), AGC = 01B or 10B (Active Gate Control), EN_GEN_CHECK=1 (detection of active / FW MOSFET), AFWx = 1 (active freewheeling for HBx is activated) 102 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Gate Drivers External PWMz Synchronized intern. PWMz t tPWM_SYNCH Charge phase IGS_LSx t Postcharge Phase tPCHGx ICHGMAXx IPRECHGx ICHGx 0 t tHBxBLANK Active Low-side = Active MOSFET tHBxCCP FW LSx internal drive signal tFVDS ICHGMAXx IPRECHGx IHOLD ICHGx IHOLD ICHGx t 0 - IHOLD VGS_LSx t tRISEx VSHx tDONx VS VSHH VSHH VSHL IDS_LSDx VSHL t Detection of the active MOSFET (EN_GEN_CHECK= 1). VSH > VSHH: LS MOSFET is the active MOSFET IPHASE t IGS_HSx High-side = FW MOSFET and PWM MOSFET t - ICHGFWx HSx internal drive signal tFVDS IHOLD t - IHOLD - IHOLD - ICHGFWx Hard off - IHARDOFF Figure 52 Datasheet PWM falling edge - PWM mode with active gate control, HS PWM (HBxMODE = 10B) , LS as active MOSFET, HS as FW MOSFET. PWM_NB =0 (one PWM input per HB), AGC = 01B or 10B (Active Gate Control), EN_GEN_CHECK=1 (detection of active / FW MOSFET), AFWx = 1 (active freewheeling for HBx is activated) 103 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Gate Drivers 11.3.3.2 Control signals with passive free-wheeling (AFWx = 0) This section describes the MOSFET control signals with active freewheeling and HS PWM: • The HS PWM MOSFET is the active MOSFET (Chapter 11.3.3.2.1). • The HS PWM MOSFET is the free-wheeling MOSFET (Chapter 11.3.3.2.2). 11.3.3.2.1 The PWM MOSFET is the active MOSFET This section shows the control signals of the MOSFET when the PWM is the active MOSFET. Datasheet 104 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Gate Drivers External PWMz Synchronized intern. PWMz t tPWM_SYNCH Charge phase IGS_HSx t Postcharge Phase tPCHGx ICHGMAXx PWM MOSFET = Active MOSFET IPRECHGx ICHGx 0 t tHBxBLANK HSx internal drive signal tFVDS ICHGMAXx IPRECHGx IHOLD ICHGx IHOLD ICHGx t 0 - IHOLD VGS_HSx t VSHx VS VSHH tRISEx tDONx VSHL VSHH VSHL t IDS_HSDx IPHASE t FW MOSFET PFW IGS_LSx t LSx internal drive signal tFVDS t - IHOLD - IHOLD Hard off - IHARDOFF Figure 53 Datasheet Adaptive turn-on with high-side PWM, AGC[1:0] = (1,0) or (1,1), AFWx=0, POCHGDIS=0, the PWM MOSFET is the active MOSFET. PWM_NB=0. 105 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Gate Drivers External PWMz t tPWM_SYNCH Synchronized intern. PWMz t IGS_HSx PWM MOSFET = Active MOSFET Discharge phase tPDCHGx t 0 - IDCHGx - IPREDCHGx tHBxCCP Active HSx internal drive signal IHOLD t 0 - IHOLD - IDCHGx - IDCHGx - IPREDCHGx - IHOLD VGS_HSx t VSHx tFALLx tDOFFx VS VSHH VSHH VSHL VSHL t IDS_HSDx IPHASE FW MOSFET PFW t IGS_LSx 0 t LSx internal drive signal t - IHOLD Figure 54 Adaptive turn-off with high-side PWM, AGC[1:0] = (1,0) or (1,1), AFWx=0, POCHGDIS=0, the PWM MOSFET is the active MOSFET.PWM_NB=0. 11.3.3.2.2 The PWM MOSFET is the free-wheeling MOSFET This section shows the control signals of the MOSFET when the PWM is the free-wheeling MOSFET. Datasheet 106 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Gate Drivers External PWMz t tPWM_SYNCH Synchronized intern. PWMz t IGS_LSx Discharge phase tPDCHGx t 0 Low-side = Active MOSFET - IDCHGx - IPREDCHGx tHBxCCP Active for cross current protection LSx internal drive signal IHOLD t 0 - IHOLD - IDCHGx - IHOLD - IDCHGx - IPREDCHGx VGS_LSx t VSHx tDOFFx tFALLx VS VSHH VSHL VSHH VSHL t Detection of the active MOSFET (EN_GEN_CHECK= 1). VSH > VSHH: LS MOSFET is the active MOSFET IDS_LSDx IPHASE High-side = FW MOSFET (and PWM MOSFET) t Figure 55 Datasheet IGS_HSx t HSx internal drive signal t - IHOLD \G t D i \fi \BLDC\ PWM rising edge with adaptive control, EN_GEN_CHECK = 1 with high-side PWM, AGC[1:0] = (1,0) or (1,1), AFWx=0, POCHGDIS=0. The PWM MOSFET is the FW MOSFET. PWM_NB=0. 107 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Gate Drivers Detection of the active MOSFET (EN_GEN_CHECK= 1). VSH > VSHH: LS MOSFET is the active MOSFET External PWMz Synchronized intern. PWMz t tPWM_SYNCH Charge phase IGS_LSx t Postcharge Phase tPCHGx ICHGMAXx IPRECHGx ICHGx 0 t Low-side = Active MOSFET tHBxBLANK Active LSx internal drive signal tFVDS ICHGMAXx IPRECHGx IHOLD ICHGx IHOLD ICHGx t 0 - IHOLD VGS_LSx t VSHx VS VSHH tRISEx tDONx VSHL VSHH VSHL t IDS_LSDx IPHASE t IGS_HSx High-side FW MOSFET (and PWM MOSFET) t Figure 56 HSx internal drive signal tFVDS t - IHOLD - IHOLD Hard off - IHARDOFF PWM falling edge with adaptive control, EN_GEN_CHECK = 1 with high-side PWM, AGC[1:0] = (1,0) or (1,1), AFWx=0, POCHGDIS=0. The PWM MOSFET is the FW MOSFET. PWM_NB=0. 11.3.3.3 Time modulation of pre-charge and pre-discharge times If DEEP_ADAP =0: Datasheet 108 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Gate Drivers • one single precharge current is applied during tPCHGx to regulate TDON • one single precharge current is applied during tPDCHGx to regulate TDOFF If DEEP_ADAP = 1 (“deep adaptation” or “time modulation”) it is possible to: • to divide the precharge phase in two parts, during which two different precharge currents can be applied • to divide the predischarge phase in two parts, during which two different precharge currents can be applied Figure 57 describes the principle of the time modulation applied to the precharge phase. The same principle is also applied for the regulation of the pre-discharge phase. Datasheet 109 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Gate Drivers TDON adaptation with two current steps (IPCHGADT = 1) Current i+2 No 3 consecutive sign changes of (TDON EFF- TDON TARGET) or No error for 3 consecutive PWM cycles Current i Yes tPCHG tPCHG TDON adaptation with one current step i+1 i 3 consecutive sign changes of (TDON EFF- TDON TARGET) No tPCHG tPCHG Yes Precharge phase splitted in 2 sub-phases i+1 i 50% 50% tPCHG Exit from time modulation 2) Yes TDON EFF = TDON TARGET No Precharge splitted: 75%-25% if TDON EFF > TDON TARGET 25%-75% if TDON EFF < TDON TARGET i+1 i or 25% 75% Yes tPCHG TDON EFF = TDON TARGET i+1 i 75% 25% tPCHG No Precharge splitted: E.g 87.5%-12.5% Etc... 1) No 2) 1) Precharge further split either: - until TDON EFF = TDON TARGET - Or until no further split of tPCHG is possible. Refer to 2). TDON EFF = TDON TARGET 2) Exit time modulation: - tPCHG cannot be further divided due to the limitation of the resolution - and the regulation of TDON is still not possible à One single current is applied during tPCHG Figure 57 Datasheet Principle of the time modulation of the precharge phase, DEEP_ADAP = 1, AGC = 10B or 11B 110 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Gate Drivers 11.3.3.4 Operation at high and low duty cycles In the particular cases where the on-time is shorter than tHBxCCP FW or the off-time of the PWM signal is shorter than tHBxCCP Active: • No distinction between active MOSFET and FW MOSFET is possible. Therefore PWM MOSFET (selected by HBxMODE[1:0]) is controlled as active MOSFET. • The MOSFET opposite to the PWM MOSFET stays off (passive FW) 11.3.3.5 Measurements of the switching times The effective switching times in PWM operation: • of the PWM MOSFET if EN_GEN_CHECK = 0 • of the active MOSFET if EN_GEN_CHECK = 1 are reported in the registers: EFF_TDON_OFF1,EFF_TDON_OFF2,EFF_TDON_OFF3. If the end of the rise time for a given MOSFET is not detected before tHBxBLANK Active elapses, then the corresponding status register reports an effective rise time equal to zero. If the end of the fall time for a given MOSFET is not detected before tHBxCCP Active active elapses, then the corresponding status register reports an effective fall time equal to zero. The device cannot measure the switching times tDON, tDOFF, tRISE and tFALL at very high and very low duty cycles: tON < tHBxCCP FW and tOFF < tHBxCCP active. In this case, the corresponding registers report effective tDON, tDOFF, tRISE and tFALL equal to zero. Datasheet 111 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Gate Drivers 11.3.4 PWM operation with 6 PWM inputs Each high-side MOSFET and each low-side MOSFET is controlled by one PWM input. if PWM_NB is set to 1 (see CSA) and HBx_PWM_EN are set to 1 (see HBMODE). Refer to Table 30. CP µC_PWM2 VS PWM2 HS1 CP µC_PWM1 PWM1 LS1 µC_PWM4 µC_PWM3 PWM4 Control SL CP VS HS2 CP PWM3 LS2 SL CP µC_PWM6 VS PWM6 HS3 CP µC_PWM5 PWM5 LS3 SL Figure 58 Half-bridge PWM control with six PWM inputs, PWM_NB = 1 Table 30 Half-bridge PWM settings with 6 PWM inputs (PWM_NB = 1)FW and Active MOSFET PWM_NB HBx_PWM HBxMODE1) _EN1) Half-bridge x settings1) 1 Don’t care 00B LSx and HSx MOSFETs are kept OFF by the passive discharge (default) 1 1 01B HBx is controlled by its PWM inputs 1 1 1 Don’t care 10B 11B • If EN_GEN_CHECK = 0: LSx is always considered as the active MOSFET • If EN_GEN_CHECK = 1: The active and the FW MOSFETs are detected according to Chapter 11.3.1, independently from HBxMODE HBx is controlled by its PWM inputs • If EN_GEN_CHECK = 0: HSx is always considered as the active MOSFET • If EN_GEN_CHECK = 1: The active and the FW MOSFETs are detected according to Chapter 11.3.1 independently from HBxMODE LSx and HSx MOSFETs are actively kept OFF 1) x = 1 to 3 Datasheet 112 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Gate Drivers Table 31 PWM Control of HS1 and LS1, PWM_NB = 1, HB1_PWM_EN = 1 HB1MODE[1:0] PWM1/CRC PWM2 HS1 LS1 01 Low Low OFF OFF 01 Low High ON OFF 01 High Low OFF ON 01 High High OFF OFF 10 Low Low OFF OFF 10 Low High OFF ON 10 High Low ON OFF 10 High High OFF OFF Table 32 PWM Control of HS2 and LS2, PWM_NB = 1, HB2_PWM_EN = 1 HB2MODE[1:0] PWM3 PWM4 HS2 LS2 01 Low Low OFF OFF 01 Low High ON OFF 01 High Low OFF ON 01 High High OFF OFF 10 Low Low OFF OFF 10 Low High OFF ON 10 High Low ON OFF 10 High High OFF OFF Table 33 PWM Control of HS3 and LS3, PWM_NB = 1, HB3_PWM_EN = 1 HB3MODE[1:0] PWM5 PWM6 HS3 LS3 01 Low Low OFF OFF 01 Low High ON OFF 01 High Low OFF ON 01 High High OFF OFF 10 Low Low OFF OFF 10 Low High OFF ON 10 High Low ON OFF 10 High High OFF OFF Figure 59 shows the PWM control of HBx in PWM (HBx_PWM_EN = 1): Turn-off of the FW MOSFET (low-side MOSFET in this case) followed by the activation of the active MOSFET (high-side MOSFET in this case)1) with PWM_NB = 1, AGC[1:0]=01B or 10B, POCHGDIS = 0 (post-charge enabled). This control scheme is applicable for the following cases: 1) If the synchronized HS PWM rising edge occurs after tHBxCCP FW and before the end of tOFF timeout FW, then the LS MOSFET is discharged with IHARDOFF and the HS is turned on, when the HS PWM rising edge is detected Datasheet 113 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Gate Drivers 1. EN_GEN_CHECK = 0 (detection of FW/Active MOSFET disabled); HBxMODE[1:0] = 10B (HS MOSFET is considered as active MOSFET by default). 2. EN_GEN_CHECK = 1 (detection of active / FW MOSFET enabled); HS MOSFET detected as active MOSFET; HBxMODE[1:0] = 01B or10B. Note: Datasheet If the synchronized HS PWM rising edge occurs before the end of tHBxCCP active, then the device prevents an activation of the HS MOSFET until tHBxCCP FW elapses. In other words, the HS PWM rising edge is ignored until the end of tHBxCCP FW. 114 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Gate Drivers External HSx PWM signal Synchronized HSx PWM signal tPWM_SYNCH Charge phase IGS_HSx t Postcharge Phase tPCHGx ICHGMAXx IPRECHGx HS MOSFET (Active MOSFET) ICHGx 0 t HSx internal drive signal tHBxBLANK Active tFVDS ICHGMAXx IPRECHGx IHOLD ICHGx IHOLD ICHGx t 0 - IHOLD VGS_HSx t VSHx VSHx < VSHL right before the activation of HSx tRISEx HSx detected as active MOSFET VS VSHH VSHH tDONx VSHL VSHL t IDS_HSDx IPHASE t Synchronized LSx PWM signal LS MOSFET (FW MOSFET) LSx internal drive signal tHBxCCP FW t tOFF Timeout FW tFVDS IHOLD t - IHOLD - IHOLD - ICHGFWx Hard off - IHARDOFF Figure 59 Datasheet Turn-on of an active MOSFET in PWM mode with active gate control, HS as active MOSFET, LS as FW MOSFET. Two PWM inputs per half-bridge, active gate control enabled. PWM_EN =1 115 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Gate Drivers Figure 60 shows the PWM control of HBx in PWM (HBx_PWM_EN = 1): Turn-off of the active MOSFET (high-side MOSFET in this case) followed by the activation of the FW MOSFET low-side MOSFET in this case) with PWM_NB = 1, AGC[1:0] = 01B or 10B, POCHGDIS = 0 (post-charge enabled). This control scheme is applicable for the following cases: 1. EN_GEN_CHECK = 0 (detection of FW/Active MOSFET disabled); HBxMODE[1:0] = 10B (HS MOSFET is considered as active MOSFET by default). 2. EN_GEN_CHECK = 1 (detection of active / FW MOSFET enabled); HS MOSFET detected as active MOSFET; HBxMODE[1:0] = 01B or 10B. Note: Datasheet If the synchronized LS PWM rising edge occurs before the end of tHBxCCP active, then the device prevents an activation of the LS MOSFET until tHBxCCP active elapses. In other words, the LS PWM rising edge is ignored until the end of tHBxCCP active. 116 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Gate Drivers External HSx PWM signal t tPWM_SYNCH Synchronized HSx PWM signal t tPDCHGx Discharge phase HSx internal drive signal tHBxCCP Active HS MOSFET (Active MOSFET) IHOLD t 0 - IHOLD - IHOLD - IDCHGx - IHOLD - IDCHGx - IPREDCHGx tOFF timeout Active Hard off - IHARDOFF VGS_HSx t VSHx VS VSHH VSHL tFALLx VSHx < VSHL right before the activation of HSx HSx detected as active MOSFET tDOFFx VSHH VSHL t IDS_HSDx IPHASE t LS MOSFET (FW MOSFET) Synchronized LSx PWM signal t LSx internal drive signal tHBxBLANK FW tFVDS ICHGFWx IHOLD IHOLD t - IHOLD Figure 60 Turn-off of an active MOSFET in PWM mode with active gate control, HS as active MOSFET, LS as FW MOSFET. two PWM inputs per half-bridge, active gate control enabled. PWM_NB=1. 11.3.5 Status bits for regulation of turn-on and turn-off delay times The control bits TDREGx (TDREG) indicate if tDONx and tDOFFx of the half-bridge x, using the adaptive control scheme (AGC = 10B or 11B), are in regulation. Datasheet 117 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Gate Drivers The half-bridge x is considered in regulation if one of the following conditions is met: • Condition 1: The effective turn-on and turn-off delays are equal to the configured delays for at least eight cumulative PWM cycle (HBx tDON counter ≥ 8 and HBx tDOFF counter ≥ 8). For each PWM cycle – if tDONxEFF1) = TDONx2), x = 1.. 3, HBx tDON counter is incremented – if tDONxEFF1) ≠ TDONx2), x = 1.. 3, HBx tDON counter is decremented – if tDOFFxEFF1) = TDOFFx3), x = 1.. 3, HBx tDOFF counter is incremented – if tDOFFxEFF 1) ≠ TDOFFx3), x = 1.. 3, HBx tDOFF counter is decremented • Condition 2: The error between the effective delays ((tDONxEFF-TDONx) and(tDOFFxEFF-TDOFFx )) changes its sign three times consecutively 1) Refer to EFF_TDON_OFF1, EFF_TDON_OFF2, EFF_TDON_OFF3 2) Refer to TDON_HB_CTRL 3) Refer to TDOFF_HB_CTRL Datasheet 118 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Gate Drivers 11.3.6 Gate driver current Each gate driver is able to source and sink currents from 0.5 mA to 150 mA, with 64 steps. 150 Nominal PWM charge/ intial precharge current [mA] 140 130 120 110 100 90 80 70 60 50 40 30 20 10 0 0 Figure 61 Datasheet 5 10 15 20 25 30 ICHG[5:0]dec 35 40 45 50 55 60 Configurable discharge currents in PWM operation 119 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Gate Drivers Table 34 Charge currents and initial precharge currents ICHGx[5:0], PCHGINITx[5:0] Parameter Nom. current name [mA] Max. deviation to nominal values [%] 000000B ICHG0 0.5 +/- 60% 000001B ICHG1 0.7 +/- 60 % 000010B ICHG2 1.0 +/- 60 % 000011B ICHG3 1.4 +/- 60 % 000100B ICHG4 1.8 +/- 60 % 000101B ICHG5 2.4 +/- 60 % 000110B ICHG6 3.0 +/- 60 % 000111B ICHG7 3.8 +/- 60 % 001000B ICHG8 4.7 +/- 55% 001001B ICHG9 5.8 +/- 55% 001010B ICHG10 6.9 +/- 55% 001011B ICHG11 8.1 +/- 55% 001100B ICHG12 9.4 +/- 55% 001101B ICHG13 10.8 +/- 55% 001110B ICHG14 12.2 +/- 40% 001111B ICHG15 13.7 +/- 40% 010000B ICHG16 15.3 +/- 40 % 010001B ICHG17 17.1 +/- 40 % 010010B ICHG18 19 +/- 40% 010011B ICHG19 21 +/- 40 % 010100B ICHG20 23 +/- 40% 010101B ICHG21 25 +/- 40 % 010110B ICHG22 27.1 +/- 40 % 010111B ICHG23 29.3 +/- 40 % 011000B ICHG24 31.6 +/- 40 % 011001B ICHG25 34 +/- 40 % 011010B ICHG26 36.5 +/- 40 % 011011B ICHG27 39 +/- 40 % 011100B ICHG28 41.6 +/- 40 % 011101B ICHG29 44.2 +/- 30 % 011110B ICHG30 46.9 +/- 30 % 011111B ICHG31 49.7 +/- 30 % 100000B ICHG32 52.5 +/- 30 % 100001B ICHG33 55.3 +/- 30 % 100010B ICHG34 58.1 +/- 30 % 100011B ICHG35 60.8 +/- 30 % Datasheet 120 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Gate Drivers Table 34 Charge currents and initial precharge currents (cont’d) ICHGx[5:0], PCHGINITx[5:0] Parameter Nom. current name [mA] Max. deviation to nominal values [%] 100100B ICHG36 63.6 +/- 30 % 100101B ICHG37 66.5 +/- 30 % 100110B ICHG38 69.4 +/- 30 % 100111B ICHG39 72.3 +/- 30 % 101000B ICHG40 75.2 +/- 30 % 101001B ICHG41 78.1 +/- 30 % 101010B ICHG42 81.1 +/- 30 % 101011B ICHG43 84.1 +/- 30 % 101100B ICHG44 87.1 +/- 30 % 101101B ICHG45 90.2 +/- 30 % 101110B ICHG46 93.3 +/- 30 % 101111B ICHG47 96.4 +/- 30 % 110000B ICHG48 99.5 +/- 30 % 110001B ICHG49 102.7 +/- 30 % 110010B ICHG50 105.8 +/- 30 % 110011B ICHG51 109 +/- 30 % 110100B ICHG52 112.2 +/- 30 % 110101B ICHG53 115.4 +/- 30 % 110110B ICHG54 118.7 +/- 30 % 110111B ICHG55 122 +/- 30 % 111000B ICHG56 125.3 +/- 30 % 111001B ICHG57 128.7 +/- 30 % 111010B ICHG58 132.1 +/- 30 % 111011B ICHG59 135.5 +/- 30 % 111100B ICHG60 139 +/- 30 % 111101B ICHG61 142.5 +/- 30 % 111110B ICHG62 146 +/- 30 % 111111B ICHG63 150 +/- 30 % Datasheet 121 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Gate Drivers 150 Nominal PWM Discharge/Initial precharge current [mA] 140 130 120 110 100 90 80 70 60 50 40 30 20 10 0 0 Figure 62 Datasheet 5 10 15 20 25 30 IDCHG[5:0]dec 35 40 45 50 55 60 Configurable discharge currents in PWM operation 122 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Gate Drivers Table 35 Discharge currents and initial predischarge currents IDCHG[5:0], PDCHGINITx[5:0] Parameter name Nom. current [mA] Max. deviation to nominal values [%] 000000B IDCHG0 0.5 +/- 60% 000001B IDCHG1 0.7 +/- 60 % 000010B IDCHG2 1.0 +/- 60 % 000011B IDCHG3 1.4 +/- 60 % 000100B IDCHG4 1.8 +/- 60 % 000101B IDCHG5 2.4 +/- 60 % 000110B IDCHG6 3.0 +/- 60 % 000111B IDCHG7 3.8 +/- 60 % 001000B IDCHG8 4.7 +/- 60 % 001001B IDCHG9 5.8 +/- 60 % 001010B IDCHG10 6.9 +/- 60 % 001011B IDCHG11 8.1 +/- 60 % 001100B IDCHG12 9.4 +/- 60 % 001101B IDCHG13 10.7 +/- 60 % 001110B IDCHG14 12.1 +/- 40% 001111B IDCHG15 13.5 +/- 40% 010000B IDCHG16 15.1 +/- 40 % 010001B IDCHG17 16.8 +/- 40 % 010010B IDCHG18 18.6 +/- 40% 010011B IDCHG19 20.5 +/- 40 % 010100B IDCHG20 22.5 +/- 40% 010101B IDCHG21 24.5 +/- 40 % 010110B IDCHG22 26.5 +/- 40 % 010111B IDCHG23 28.7 +/- 40 % 011000B IDCHG24 30.9 +/- 40 % 011001B IDCHG25 33.2 +/- 40 % 011010B IDCHG26 35.7 +/- 40 % 011011B IDCHG27 38.2 +/- 40 % 011100B IDCHG28 40.8 +/- 40 % 011101B IDCHG29 43.4 +/- 30 % 011110B IDCHG30 46.1 +/- 30 % 011111B IDCHG31 48.8 +/- 30 % 100000B IDCHG32 51.5 +/- 30 % 100001B IDCHG33 54.2 +/- 30 % 100010B IDCHG34 56.9 +/- 30 % 100011B IDCHG35 59.6 +/- 30 % Datasheet 123 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Gate Drivers Table 35 Discharge currents and initial predischarge currents (cont’d) IDCHG[5:0], PDCHGINITx[5:0] Parameter name Nom. current [mA] Max. deviation to nominal values [%] 100100B IDCHG36 62.4 +/- 30 % 100101B IDCHG37 65.2 +/- 30 % 100110B IDCHG38 68 +/- 30 % 100111B IDCHG39 70.8 +/- 30 % 101000B IDCHG40 73.7 +/- 30 % 101001B IDCHG41 76.6 +/- 30 % 101010B IDCHG42 79.5 +/- 30 % 101011B IDCHG43 82.5 +/- 30 % 101100B IDCHG44 85.5 +/- 30 % 101101B IDCHG45 88.5 +/- 30 % 101110B IDCHG46 91.5 +/- 30 % 101111B IDCHG47 94.6 +/- 30 % 110000B IDCHG48 97.7 +/- 30 % 110001B IDCHG49 100.9 +/- 30 % 110010B IDCHG50 104.2 +/- 30 % 110011B IDCHG51 107.5 +/- 30 % 110100B IDCHG52 110.8 +/- 30 % 110101B IDCHG53 114.2 +/- 30 % 110110B IDCHG54 117.6 +/- 30 % 110111B IDCHG55 121 +/- 30 % 111000B IDCHG56 124.5 +/- 30 % 111001B IDCHG57 128 +/- 30 % 111010B IDCHG58 131.5 +/- 30 % 111011B IDCHG59 135.1 +/- 30 % 111100B IDCHG60 138.7 +/- 30 % 111101B IDCHG61 142.3 +/- 30 % 111110B IDCHG62 145.8 +/- 30 % 111111B IDCHG63 150 +/- 30 % 11.4 Passive discharge Resistors (RGGND) between the gate of GHx and GND, and between GLx and GND, ensure that the external MOSFETs are turned off in the following conditions: • VCC1 undervoltage • HBxMODE = 00B in Normal Mode • CPEN = 0 in Normal Mode • CSA Overcurrent detection with OCEN = 1 in normal mode Datasheet 124 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Gate Drivers • VS overvoltage or VSINT overvoltage • Charge pump undervoltage and charge pump blank time (tCPUVBLANK) • Charge pump overtemperature (CP_OT) • VDS overvoltage after active discharge in Normal Mode • In Init Mode, Stop Mode, Fail Safe Mode, Restart Mode and Sleep Mode (exceptions for low-sides in parking braking and VS / VSINT overvoltage braking , refer to Chapter 11.6 and Chapter 12.11.3) 11.5 Slam mode The slam mode is applicable in Normal Mode. If the SLAM bit is set in BRAKE register: 1. If HBxMODE = 01b or 10b , then the corresponding MOSFETs are actively turned off with their static discharge current during their respective tHBxCCP Active. 2. Then charge pump is deactivated independently from CPEN 3. Then PWM1/CRC input pin is mapped to LS1, LS2, LS3, independently from PWM_NB, HBxMODE and HBx_PWM_EN a) If PWM1/CRC is High, then the low-side MOSFETs are turned on within tON_BRAKE. b) If PWM1/CRC is Low, then the low-side MOSFETs are turned off within tOFF_BRAKE. There is also the possibility to disable selectively the LSx in SLAM mode. 11.6 Parking braking mode If PARK_BRK_EN bit is set, while the device goes in Sleep Mode or in Stop Mode: 1. If HBxMODE = 01b or 10b , then the corresponding MOSFETs are actively turned off with their static discharge current during their respective tHBxCCP Active. 2. Then charge pump is deactivated independently from CPEN bit. 3. Then the passive discharge (RGGND) of the low-sides is deactivated, the passive discharge of the high-sides are activated 4. If PWM1/CRC is High, then the low-side MOSFETs are turned on within tON_BRAKE. Refer to Chapter 12.11.2 for the protection of the of low-side MOSFETs against short circuits when the parking braking mode is activated. Datasheet 125 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Gate Drivers 11.7 Charge pump A dual-stage charge pump supplies the gate drivers for the high-side and low-side MOSFETs. It requires three external capacitors connected between CPC1N and CPC1P, CPC2N and CPC2P, VS and CP. The buffer capacitor between VS and CP must have a capacitance equal or higher than 470 nF. CCP ≥ 470 nF CCP1 CPC2P CPC1P CPC2N CPC1N VS CCP2 CP Single/dual stage charge pump Precharge Logic Figure 63 Charge pump - Block diagram Logic or normal level MOSFETs The regulation of the charge pump outputs voltage can be configured depending on the type of MOSFET. FET_LVL = 0: Logic level MOSFETs are selected: • VCP - VS = VCP3 (11 V typ. at VS > 8 V). • The high-side gate-source voltage GHx - SHx is VGH4 (VS > 8 V). • The low-side gate-source voltage GLx - SL is VGH3 (VS > 8 V). FET_LVL = 1: Normal level MOSFETs are selected: • VCP - VS = VCP1(15 V typ. at VS > 8 V). • The high-side and low-side gate-source voltage GHx - SHx or GLx - SL is VGH1 (VS > 8 V). CPSTGA = 0 (default, see GENCTRL), the device operates with the dual-stage charge pump. If CPSTGA = 1, the device switches to single-stage or dual-stage charge pump automatically: • If VS > VCPSO DS: the TLE9563-3QX switches from a dual-stage to a single-stage charge pump. • If VS < VCPSO SD: the TLE9563-3QX switches from single-stage to dual-stage charge pump. The operation with the single-stage charge pump reduces the current consumption from the VS pin. Datasheet 126 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Gate Drivers 11.8 Frequency modulation A modulation of the charge pump frequency can be activated to reduce the peak emission. The modulation frequency is set by the control bit FMODE in GENCTRL: • FMODE = 0: No modulation. • FMODE = 1: Modulation frequency = 15.6 kHz (default). Datasheet 127 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Gate Drivers 11.9 Electrical characteristics gate driver The electrical characteristics related to the gate driver are valid for VCP > VS + 8.5 V Table 36 Electrical characteristics: gate drivers VSINT = 5.5 V to 28 V, Tj = -40°C to +150°C, VCP > VS + 8.5 V, VS = 6 to 19V, all voltages with respect to ground, positive current flowing into pin except for IGLx and IGHx (unless otherwise specified). Parameter Symbol Values Min. Typ. Unit Max. Note or Test Condition Number Comparators SHx High Threshold VSHH VS - 2.6 – VS - 1.9 V SHx Low Threshold VSHL 1.9 2.6 – P_12.11.1 V Referred to GND P_12.11.2 P_12.11.3 – 12 30 ns 1) High Level Output Voltage VGH1 GHx vs. SHx and GLx vs. SL 10 11.5 12.5 V 2) VS ≥ 8 V , CLoad = 10 nF, ICP = -12 mA, FET_LVL = 1 P_12.11.4 High Level Output Voltage VGH2 GHx vs. SHx and GLx vs. SL 7 – 12.5 V VS = 6 V, CLoad = 10 nF, ICP = -6 mA, FET_LVL = 1 P_12.11.5 High Level Output Voltage VGH3 GLx vs. SL 10 – 12.5 V 3) VS ≥ 6 V , CLoad = 10 nF, FET_LVL = 0 P_12.11.6 High Level Output Voltage VGH4 GHx vs. SHx 8.5 10 12.5 V 2) VS ≥ 8 V , CLoad = 10 nF, ICP = -12 mA, FET_LVL = 0 P_12.11.7 High Level Output Voltage VGH5 GHx vs. SHx 7 – 12.5 V VS = 6 V, CLOAD= 10 nF, ICP = -6 mA, FET_LVL =0 P_12.11.8 Charge current ICHG0 -60% 0.5 +60% mA ICHG = 0D 1) P_12.11.70 CLoad = 2.2 nF VS ≥8V, VGS≤VGS(ON)4) Charge current ICHG8 -55% 4.7 +55% mA ICHG =8 D 1) P_12.11.71 CLoad = 2.2 nF VS ≥8V, VGS≤VGS(ON)4) Charge current ICHG16 -40% 15.3 +40% mA ICHG =16 D 1) P_12.11.72 CLoad = 2.2 nF VS ≥8V, VGS≤VGS(ON)4) Charge current ICHG32 -30% 52.5 +30% mA ICHG =32 D 1) P_12.11.73 CLoad = 10 nF VS ≥8V, VGS≤VGS(ON)4) SHx comparator delay tSHx MOSFET Driver Output Datasheet 128 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Gate Drivers Table 36 Electrical characteristics: gate drivers (cont’d) VSINT = 5.5 V to 28 V, Tj = -40°C to +150°C, VCP > VS + 8.5 V, VS = 6 to 19V, all voltages with respect to ground, positive current flowing into pin except for IGLx and IGHx (unless otherwise specified). Parameter Symbol Values Min. Typ. Max. Unit Note or Test Condition Number Charge current ICHG48 -30% 99.5 +30% mA ICHG =48 D 1) P_12.11.74 CLoad = 10 nF VS ≥8V, VGS≤VGS(ON)4) Charge current ICHG63 -30% 150 +30% mA ICHG =63 D 1) P_12.11.75 CLoad = 22 nF VS ≥8V, VGS≤VGS(ON)4) Discharge current IDCH0 -60% -0.5 +60% mA IDCHG =0 D 1) P_12.11.76 CLoad = 2.2 nF VS ≥8V,VGS≥VGS(OFF1) Discharge current IDCH8 -55% -4.7 55% mA IDCHG =8 D 1) P_12.11.77 CLoad = 2.2 nF VS ≥8V,VGS≥VGS(OFF1) Discharge current IDCHG16 -40% -15.1 +40% mA IDCHG =16 D 1) P_12.11.78 CLoad = 2.2 nF VS ≥8V,VGS≥VGS(OFF1) Discharge current IDCHG32 -30% -51.5 +30% mA IDCHG =32 D 1) P_12.11.79 CLoad = 10 nF VS ≥8V,VGS≥VGS(OFF2) Discharge current IDCHG48 -30% -97.7 +30% mA IDCHG = 48D 1) P_12.11.80 CLoad = 10 nF VS ≥8V,VGS≥VGS(OFF2) Discharge current IDCHG63 -30% -150 +30% mA IDCHG = 63D 1) P_12.11.81 CLoad = 22 nF VS ≥8V,VGS≥VGS(OFF2) Charge current temperature drift ICHG0,TDrift -37% -12% 15% ICHG = 0D 1)5) P_12.11.119 Charge current temperature drift ICHG8,TDrift -17% 1% 20% ICHG = 8D 1)5) P_12.11.120 Charge current temperature drift ICHG16,TDrift -12% 3% 18% ICHG = 16D 1)5) P_12.11.121 Charge current temperature drift ICHG32,TDrift -11% -1% 9% ICHG = 32D 1)5) P_12.11.122 Charge current temperature drift ICHG48,TDrift -7.5% 0.5% 8% ICHG = 48D 1)5) P_12.11.123 Charge current temperature drift ICHG63,TDrift -5.5% 1.5% 8.5% IDCHG = 63D 1)5) P_12.11.124 Discharge current temperature drift IDCHG0,TDrift -29% -4.5% 20% IDCHG = 0D 1)5) P_12.11.125 Datasheet 129 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Gate Drivers Table 36 Electrical characteristics: gate drivers (cont’d) VSINT = 5.5 V to 28 V, Tj = -40°C to +150°C, VCP > VS + 8.5 V, VS = 6 to 19V, all voltages with respect to ground, positive current flowing into pin except for IGLx and IGHx (unless otherwise specified). Parameter Symbol Values Unit Min. Typ. Max. Note or Test Condition Number Discharge current temperature drift IDCHG8,TDrift -8% 8.5% 26% IDCHG = 8D 1)5) P_12.11.126 Discharge current temperature drift IDCHG16,TDrift -4% 9.5% 23% IDCHG = 16D 1)5) P_12.11.127 Discharge current temperature drift IDCHG32,TDrift -4% 4.5% 13% IDCHG = 32D 1)5) P_12.11.128 Discharge current temperature drift IDCHG48,TDrift -4% 3.5% 10% IDCHG = 48D 1)5) P_12.11.129 Discharge current temperature drift IDCHG63,TDrift -3.5% 3.5% 9.5% IDCHG = 63D 1)5) P_12.11.130 Charge current VS drift ICHG0,VsDrift 3% 4.5% 6% ICHG = 0D 1)6) P_12.11.131 1)6) P_12.11.132 Charge current VS drift ICHG8,VsDrift 4.5% 6% 7.5% ICHG = 8D Charge current VS drift ICHG16,VsDrift 4% 5.8% 7.5% ICHG = 16D 1)6) P_12.11.133 5.8% ICHG = 32D 1)6) P_12.11.134 ICHG = 48D 1)6) P_12.11.135 ICHG = 63D 1)6) P_12.11.136 1)6) P_12.11.137 P_12.11.138 Charge current VS drift Charge current VS drift Charge current VS drift ICHG32,VsDrift ICHG48,VsDrift ICHG63,VsDrift 2% -0.5% -2.3% 3.8% 2% 0.3% 4.5% 2.8% Discharge current VS drift IDCHG0,VsDrift -3% -1.5% 0% IDCHG = 0D Discharge current VS drift IDCHG8,VsDrift -3% -0.5% 2% IDCHG = 8D 1)6) Discharge current VS drift IDCHG16,VsDrift -3.3% -0.3% 2.3% IDCHG = 16D 1)6) P_12.11.139 1)6) P_12.11.140 Discharge current VS drift IDCHG32,VsDrift -2% 0% 2% IDCHG = 32D Discharge current VS drift IDCHG48,VsDrift -1.5% 0% 1.5% IDCHG = 48D 1)6) P_12.11.141 1.5% IDCHG = 63D 1)6) P_12.11.142 P_12.11.22 Discharge current VS drift IDCHG63,VsDrift -1.5% 0.2% 10 20 30 kΩ 1) Resistor between SHx and RSHGND GND 10 20 30 kΩ 1)7) P_12.11.23 Low RDSON mode – 22 35 Ω 1) P_12.11.24 Passive discharge resistance between GHx/GLx and GND RGGND RONCCP VS = 13.5 V VCP = VS + 14 V ICHG = IDCHG = 63D Gate Drivers Dynamic Parameters Datasheet 130 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Gate Drivers Table 36 Electrical characteristics: gate drivers (cont’d) VSINT = 5.5 V to 28 V, Tj = -40°C to +150°C, VCP > VS + 8.5 V, VS = 6 to 19V, all voltages with respect to ground, positive current flowing into pin except for IGLx and IGHx (unless otherwise specified). Parameter Symbol Values Min. Typ. Max. Unit Note or Test Condition 8) Number Gate Driver turn-on delay Time tDGDRV_ON1 – – 400 ns P_12.11.25 From PWM9) rising edge to 20% of ICHGx , x = 0 to 63, CLoad = 10 nF, BDFREQ = 0 Gate Driver turn-on delay Time tDGDRV_ON2 – – 300 ns 8) From PWM9) P_12.11.93 rising edge to 20% of ICHGx , x = 0 to 63, CLoad = 10 nF, BDFREQ = 1 30 50 ns 8) From 20% of ICHGx P_12.11.26 to ICHGx , x = 0 to 63, CLoad = 10 nF 8) Gate Driver current turn-on tGDRV_RISE(ON) – rise time Gate Driver turn-off delay Time tDGDRV_OFF1 – – 400 ns From PWM9) P_12.11.27 rising edge to 20% of IDCHGx , x = 0 to 63, CLoad = 10 nF, BDFREQ = 0 Gate Driver turn-off delay Time tDGDRV_OFF2 – – 300 ns 8) P_12.11.94 From PWM9) rising edge to 20% of IDCHGx , x = 0 to 63, CLoad = 10 nF, BDFREQ = 1 30 50 ns 8) From 20% of IDCHGx to IDCHGx , x = 0 to 63, CLoad = 10 nF P_12.11.28 Gate Driver current turn-off tGDRV_RISE(OFF – rise time ) External MOSFET gate-tosource voltage - ON VGS(ON)1 7 – – V 1) VS ≥ 8 V, FET_LVL=1 P_12.11.29 External MOSFET gate-tosource voltage - ON VGS(ON)1 7 – – V 1) VS ≥ 8 V, FET_LVL=1 P_12.11.102 External MOSFET gate-tosource voltage - ON VGS(ON)2 5.5 – – V 1) VS ≥ 8 V, FET_LVL=0 P_12.11.103 External MOSFET gate-tosource voltage - OFF VGS(OFF)1 – – 1.5 V 1) P_12.11.30 Datasheet 131 IDCHGx ≤ 24D(≤ 41 mA typ.) Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Gate Drivers Table 36 Electrical characteristics: gate drivers (cont’d) VSINT = 5.5 V to 28 V, Tj = -40°C to +150°C, VCP > VS + 8.5 V, VS = 6 to 19V, all voltages with respect to ground, positive current flowing into pin except for IGLx and IGHx (unless otherwise specified). Parameter Symbol Values Min. Typ. Max. Unit Note or Test Condition Number 1) External MOSFET gate-tosource voltage - OFF VGS(OFF)2 – – 5 V IDCHGx > 28D(> 41 mA typ.) P_12.11.101 PWM synchronization delay tPWM_SYNCH0 80 – 200 ns 1) BDFREQ = 0 P_12.11.33 PWM synchronization delay tPWM_SYNCH1 40 – 100 ns 1) BDFREQ= 1 P_12.11.82 Bridge driver frequency tBDFREQ0 16.8 18.75 20.7 MHz 1) BDFREQ= 0 P_12.11.83 Bridge driver frequency tBDFREQ1 33.7 37.5 42.3 MHz 1) BDFREQ= 1 P_12.11.84 Pre-charge time tPCHG000 80 107 140 ns 1) TPCHG = 000, BDFREQ= 0 or 1 P_12.11.34 Pre-charge time tPCHG001 130 160 190 ns 1) TPCHG = 001, BDFREQ= 0 or 1 P_12.11.35 Pre-charge time tPCHG010 170 214 260 ns 1) TPCHG = 010, BDFREQ= 0 or 1 P_12.11.36 Pre-charge time tPCHG011 210 267 330 ns 1) TPCHG = 011, BDFREQ= 0 or 1 P_12.11.37 Pre-charge time tPCHG100 250 320 390 ns 1) TPCHG = 100, BDFREQ= 0 or 1 P_12.11.85 Pre-charge time tPCHG101 420 533 630 ns 1) TPCHG = 101, BDFREQ= 0 or 1 P_12.11.86 Pre-charge time tPCHG110 600 747 900 ns 1) TPCHG = 110, BDFREQ= 0 or 1 P_12.11.87 Pre-charge time tPCHG111 840 1067 1260 ns 1) TPCHG = 111, BDFREQ= 0 or 1 P_12.11.88 Pre-discharge time tPDCHG000 80 107 140 ns 1) TPDCHG = 000, BDFREQ= 0 or 1 P_12.11.38 Pre-discharge time tPDCHG001 130 160 190 ns 1) TPDCHG = 001, BDFREQ= 0 or 1 P_12.11.39 Pre-discharge time tPDCHG010 170 214 260 ns 1) TPDCHG = 010, BDFREQ= 0 or 1 P_12.11.40 Pre-discharge time tPDCHG011 210 267 330 ns 1) TPDCHG = 011, BDFREQ= 0 or 1 P_12.11.41 Pre-discharge time tPDCHG100 250 320 390 ns 1) TPDCHG = 100, BDFREQ= 0 or 1 P_12.11.89 Pre-discharge time tPDCHG101 420 533 630 ns 1) TPDCHG = 101, BDFREQ= 0 or 1 P_12.11.90 Pre-discharge time tPDCHG110 600 747 900 ns 1) P_12.11.91 Datasheet 132 TPDCHG = 110, BDFREQ= 0 or 1 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Gate Drivers Table 36 Electrical characteristics: gate drivers (cont’d) VSINT = 5.5 V to 28 V, Tj = -40°C to +150°C, VCP > VS + 8.5 V, VS = 6 to 19V, all voltages with respect to ground, positive current flowing into pin except for IGLx and IGHx (unless otherwise specified). Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. 840 1067 1260 ns 1) TPDCHG = 111, BDFREQ= 0 or 1 P_12.11.92 4 4.8 µs 1) P_12.11.9 Pre-discharge time tPDCHG111 Discharge timeout tOFF_TIMEOUT 3.2 PWM_NB=1B Low-side gate driver, CP off - Slam mode, parking braking and VS overvoltage braking LS turn-on time, CP off tON_BRAKE – 4.5 9 µs CLOAD = 10 nF P_12.11.42 VGLx-VSL = 5 V, VS > 8 V or VSINT > 8 V LS turn-off time, CP off tOFF_BRAKE – 0.7 2 µs CLOAD = 10 nF P_12.11.43 VGLx-VSL = 1.5 V, VS > 8 V or VSINT > 8 V High output voltage GLx - SL VGLx_BRAKE 5 – 10 V VS > 8 V or VSINT > 8 V P_12.11.48 Charge Pump Frequency fCP – 250 – kHz 1) Output Voltage VCP vs. VS VCPmin1 8.5 – – V VS = 6 V, ICP = - 6 mA, P_12.11.50 FET_LVL =1 Output Voltage VCP vs. VS VCPmin2 7.5 – – V VS = 6 V, ICP = - 6 mA, P_12.11.51 FET_LVL =0 Regulated CP output voltage, VCP vs. VS VCP1 12 15 17 V 8 V < VS < 23 V ICP = - 12 mA11), CPSTGA = 0, FET_LVL =1 P_12.11.52 Regulated CP output voltage, VCP vs. VS VCP2 12 15 17 V 18 V < VS < 23 V ICP = - 12 mA11), CPSTGA = 1, FET_LVL =1 P_12.11.53 Regulated CP output voltage, VCP vs. VS VCP3 7.5 11 13 V 8 V < VS < 23 V ICP = - 12 mA11), CPSTGA = 0, FET_LVL =0 P_12.11.54 Regulated CP output voltage, VCP vs. VS VCP4 7.5 11 13 V 13 V < VS < 23 V ICP = - 12 mA11), CPSTGA = 0, FET_LVL =0 P_12.11.55 Turn-on time tON_VCP1 5 – 60 µs 1)10)11) Charge pump Datasheet 133 P_12.11.49 18 V VS + 8.5 V, VS = 6 to 19V, all voltages with respect to ground, positive current flowing into pin except for IGLx and IGHx (unless otherwise specified). Parameter Symbol Values Min. Typ. Max. Unit Note or Test Condition 1)10)11) Number Rise time tRISE_VCP1 5 30 60 µs 18 V < VS < 23 P_12.11.57 V (25%-75%) ICP = 0 , CPSTGA = 1, FET_LVL =1 Turn-on time tON_VCP2 20 60 120 µs 1)10)11) 13 V < VS VS + 8.5 V, VS = 6 to 19V, all voltages with respect to ground, positive current flowing into pin except for IGLx and IGHx (unless otherwise specified). Parameter Symbol Values Min. Typ. Max. Unit Note or Test Condition Number Digital PWMx Inputs High Level Input Voltage Threshold VPWMH – – 0.7 × Vcc1 V – P_12.11.95 Low Level Input Voltage Threshold VPWML 0.3 × Vcc1 – – V – P_12.11.96 PWMx Input Hysteresis VPWM,hys – 0.12 × Vcc1 – V 1) P_12.11.97 PWMx Pull-down Resistance RPD_PWM 20 40 80 kΩ – P_12.11.98 kΩ 12) P_12.11.99 µs 1) P_12.11.105 CRC Select; Pin PWM1/CRC Config Pull-up Resistance Config Select Filter Time 100 RCFG tCFG_F 5 10 14 1) 2) 3) 4) 5) 6) 7) Not subject to production test, specified by design. Independent from CPSTGA. ICP = -12 mA for VS ≥ 8 V, ICP = 6 mA for VS = 6 V. VGS(ON) = VGS(ON)1 if FET_LVL = 1, VGS(ON) = VGS(ON)2 if FET_LVL = 0. Tj reference = 25°C Valid for VS = 8 to 19 V, VS reference = 13.5 V This resistance is the resistance between GHx and GND connected through a diode to SHx. As a consequence, the voltage at SHx can rise up to 0.6 V typ. before it is discharged through the resistor. 8) Not subject to production test, specified by design. 9) External PWM signal. 10) Parameter dependent on the capacitance CCP. 11) CCPC1 = CCPC2 = 220 nF, CCP = 470 nF. Other CCP values higher than 470 nF can be used. Note that this capacitor influences the charge pump rise and turn-on times, and the charge , VCP ripple voltage when charging the gate of a MOSFET. 12) Config Pull-up will be only active during startup-phase for checking external pull-down. After checking, the typ. 40 kΩ Pull-down resistance will be present. Datasheet 135 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Supervision Functions 12 Supervision Functions 12.1 Reset Function VCC1 RSTN Reset logic Incl. filter & delay Figure 64 Reset Block Diagram 12.1.1 Reset Output Description The reset output pin RSTN provides a reset information to the microcontroller, for example, in the event that the output voltage has fallen below the undervoltage threshold VRTx. In case of a reset event, the reset output RSTN is pulled to low after the filter time tRF and stays low as long as the reset event is present plus a reset delay time tRD1 or tRD2 depending on the value in RSTN_DEL. When connecting the device to battery voltage, the reset signal remains low initially. When the output voltage VCC1 has reached the reset default threshold VRT1,r, the reset output RSTN is released to high after the reset delay time tRD1. A reset can also occur due to a watchdog trigger failure. The reset threshold can be adjusted via SPI, the default reset threshold is VRT1,f. The RSTN pin has an integrated pull-up resistor. In case reset is triggered, it will be pulled low for VCC1 ≥ 1V and for VSINT ≥ VPOR,f (see also Chapter 12.3). The timings for the RSTN triggering regarding VCC1 undervoltage and watchdog trigger is shown in Figure 65. Datasheet 136 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Supervision Functions VCC1 VRT1 t < tRF The reset threshold can be configured via SPI in Normal Mode, default is VRT1 undervoltage tRD1 tCW tLW tCW SPI SPI Init tOW t tLW tOW WD Trigger tCW tRDx (config) WD Trigger SPI Init t tRF RSTN tLW= long open window tCW= closed window tOW= open window t Init Normal Restart Normal Reset_timing.vsd Figure 65 Reset Timing Diagram 12.1.2 Soft Reset Description In Normal Mode and Stop Mode, it is also possible to trigger a device internal reset via a SPI command in order to bring the device into a defined state in case of failures. In this case the microcontroller must send a SPI command and set the MODE bits to ‘11’ in the M_S_CTRL register. As soon as this command becomes valid, the device is set back to Init Mode and all SPI registers are set to their default values (see SPI Chapter 13.5.1 and Chapter 13.6.1). Two different soft reset configurations are possible via the SPI bit SOFT_RESET_RO: • SOFT_RESET_RO = ‘0’: The reset output (RSTN) is triggered when the soft reset is executed (default setting) The configured reset delay time tRD1 or tRD2 is applied depending on the value in RSTN_DEL). • SOFT_RESET_RO = ‘1’: The reset output (RSTN) is not triggered when the soft reset is executed. Note: The device must be in Normal Mode or Stop Mode when sending this command. Otherwise, the command will be ignored. Note: Allow CRC configuration after software-reset - or better check once again via SPI after software reset. Datasheet 137 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Supervision Functions 12.2 Watchdog Function The watchdog is used to monitor the software execution of the microcontroller and to trigger a reset or move the device to Fail Safe Mode, if the microcontroller stops serving the watchdog due to a lock up in the software. Two different types of watchdog functions are implemented and can be selected via the bit WD_CFG: • Time-Out Watchdog (default value) • Window Watchdog The respective watchdog functions can be selected and programmed in Normal Mode. The configuration stays unchanged in Stop Mode. Please refer to Table 37 to match the device modes with the respective watchdog modes. Table 37 Watchdog Functionality by modes Mode Watchdog Mode Remarks Init Mode Starts with Long Open Window Watchdog starts with Long Open Window after RSTN is released. Normal Mode WD Programmable Window Watchdog, Time-Out watchdog or switched off for Stop Mode. Stop Mode Watchdog is fixed or off Sleep Mode Off Device will start with Long Open Window when entering Normal Mode. Restart Mode Off Device will start with Long Open Window when entering Normal Mode. The watchdog timing is programmed via SPI command in the register WD_CTRL. As soon as the watchdog is programmed, the timer starts with the new setting and the watchdog must be served. The watchdog is triggered by sending a valid SPI-write command to the watchdog configuration register. The watchdog trigger command is executed when the SPI command is interpreted. When coming from Init Mode, Restart Mode or in certain cases from Stop Mode, the watchdog timer is always started with a long open window. The long open window (tLW) allows the microcontroller to run its initialization sequences and then to trigger the watchdog via SPI. The watchdog timer period can be selected via SPI (WD_TIMER).The timer setting is valid for both watchdog types. The following watchdog timer periods are available: • WD Setting 1: 10 ms • WD Setting 2: 20 ms • WD Setting 3: 50 ms • WD Setting 4: 100 ms • WD Setting 5: 200 ms • WD Setting 6: 500 ms • WD Setting 7: 1 s • WD Setting 8: 10 s In case of a reset, Restart Mode or Fail-Safe Mode is entered according to the configuration and the SPI bits WD_FAIL are set. Once the RSTN goes high again the watchdog immediately starts with a long open window the device enters automatically Normal Mode. The Watchdog behaviour in Software Development Mode is described in Chapter 5.4.7. Datasheet 138 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Supervision Functions In case a watchdog-trigger was missed in Software Development Mode, the watchdog will start with the longopen-window once again. The WD_FAIL bits will be set after a watchdog trigger failure. The WD_FAIL bits are cleared automatically when following conditions apply: • After a successful watchdog trigger. • When the watchdog is off: in Stop Mode after successfully disabling it, in Sleep Mode, or in Fail-Safe Mode (except for a watchdog failure). 12.2.1 Time-Out Watchdog The time-out watchdog is an easier and less secure watchdog than a window watchdog as the watchdog trigger can be done at any time within the configured watchdog timer period. A correct watchdog service immediately results in starting a new watchdog timer period. Taking the tolerances of the internal oscillator into account leads to the safe trigger area as defined in Figure 66. If the time-out watchdog period elapses, a watchdog reset is created by setting the reset output RSTN low and the device switches to Restart Mode or Fail-Safe Mode. Typical timout watchdog trigger period t WD x 1.50 open window uncertainty Watchdog Timer Period (WD_TIMER) tWD x 1.20 t / [tWD_TIMER] safe trigger area Figure 66 Datasheet t WD x 1.80 Time-out Watchdog Definitions 139 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Supervision Functions 12.2.2 Window Watchdog Compared to the time-out watchdog the characteristic of the window watchdog is that the watchdog timer period is divided between a closed and an open window. The watchdog must be triggered within the open window. A correct watchdog trigger results in starting the window watchdog period by a closed window followed by an open window. The watchdog timer period is at the same time the typical trigger time and defines the middle of the open window. Taking the oscillator tolerances into account leads to a safe trigger area of: tWD × 0.72 < safe trigger area < tWD × 1.20. The typical closed window is defined to a width of 60% of the selected window watchdog timer period. Taking the tolerances of the internal oscillator into account leads to the timings as defined in Figure 67. A correct watchdog service immediately results in starting the next closed window. If the trigger signal meet the closed window or if the watchdog timer period elapses, then a watchdog reset is triggered (RSTN low) and the device switches to Restart Mode or Fail-Safe Mode. tWD x 0.6 tWD x 0.9 Typ. closed window Typ. open window tWD x 0.48 closed window tWD x 0.72 uncertainty tWD x 1.0 open window tWD x 1.20 tWD x 1.80 uncertainty Watchdog Timer Period (WD_TIMER) t / [tWD _TIMER ] safe trigger area Figure 67 Window Watchdog Definitions 12.2.3 Watchdog Setting Check Sum A check sum bit is part of the SPI command to trigger the watchdog and to set the watchdog setting. The sum of the 16 data bits in the register WD_CTRL needs to have even parity (see Equation (12.1)). This is realized by either setting the bit CHECKSUM to 0 or 1. If the check sum is wrong, then the SPI command is ignored, i.e. the watchdog is not triggered or the settings are not changed and the bit SPI_FAIL is set. The written value of the reserved bits of the WD_CTRL register is considered (even if read as ‘0’ in the SPI output) for checksum calculation, i.e. if a 1 is written on the reserved bit position, then a 1 will be used in the checksum calculation. (12.1) Bit ( CHECKSUM ) = Bit22 ⊕ … ⊕ Bit8 Datasheet 140 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Supervision Functions 12.2.4 Watchdog during Stop Mode The watchdog can be disabled for Stop Mode in Normal Mode. For safety reasons, there is a special sequence to be followed in order to disable the watchdog as described in Figure 68. Two different SPI bits (WD_STM_EN_0, WD_STM_EN_1) in the registers HW_CTRL and WD_CTRL need to be set. Correct WD disabling sequence Sequence Errors Missing to set bit WD_STM_EN_0 with the next watchdog trigger after having set WD_STM_EN_1 Set bit WD_STM_EN_1 = 1 with next WD Trigger Staying in Normal Mode instead of going to Stop Mode with the next trigger Set bit WD_STM_EN_0 = 1 Before subsequent WD Trigger Will enable the WD: Change to Stop Mode Switching back to Normal Mode Triggering the watchdog WD is switched off Figure 68 Watchdog disabling sequence in Stop Mode If a sequence error occurs, then the bit WD_STM_EN_1 will be cleared and the sequence has to be started again. The watchdog can be enabled by triggering the watchdog in Stop Mode or by switching back to Normal Mode via SPI command. In both cases the watchdog will start with a long open window and the bits WD_STM_EN_1 and WD_STM_EN_0 are cleared. After the long open window the watchdog has to be served as configured in the WD_CTRL register. Note: The bit WD_STM_EN_0 will be cleared automatically when the sequence is started and it was 1 before. WD_STM_EN_0 can also not be set if WD_STM_EN_1 isn't yet set. 12.2.5 Watchdog Start in Stop Mode due to Bus Wake In Stop Mode the Watchdog can be disabled. In addition a feature is available which will start the watchdog with any BUS wake (CAN, ) during Stop Mode. The feature is enabled by setting the bit WD_EN_ WK_BUS = 1 (default value after POR). The bit can only be changed in Normal Mode and needs to be programmed before starting the watchdog disable sequence. A wake on the Bus will generate an interrupt and the RXDCAN, is pulled to low. By these signals the microcontroller is informed that the watchdog is started with a long open window. After the long open window the watchdog has to be served as configured in the WD_CTRL register. To disable the watchdog again, the device needs to be switched to Normal Mode and the sequence needs to be sent again. Datasheet 141 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Supervision Functions 12.3 VSINT Power On Reset At power up of the device, the Power on Reset is detected when VSINT > VPOR,r and the SPI bit POR is set to indicate that all SPI registers are set to POR default settings. VCC1 is starting up and the reset output will be kept low and will only be released once VCC1 has crossed VRT1,r and after tRD1 has elapsed. In case VSINT < VPOR,f, an device internal reset will be generated and the device is switched off and will restart in Init Mode at the next VSINT rising. This is shown in Figure 69. VSINT VPOR,r VPOR,f t VCC1 VRT1,r The reset threshold can be configured via SPI in Normal Mode, default is VRT1 VRTx,f t RSTN Restart Mode is entered whenever the Reset is triggered t tRD1 Mode OFF INIT MODE Any MODE Restart OFF t SPI Command Figure 69 Datasheet Ramp up / down example of Supply Voltage 142 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Supervision Functions 12.4 VSINT Under- and Overvoltage 12.4.1 VSINT Undervoltage The VSINT under-voltage monitoring is always active in Init Mode, Restart Mode, Normal Mode. If the supply voltage VSINT drops below VSINT,UV for more than tVSUV_FILT, then the device does the following measures: • The VCC1 short circuit diagnosis becomes inactive (see Chapter 12.8). However, the thermal protection of the device remains active. If the undervoltage threshold is exceeded (VSINT rising) then the function will be automatically enabled again. • The status bit VSINT_UV is set and latched until a clear command of SUP_STAT is received. Note: VSINT under-voltage monitoring is not available in Stop Mode due to current consumption saving requirements except if the VCC1 load current is above the active peak threshold (I_PEAK_TH) or if VCC1 is below the VCC1 prewarning threshold. 12.4.2 VSINT Overvoltage The VSINT over-voltage monitoring is always active in Init Mode, Restart Mode and Normal Mode. If VSINT rises above VS,OVD1, VS,OVD2 for more than tVSOV_FILT then the device does the following measures: 1. If HBxMODE = 01b or 10b , then the corresponding MOSFETs are actively turned off with their static discharge current during their respective tHBxCCP Active. 2. Then the charge pump is turned off and the passive discharge is activated. 3. The status bits VSINT_OV is set and latched until a clear command of SUP_STAT is received. If VS or VSINT fall below VS,OVD1 or VS,OVD2: • If CPEN = 0 : the charge pumps stays and the bridge driver stay off. • If CPEN = 1 : – If BDOV_REC = 0 : Then the charge pump is reactivated but the bridge driver stays off until VS_OV and VSINT_OV are cleared. The current sense amplifier is reactivated (provided that CSA_OFF = 0) – If BDOV_REC = 1 : Then the charge pump and the current sense amplifier are reactivated and the bridge driver is enabled if VCP > VCPUVx, even if VS_OV or VSINT_OV is set. The state of the external MOSFETs is according to the control registers. Datasheet 143 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Supervision Functions 12.5 VS Under- and Overvoltage 12.5.1 VS Undervoltage The VS under-voltage monitoring is always active in Init-, Restart Mode and Normal Mode. If VS drops below VS,UV for more than tVSUV_FILT, then the device does the following measures: 1. If HBxMODE = 01b or 10b , then the corresponding MOSFETs are actively turned off with their static discharge current during their respective tHBxCCP Active. 2. Then the charge pump is turned off and the passive discharge is activated and the current sense amplifier is turned off. 3. The status bits VS_UV is set and latched until a clear command of SUP_STAT is received. If VS rises above VS,UV, then the charge pump is reactivated (provided that CPEN is set) and the current sense amplifier is reactivated (provided CSA_OFF = 0) but the bridge driver stays off until VS_UV is cleared. The bridge driver will be reactivated once the VS_UV bit is cleared. 12.5.2 VS Overvoltage The VS over-voltage monitoring is always active in Init-, Restart Mode and Normal Mode or when the charge pump is enabled. If VS rises above VS,OVD1 or VS,OVD2 for more than tVSOV_FILT, then the device does the following measures: 1. If HBxMODE = 01b or 10b , then the corresponding MOSFETs are actively turned off with their static discharge current during their respective tHBxCCP Active. 2. Then the charge pump is turned off and the passive discharge is activated and current sense amplifier is turned off . 3. The status bits VS_OV is set and latched until a clear command of SUP_STAT is received. If VS and VSINT fall below VS,OVD1 or VS,OVD2: • If CPEN = 0 : the charge pumps and the bridge driver stay off. • If CPEN = 1 : – If BDOV_REC = 0 : Then the charge pump is reactivated but the bridge driver stays off until VS_OV and VSINT_OV are cleared. The current sense amplifier is reactivated provided that CSA_OFF = 0 – If BDOV_REC = 1 : Then the charge pump and the current sense amplifier are reactivated and the bridge driver is enabled if VCP > VCPUVx, even if VS_OV or VSINT_OV is set. The state of the external MOSFETs is according to the control registers. Datasheet 144 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Supervision Functions 12.6 VS Under- Overvoltage for high-side 12.6.1 VS Undervoltage for high-side If the supply voltage VS passes below the undervoltage threshold (VSHS,UVD) the device does the following measures: • HS1...3 are acting accordingly to the SPI setting (refer also to Chapter 7.2.1). • SPI bit HS_UV is set. No other error bits are set. The bit can be cleared once the condition is not present anymore. 12.6.2 VS Overvoltage for high-side If the supply voltage VSHS reaches the overvoltage threshold (VSHS,OVD) the device triggers the following measures: • HS1...3 are acting accordingly to the SPI setting (refer also to Chapter 7.2.2). • The status bit HS_OV is set. No other error bits are set. The bit can be cleared once the condition is not present anymore. Datasheet 145 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Supervision Functions 12.7 VCC1 Over-/ Undervoltage and Undervoltage Prewarning 12.7.1 VCC1 Undervoltage and Undervoltage Prewarning This function is always active when the VCC1 voltage regulator is enabled. A first-level voltage detection threshold is implemented as a prewarning for the microcontroller. The prewarning event is signaled with the bit VCC1_WARN. No other actions are taken. As described in Chapter 12.1 and Figure 70, a reset will be triggered (RSTN pulled low) when the VCC1 output voltage falls below the selected undervoltage threshold (VRTx). The device will enter Restart Mode and the bit VCC1_UV is set when RSTN is released again. The hysteresis of the VCC1 undervoltage threshold can be increased by setting the bit RSTN_HYS. In this case always the highest rising threshold (VRT1,R) is used for the release of the undervoltage reset. The falling reset threshold remains as configured. An additional safety mechanism is implemented to avoid repetitive VCC1 undervoltage resets due to high dynamic loads on VCC1: • A counter is increased for every consecutive VCC1 undervoltage event (regardless on the selected reset threshold). • The counter is active in Init Mode, Normal Mode and Stop Mode. • For VS < VSINT,UV the counter will be stopped in Normal Mode (i.e. the VS UV comparator is always enabled in Normal Mode). • A 4th consecutive VCC1 undervoltage event will lead to Fail-Safe Mode entry and to setting the bit VCC1_UV_FS. • This counter is cleared: – When Fail-Safe Mode is entered. – When the bit VCC1_UV is cleared. – When a Soft-Reset is triggered. Note: After 4 consecutive VCC1_UV events, the device will enter Fail-Safe Mode and the VCC1_UV_FS bit is set. Note: The VCC1_WARN or VCC1_UV bits are not set in Sleep Mode as VCC1 = 0 V in this case. VCC1 VRTx tRF t tRDx (config) RSTN t Normal Mode Figure 70 Datasheet Restart Mode Normal Mode VCC1 Undervoltage Timing Diagram 146 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Supervision Functions Note: It is recommended to clear the VCC1_WARN and VCC1_UV bit once it is detected by the microcontroller software to verify if the undervoltage still exists or not. 12.7.2 VCC1 Overvoltage For fail-safe reasons a configurable VCC1 over voltage detection feature is implemented. It is active when the VCC1 voltage regulator is enabled. In case the VCC1,OV,r threshold is crossed, the device triggers following measures depending on the configuration: • The bit VCC1_OV is always set. • Based on the configuration of VCC1_OV_MOD, different kind of event are generated from device. • If the VCC1_OV_MOD=11B, in case of the device enters in Fail Safe Mode. VCC1 VCC1,OV t tOV_filt RSTN tRDx (config) t Normal Mode Restart Mode Figure 71 VCC1 Over Voltage Timing Diagram 12.8 VCC1 Short Circuit Diagnostics Normal Mode The short circuit protection feature for VCC1 is implemented as follows: • The short circuit detection is only enabled if VS > VSINT,UV. • If VCC1 is not above the VRTx within tVCC1,SC after device power up or after waking from Sleep Mode or FailSafe Mode (i.e. after VCC1 is enabled) then the SPI bit VCC1_SC bit is set, VCC1 is turned off, the FO pin is enabled, FAILURE is set and Fail-Safe Mode is entered. The device can be activated again via a wake-up sources. • The same behavior applies, if VCC1 falls below VRTx for longer than tVCC1,SC. 12.9 VCAN Undervoltage An undervoltage warning is implemented for VCAN as follows: • VCAN undervoltage detection: In case the CAN module is enabled and the voltage on VCAN will drop below the VCAN_UV,f threshold, then the SPI bit VCAN_UV is set and can be only cleared via SPI. Datasheet 147 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Supervision Functions 12.10 Thermal Protection Three independent and different thermal protection features are implemented in the device according to the system impact: • Individual thermal shutdown of specific blocks • Temperature prewarning of VCC1 voltage regulator • Device thermal shutdown due to VCC1 overtemperature 12.10.1 Individual Thermal Shutdown As a first-level protection measure, CAN, HSx and the charge pump are independently switched off if the respective block reaches the temperature threshold TjTSD1. Then the TSD1 bit is set. This bit can only be cleared via SPI once the overtemperature is not present anymore. Independent of the device mode the thermal shutdown protection is only active if the respective block is ON. The respective modules behave as follows: • CAN: The transmitter is disabled and stays in CAN Normal Mode acting like CAN Receive Only Mode. The status bits CAN_FAIL are set to ‘01’. Once the overtemperature condition is not present anymore, then the CAN transmitter is automatically switched on. • HSx: If one or more HSx switches reach the TSD1 threshold, then the HSx switches are turned OFF (depending on configuration either individually or all at once) and the control bits for HSx are cleared based on HS_OT_SD_DIS setting. The status bits HSx_OT are set (see register HS_OL_OC_OT_STAT). Once the over temperature condition is not present anymore, then HSx has to be configured again by SPI. • Charge pump: If the charge pump reaches TjTSD1, then CP_OT is set, CPEN is cleared and the activated MOSFETs are actively discharged with their respective static currents during their respective active cross current protection times (tHBxCCP active). When all tHBxCCP active elapsed, then the charge pump and the MOSFETs active discharge are disabled and the current sense amplifier is deactivated. Once the over temperature condition is not present anymore, then CPEN has to be configured again by SPI. Note: The diagnosis bits are not cleared automatically and have to be cleared via SPI once the overtemperature condition is not present anymore. 12.10.2 Temperature Prewarning As a next level of thermal protection a temperature prewarning is implemented if the main supply VCC1 reaches the thermal prewarning temperature threshold TjPW. Then the status bit TPW is set. This bit can only be cleared via SPI once the overtemperature is not present anymore. 12.10.3 Thermal Shutdown As a highest level of thermal protection a temperature shutdown of the device is implemented if the main supply VCC1 reaches the thermal shutdown temperature threshold TjTSD2. Once a TSD2 event is detected FailSafe Mode is entered. Only when device temperature falls below the TSD2 threshold then the device remains in Fail-Safe Mode for tTSD2 to allow the device to cool down. After this time has expired, the device will automatically change via Restart Mode to Normal Mode (see also Chapter 5.4.6). When a TSD2 event is detected, then the status bit TSD2 is set. This bit can only be cleared via SPI in Normal Mode once the overtemperature is not present anymore. For increased robustness requirements it is possible to extend the TSD2 waiting time by 64x of tTSD2 after 16 consecutive TSD2 events by setting the SPI bit TSD2_DEL. The counter is incremented with each TSD2 event even if the bit TSD2 is not cleared. Once the counter has reached the value 16, then the bit TSD2_SAFE is set Datasheet 148 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Supervision Functions and the extended TSD2 waiting time is active. The extended waiting time will be kept until TSD2_SAFE is cleared. The TSD counter is cleared when TSD2 or TSD2_DEL is cleared. Note: In case a TSD2 overtemperature occurs while entering Sleep Mode then Fail-Safe Mode is still entered. Note: In case of a TSD2 event, the FAILURE bit is set to ‘1’ and the DEV_STAT field is set to ‘01’ inside the DEV_STAT register. Datasheet 149 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Supervision Functions 12.11 Bridge driver This section describes the supervision functions related to the bridge driver. 12.11.1 Bridge driver supervision with activated charge pump This section describes the supervision functions when the charge pump is activated. 12.11.1.1 Drain-source voltage monitoring Voltage comparators monitor the activated MOSFETs to protect high-side MOSFETs and low-side MOSFETs against a short circuit respectively to ground and to the battery during ON-state. A drain-source overvoltage is detected on a low-side MOSFET if the voltage difference between VSHx and SL exceeds the threshold voltage configured by LS_VDS (see Table 38). Consequently, the corresponding halfbridge is latched off with the static discharge current. A drain-source overvoltage is detected on a high-side MOSFET if the voltage difference between VS and VSHx exceeds the threshold voltage configured by HS_VDS (see Table 39). Consequently, the corresponding halfbridge is latched off with the static discharge current. Table 38 Low-side drain-source overvoltage threshold LSxVDSTH[2:0] Drain-Source overvoltage threshold for LSx (typical) 000B 160 mV 001B 200 mV (default) 010B 300 mV 011B 400 mV 100B 500 mV 101B 600 mV 110B 800 mV 111B 2V Table 39 High-side drain-source overvoltage threshold HSxVDSTH[2:0] Drain-Source overvoltage threshold for HSx (typical) 000B 160 mV 001B 200 mV (default) 010B 300 mV 011B 400 mV 100B 500 mV 101B 600 mV 110B 800 mV 111B 2V Attention: 2 V threshold is dedicated for the diagnostic in off-state. It is highly recommended to select another drain-source overvoltage threshold once the routine of the diagnostic in off-state has been performed to avoid additional current consumption from VS and from the charge pump. The device reports a Drain-Source overvoltage error if both conditions are met: Datasheet 150 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Supervision Functions • After expiration of the blank time . • If the Drain-Source voltage monitoring exceeds the configured threshold for a duration longer than the configured filter time (refer to Table 40 and LS_VDS TFVDS bits). Table 40 Drain-Source overvoltage filter time TFVDS[2:0] Drain-Source overvoltage filter time (typical) 00B 0.5 µs (default) 01B 1 µs 10B 2 µs 11B 6 µs If a short circuit is detected by the Drain-Source voltage monitoring: • The impacted half-bridge is latched off with the static discharge current for the configured cross-current protection time. • The corresponding bit in the status register DSOV is set. • The DSOV bit in Global Status Register GEN_STAT is set. If a Drain-Source overvoltage is detected for one of the MOSFETs, then the status register DSOV must be cleared in order to re-enable the faulty half-bridge. 12.11.1.2 Cross-current protection and drain-source overvoltage blank time All gate drivers feature a cross-current protection time and a Drain-Source overvoltage blank time. The cross-current protection avoids the simultaneous activation of the high-side and the low-side MOSFETs of the same half-bridge. During the blank time, the drain-source overvoltage detection is disabled, to avoid a wrong fault detection during the activation phase of a MOSFET. Note: The setting of the cross-current protection and of the blank times may be changed by the microcontroller only if all HBx_PWM_EN bits are reset. Note: Changing the Drain-Source overvoltage of a half-bridge x (HBx) in on-state (HBxMODE[1:0]=(0,1) or (1,0)) may result in a wrong VDS overvoltage detection on HBx. Therefore it is highly recommended to change this threshold when HBxMODE[1:0]=(0,0) or (1,1) 12.11.1.2.1 Cross-current protection The active and freewheeling cross-current protection times of each half-bridge is configured individually with the control register CCP_BLK. The typical cross-current protection time applied to the freewheeling MOSFET of the half-bridge x is 587 ns + 266 ns x TCCP[3:0]D, where TCCP[3:0]D is the decimal value of the control bits TCCP. 12.11.1.2.2 Drain-source overvoltage blank time A configurable blank time for the Drain-Source monitoring is applied at the turn-on of the MOSFETs. During the blank time, a Drain-Source overvoltage error is masked. Datasheet 151 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Supervision Functions For Half-Bridges in PWM mode with AFWx = 1: • the blank time of the PWM MOSFET starts at the expiration of the cross-current protection time of the PWM MOSFET. Refer to Figure 72. • the blank time of the free-wheeling MOSFET starts after expiration of the cross-current protection time at turn-off of the PWM MOSFET. Refer to Figure 72. PWM t IGS_PWM MOSFET tPCHGz Post-charge ICHGMAXz IPRECHGz tPDCHGz ICHGz t 0 - IDCHGz - IPREDCHGz tHBxCPP tBLANK for PWM MOSFET tHBxCPP for symmetrisation tHBxCPP IGS Freewheeling MOSFET ICHGMAXz t tBLANK for freewheeling MOSFET - ICHGMAXz Figure 72 Blank time for half-bridges in PWM operation with AFW = 1 For statically activated half-bridges, the blank time starts: • Case1: at expiration of the cross-current protection (Figure 42), if the opposite MOSFET was previously activated. • Case 2: right after the decoding of the SPI command to turn on a MOSFET, if the half-bridge was in high impedance (Figure 43). The blank times of the active and FW MOSFETs can be configured with the control register CCP_BLK. The typical blank is 587 ns + 266 ns x TBLK[3:0]D). Note: The blank time is implemented at every new activation of a MOSFET, including a recovery from VS undervoltage, VS overvoltage, VSINT overvoltage, CP UV, CP OT. 12.11.1.3 OFF-state diagnostic In order to support the off-state diagnostic (HBxMODE= 11 and CPEN = 1), the gate driver of each MOSFET provides pull-up (IPUDiag) and a pull-down currents (IPDDiag) at the SHx pins. This function requires an activated charge pump. The pull-up current source of a given half-bridge is on when the half-bridge is active: HBxMODE= 01, 10 or 11 and CPEN = 1. The pull-down current of each low-side gate driver is activated by the control bits HBx (HB_ICHG_MAX register). During the off-state diagnostic routine performed by the microcontroller, the drain-source overvoltage threshold of the relevant half-bridges must be set to 2V nominal. Refer to Table 38. Once the routine is finished, it is highly recommended to decrease the drain-source overvoltage threshold to a lower value, avoiding additional current consumption from the VS input. Datasheet 152 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Supervision Functions The following failures can be detected: • MOSFET short circuit to GND • MOSFET short circuit the battery • Open load (disconnected motor) The status of the output voltages VOUTx, can be read back with status bit HBxVOUT (register GEN_STAT) when the corresponding half-bridge is in off-state (HBxMODE[1:0] = 11). Note: HBxVOUT = 0 if the half-bridge x is not actively off (HBxMODE[1:0] = (0,0), (0,1) or (1,0) and CPEN=1) or when the charge pump is deactivated (CPEN=0). 12.11.1.4 Charge pump undervoltage The voltage of the charge pump output (VCP) is monitored in order to ensure a correct control of the external MOSFETs. The charge pump undervoltage threshold is configurable by the control bits FET_LVL and CPUVTH. Table 41 Charge pump undervoltage thresholds FET_LVL = 0 FET_LVL = 1 CPUVTH = 0 VCPUV1 (6 V typ. referred to VS) VCPUV3 (7.5 V typ. referred to VS) CPUVTH = 1 VCPUV2 (6.5 V typ. referred to VS) VCPUV4 (8 V typ. referred to VS) If VCP falls below the configured charge pump undervoltage threshold while CPEN = 1: • If one of the MOSFET is on, then all MOSFETs are actively turned off with their configured static discharge current during their respective tHBxCCP active. • Then the gate drivers are turned off and CSA is turned off . • CP_UV is set and latched. The CP_UV is reset and the normal operation is resumed once SUP_STAT is cleared and VCP > VCPUV. The charge pump undervoltage detection is blanked (tCPUVBLANK) during each new activation of the charge pump1). 12.11.1.5 Switching parameters of MOSFETs in PWM mode The effective switching parameters of the active MOSFETs (EN_GEN_CHECK=1), respectively PWM MOSFET (EN_GEN_CHECK=0)can be read out with dedicated status registers: • The turn-on and turn off delays, noted tDON and tDOFF are reported by the status register EFF_TDON_OFF1, EFF_TDON_OFF2, EFF_TDON_OFF3. • The rise and fall times, noted tRISE and tFALL, are reported by the status register TRISE_FALL1, TRISE_FALL2, TRISE_FALL3. 12.11.2 Low-side drain-source voltage monitoring during braking The low-side MOSFETs are turned-on while the charge pump is deactivated in the following conditions: • The slam mode is activated and PWM1/CRC is High. 1) Including CPEN set to 1, recovery from VS under/overvoltage, VSINT overvoltage and CP_ OT Datasheet 153 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Supervision Functions • The parking braking mode is activated and the device is in Sleep Mode or Stop Mode. • VS overvoltage brake is activated and (VS > VS Overvoltage braking or VSINT > VSINT Overvoltage braking) in all device modes if OV_BRK_EN is set. Under these conditions, the drain-source voltage of the low-sides are monitored and the applied drain-source overvoltage thresholds are according to VDSTH_BRK. The applied blank time, which starts at the beginning of the brake activation, is: • tBLK_BRAKE1 if TBLK_BRK = 0 • tBLK_BRAKE2 if TBLK_BRK = 1 During the blank time, a drain-source overvoltage of the low-sides is masked. The applied filter time is tFVDS_BRAKE. If a drain-source overvoltage is detected during braking , then all low-side MOSFETs are turned off (latched) within tOFF_BRAKE. SLAM_LSx_DIS (BRAKE, SLAM, PARK_BRK_EN, OV_BRK_EN are unchanged. The corresponding status bit LSxDSOV_BRK is set in DSOV. The low-sides can be reactivated only if all LSxDSOV_BRK bits (DSOV) are cleared (even in slam mode with the respective LSx disabled by the SLAM_LSx_DIS bit). If any of the status bits LSxDSOV_BRK is set, then the charge pump stays off (CPEN=1 command is accepted but the charge pump stays disabled until all LSxDSOV_BRK are cleared). 12.11.3 VS or VSINT Overvoltage braking The VS and VSINT overvoltage braking is activated if the OV_BRK_EN bit in BRAKE register is set regardless of the device mode. If VS, respectively VSINT, exceeds VOVBR,cfgx,r (x = 0 to 7), then all low-sides MOSFETs are turned-on within tON_BRAKE. The status bits VSOVBRAKE_ST, respectively VSINTOVBRAKE_ST, is set and latched (see DSOV register). If VS and VSINT decrease below VOVBR,cfgx,r - VHYS,cfgx (x = 0 to 7), then all low-sides MOSFETs are turned-off within tOFF_BRAKE after the filter time tOV_BR_FILT. If (VSHx - VSL) exceeds the configured threshold, then all low-sides MOSFETs are turned-off within tOFF_BRAKE after the filter time tFVDS_BRAKE. The threshold is: • VVDSMONTH0_BRAKE if VDSTH_BRK = 0 • VVDSMONTH1_BRAKE if VDSTH_BRK = 1 12.12 Current sense amplifier The current sense amplifier (CSA) allows current measurements with external shunt resistor in low-side configuration. The CSA is supplied by the charge pump (CP). Therefore, if the CP is off, then the CSA is deactivated. 12.12.1 Unidirectional and bidirectional operation The current sense amplifier (CSA) can work either as unidirectional or bi-directional operation. Refer to CSA register. Unidirectional operation CSD = 0 Datasheet 154 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Supervision Functions In unidirectional operation, the CSA is optimized to measure the current flowing through the external shunt resistor when VCSAP ≥ VCSAN. VCSO = VREF Unidir + (VCSAP - VCSAN + VOS) × GDIFF provided that VCSO is in the linear range1) 2). Bidirectional operation CSD = 1 In bidirectional operation, the CSA measures the current flowing through the external shunt resistor in both directions: VCSAP ≥ VCSAN or VCSAP ≤ VCSAN. The output CSO works at half-scale range: VCSO = VREF Bidir+ (VCSAP - VCSAN + VOS) × GDIFF, provided that VCSO is in the linear range 2). 12.12.2 Gain configuration The gain of the current sense amplifier is configurable by the configuration bits CSAG bits. Refer to Table 42. Table 42 Configuration of the current sense amplifier gain CSAG[1:0] Current sense amplifier gain GDIFF 00B GDIFF10 01B GDIFF20 10B GDIFF40 11B GDIFF60 12.12.3 Overcurrent Detection A comparator at CSO detects overcurrent conditions. The overcurrent threshold is configurable with the OCTH bits. Refer to Table 43 for unidirectional operation and Table 44 for bidirectional operation. Table 43 Overcurrent detection thresholds in unidirectional operation (CSD = 0) OCTH[1:0] Typical Overcurrent Detection Threshold 00B VCSO > VCC1/2 01B VCSO > VCC1 /2+ VCC1/10 10B VCSO > VCC1 /2+ 2 × VCC1/10 11B VCSO > VCC1/2 /2+ 3 × VCC1/10 1) Valid if 0.5 V ≤ VCSO ≤ VCC1 - 0.5 V. 2) VCSO is clamped between VCC1 and GND. Datasheet 155 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Supervision Functions VCSO CSO unidirectional overcurrent detection threshold VCC1 OCTH[1:0] VCC1 / 2 + 3 x VCC1 / 10 VOCTH4 Unidir (1,1) VCC1 / 2 + 2 x VCC1 / 10 VOCTH3 Unidir (1,0) VCC1 / 2 + VCC1 / 10 VOCTH2 Unidir (0,1) VCC1 / 2 VOCTH1 Unidir (0,0) VREF Unidir Typ. VCC1/5 0V Figure 73 Datasheet Overcurrent detection thresholds in unidirectional operation (CSD = 0) 156 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Supervision Functions Table 44 Overcurrent detection thresholds in bidirectional operation (CSD = 1) OCTHx[1:0] Typical Overcurrent Detection Threshold 00B VCSO > VCC1/2 + 2 × VCC1/20 or VCSO< VCC1/2 -2 × VCC1/20 01B VCSO > VCC1/2 + 4 × VCC1/20 or VCSO< VCC1/2 - 4 × VCC1/20 10B VCSO > VCC1/2+ 5 × VCC1/20 or VCSO< VCC1/2 - 5 × VCC1/20 11B VCSO > VCC1/2+ 6 × VCC1/20 or VCSO< VCC1/2 - 6 × VCC1/20 VCSO CSO bidirectional overcurrent detection threshold VCC1 OCTH[1:0] VCC1 / 2 + 6 x VCC1 / 20 VCC1 / 2 + 5 x VCC1 / 20 VCC1 / 2 + 4 x VCC1 / 20 VOCTH4 BidirH VOCTH3 BidirH VOCTH2 BidirH (1,1) (1,0) (0,1) VCC1 / 2 + 2 x VCC1 / 20 VOCTH1 BidirH (0,0) VCC1 / 2 - 2 x VCC1 / 20 VOCTH1 BidirL (0,0) VCC1 / 2 - 4 x VCC1 / 20 VCC1 / 2 - 5 x VCC1 / 20 VCC1 / 2 - 6 x VCC1 / 20 VOCTH2 BidirL (0,1) VOCTH3 BidirL (1,0) (1,1) VREF Bidir Typ. VCC1 /2 VOCTH4 BidirL 0V Figure 74 Overcurrent detection thresholds in bidirectional operation (CSD = 1) It is possible to program the device behavior when an overcurrent condition is detected: • OCEN bit = 0 (see CSA): the device only reports the overcurrent event ( bit is set), without any change of the gate driver states. • OCEN bit = 1 (see CSA): the device reports the overcurrent event ( bit is set) and actively turns off all MOSFETs with static discharge curent: – The MOSFETs can be reactivated by clearing OC_CSA or by resetting the OCEN bit. The overcurrent filter time is configurable (refer to tFOC) by the OCFILT control bits. tFOC refers to the output of the current sense amplifier. The CSO settling time (2 µs max, tSET) and the analog propagation delay (< 1 µs) are not taken into account by the overcurrent filter time. 12.12.4 CSO output capacitor The capacitor connected to CSO (CCSO) must be between 10 pF and 2.2 nF. The control bit CSO_CAP optimizes the current consumption for CCSO < 400 pF or 400 pF < CCSO < 2.2 nF1). Datasheet 157 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Supervision Functions 12.13 Electrical Characteristics Table 45 Electrical Characteristics VSINT = 5.5 V to 28 V; Tj = -40°C to +150°C; Normal Mode; all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified. Parameter Symbol Values Min. Typ. Max. Unit Note or Test Condition Number VCC1 Monitoring; VCC1 = 5.0V Version Undervoltage Prewarning Threshold Voltage PW,f VPW,f 4.53 4.70 4.84 V VCC1 falling, SPI bit is set P_13.12.1 Undervoltage Prewarning Threshold Voltage PW,r VPW,r 4.60 4.75 4.90 V VCC1 rising P_13.12.2 Undervoltage Prewarning Threshold Voltage hysteresis VPW,hys 30 50 90 mV 6) P_13.12.3 VCC1 UV Prewarning Detection Filter Time tVCC1,PW_F 5 10 14 us 2) rising and falling P_13.12.4 Reset Threshold Voltage RT1,f VRT1,f 4.45 4.6 4.75 V default setting; VCC1 falling P_13.12.5 Reset Threshold Voltage RT1,r VRT1,r 4.58 4.74 4.90 V default setting; VCC1 rising P_13.12.6 Reset Threshold Voltage RT2,f VRT2,f 3.70 3.85 4.00 V VCC1 falling P_13.12.7 Reset Threshold Voltage RT2,r VRT2,r 3.85 4.0 4.15 V VCC1 rising P_13.12.8 Reset Threshold Voltage RT3,f VRT3,f 3.24 3.40 3.55 V VS ≥ 4 V; VCC1 falling P_13.12.9 Reset Threshold Voltage RT3,r VRT3,r 3.39 3.54 3.70 V VS ≥ 4 V; VCC1 rising P_13.12.10 Reset Threshold Voltage RT4,f VRT4,f 2.49 2.65 2.8 V VS ≥ 4 V; VCC1 falling P_13.12.11 Reset Threshold Voltage RT4,r VRT4,r 2.65 2.76 2.95 V VS ≥ 4 V; VCC1 rising P_13.12.12 Reset Threshold Hysteresis VRT,hys 70 140 220 mV 6) P_13.12.13 VCC1 Over Voltage Detection Threshold Voltage VCC1,OV,r 5.5 5.65 5.8 V 1)6) VCC1 Over Voltage Detection Threshold Voltage VCC1,OV,f 5.4 5.55 5.7 V 6) VCC1 OV Detection Filter Time tVCC1,OV_F 51 64 80 us 2) rising VCC1 P_13.12.26 falling VCC1 P_13.12.27 P_13.12.31 1) for 400 pF < CCSO < 2.2 nF, a seial resistor of min. 45 Ohm between the CSO pin and the CCSO capacitor is required, Datasheet 158 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Supervision Functions Table 45 Electrical Characteristics (cont’d) VSINT = 5.5 V to 28 V; Tj = -40°C to +150°C; Normal Mode; all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified. Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. tVCC1,SC 3.2 4 4.8 ms 2) blanking time during power-up, short circuit detection for VS ≥ VS,UV P_13.12.32 VRSTN,L – 0.2 0.4 V IRSTN = 1 mA for VCC1 ≥ 1 V & VS ≥ VPOR,f P_13.12.33 Reset High Output Voltage VRSTN,H 0.8 x VCC1 – VCC1 + 0.3 V V IRSTN = -20 µA P_13.12.34 Reset Pull-up Resistor RRSTN 10 20 40 kΩ P_13.12.35 Reset Filter Time tRF 4 10 26 µs VRSTN = 0 V 2) VCC1 < VRT1x tRD1 8 VCC1 Short to GND Filter Time Reset Generator; Pin RSTN Reset Low Output Voltage Reset Delay Time 1 P_13.12.36 to RSTN = L see also Chapter 12.3 10 12 ms 2) RSTN_DEL = 0 P_13.12.37 RSTN_DEL = 1 P_13.12.64 tRD2 1.6 2 2.4 ms 2) VCAN_UV,f 4.5 – 4.75 V VCAN falling P_13.12.38 CAN Supply undervoltage VCAN_UV,r detection threshold (rising) 4.6 – 4.85 V VCAN rising P_13.12.39 VCAN Undervoltage detection hysteresis VCAN,UV, hys 50 90 130 mV 6) P_13.12.40 VCAN UV detection Filter Time tVCAN,UV_F 5 10 14 µs 2) Reset Delay Time 2 VCAN Monitoring CAN Supply undervoltage detection threshold (falling) VCAN rising and P_13.12.41 falling Watchdog Generator / Internal Oscillator Long Open Window tLW 160 200 240 ms 2) P_13.12.42 Internal Clock Generator Frequency fCLKSBC,1 0.8 1.0 1.2 MHz – P_13.12.43 100 120 ms 2)3) P_13.12.45 Minimum Waiting time during Fail-Safe Mode Min. waiting time Fail-Safe tFS,min 80 Power-on Reset, Over / Undervoltage Protection VSINT Power on reset rising VPOR,r – – 4.5 V VSINT increasing P_13.12.46 VSINT Power on reset falling – – 3 V VSINT decreasing P_13.12.47 Datasheet VPOR,f 159 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Supervision Functions Table 45 Electrical Characteristics (cont’d) VSINT = 5.5 V to 28 V; Tj = -40°C to +150°C; Normal Mode; all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified. Parameter Symbol Values Min. Typ. Max. Unit Note or Test Condition Number VSINT Undervoltage Detection Threshold VSINT,UV 5.3 – 6.0 V P_13.12.48 Supply UV threshold for VCC1 SC detection; hysteresis included; includes rising and falling threshold VSHS Overvoltage Detection Threshold VSHS,OVD 20 – 22 V Supply OV supervision for HSx; hysteresis included P_13.12.55 VSHS Overvoltage Detection hysteresis VSHS,OVD,hys 100 500 – mV 6) P_13.12.56 VSHS Undervoltage Detection Threshold VSHS,UVD 4.8 – 5.5 V Supply UV supervision for HSx; hysteresis included P_13.12.57 VSHS Undervoltage Detection hysteresis VSHS,UVD,hys 50 200 350 mV 6) P_13.12.58 VSHS Undervoltage Detection Filter Time tVSHS,UV 5 10 14 us 2) rising and falling P_13.12.300 VSHS Overvoltage Detection Filter Time tVSHS,OV 5 10 14 us 2) rising and falling P_13.12.301 Charge Pump Undervoltage Charge Pump Undervoltage Referred to VS VCPUV1 5.4 5.9 6.4 V FET_LVL = 0 CPUVTH = 0 falling threshold, VS ≥6 V P_13.12.59 Charge Pump Undervoltage Referred to VS VCPUV2 5.85 6.35 6.85 V FET_LVL = 0 CPUVTH = 1 falling threshold, VS ≥ 6 V P_13.12.60 Charge Pump Undervoltage Referred to VS VCPUV3 6.85 7.35 7.85 V FET_LVL = 1 CPUVTH = 0 falling threshold, VS ≥ 6 V P_13.12.61 Datasheet 160 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Supervision Functions Table 45 Electrical Characteristics (cont’d) VSINT = 5.5 V to 28 V; Tj = -40°C to +150°C; Normal Mode; all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified. Parameter Symbol Values Min. Typ. Max. Unit Note or Test Condition Number Charge Pump Undervoltage Referred to VS VCPUV4 7.5 8 8.5 V FET_LVL = 1 CPUVTH = 1 falling threshold, VS ≥ 6 V P_13.12.62 Charge Pump Undervoltage Filter Time tCPUV 51 64 80 µs 6) VS ≥ 6 V P_13.12.63 Charge Pump Undervoltage Blank Time tCPUVBLANK 400 500 600 µs 6) VS ≥ 6 V P_13.12.175 VS undervoltage threshold VS,UV 4.7 – 5.4 V hysteresis included P_13.12.66 VS overvoltage threshold detection 1 VS,OVD1 19 – 22.5 V hysteresis included, VS_OV_SEL = 0 P_13.12.68 VS overvoltage threshold detection 2 VS,OVD2 27.75 – 31.25 V hysteresis included, VS_OV_SEL = 1 P_13.12.65 5 10 14 µs 2) rising and falling P_13.12.71 rising and falling P_13.12.72 VS monitoring VS undervoltage filter time tVSUV_FILT VS overvoltage filter time tVSOV_FILT 5 10 14 µs 2) Off-state open load diagnosis Pull-up diagnosis current IPUDiag -600 -400 -270 µA VS ≥ 6 V P_13.12.73 Pull-down diagnosis current IPDDiag 1600 2200 2800 µA VS ≥ 6 V P_13.12.74 Diagnosis current ratio IDiag_ratio 4.25 5.25 6.25 Ratio IPDDiag / IPUDiag P_13.12.302 Drain-source monitoring CP activated Blank time tBLANK typ20% 587 typ+20 ns +266 % xTBLK 6) Cross-current protection time tCCP typ20% 587 typ+20 ns +266 % xTCCP 6) HS/LS Drain-source overvoltage 0 VVDSMONTH0_ 0.115 0.16 0.195 V VDSTH[2:0] = 000B, P_13.12.77 VS≥6 V, TFVDS=00B 0.2 0.25 V VDSTH[2:0] = 001B, P_13.12.78 VS≥6 V, TFVDS=00B 0.3 0.36 V VDSTH[2:0] = 010B, P_13.12.79 VS≥6 V, TFVDS=00B CPON HS/LS Drain-source overvoltage 1 VVDSMONTH1_ 0.16 HS/LS Drain-source overvoltage 2 VVDSMONTH2_ 0.24 Datasheet CPON CPON 161 TBLK: decimal P_13.12.75 value of TBLK[3:0], VS ≥ 6 V TCCP: decimal value of TCCPx[3:0], VS ≥ 6 V P_13.12.76 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Supervision Functions Table 45 Electrical Characteristics (cont’d) VSINT = 5.5 V to 28 V; Tj = -40°C to +150°C; Normal Mode; all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified. Parameter Symbol Values Min. HS/LS Drain-source overvoltage 3 VVDSMONTH3_ 0.32 HS/LS Drain-source overvoltage 4 VVDSMONTH4_ 0.4 HS/LS Drain-source overvoltage 5 VVDSMONTH5_ 0.48 HS/LS Drain-source overvoltage 6 VVDSMONTH6_ 0.64 HS/LS Drain-source overvoltage 7 VVDSMONTH7_ 1.75 Unit Note or Test Condition Number Typ. Max. 0.4 0.48 V VDSTH[2:0] = 011B, P_13.12.80 VS≥6 V, TFVDS=00B 0.5 0.6 V VDSTH[2:0] = 100B, P_13.12.81 VS≥6 V, TFVDS=00B 0.6 0.72 V VDSTH[2:0] = 101B, P_13.12.82 VS≥6 V, TFVDS=00B 0.8 0.96 V VDSTH[2:0] = 110B, P_13.12.83 VS≥6 V, TFVDS=00B 2.0 2.25 V VDSTH[2:0] = 111B, P_13.12.84 VS≥6 V, TFVDS=00B CPON CPON CPON CPON CPON Drain-Source monitoring - Slam mode, parking braking and VS overvoltage braking, VS or VSINT ≥ 8V Blank time tBLK_BRAKE1 4.5 7 9.5 µs TBLK_BRK = 0, VS or VSINT ≥ 8 V P_13.12.85 Blank time tBLK_BRAKE2 9 11 13 µs TBLK_BRK = 1, VS or VSINT ≥ 8 V P_13.12.86 VDS Filter time tFVDS_BRAKE 0.5 1 2.5 µs VS or VSINT ≥ 8 V P_13.12.87 LS Drain-source monitoring thresholds VVDSMONTH0_ 0.56 0.8 1.05 V VS or VSINT ≥ 8 V VDSTH_BRK = 0 P_13.12.89 LS Drain-source monitoring thresholds VVDSMONTH1_ 0.15 0.22 0.29 V VS or VSINT ≥ 8 V VDSTH_BRK = 1 P_13.12.90 BRAKE BRAKE VS Overvoltage Braking Mode VS Overvoltage braking config 0 rising VOVBR,cfg0,r 25.65 27 28.35 V OV_BRK_TH=000B P_13.12.97 VS Overvoltage braking config 1 rising VOVBR,cfg1,r 26.60 28 29.40 V OV_BRK_TH=001B P_13.12.98 VS Overvoltage braking config 2 rising VOVBR,cfg2,r 27.55 29 30.45 V OV_BRK_TH=010B P_13.12.99 VS Overvoltage braking config 3 rising VOVBR,cfg3,r 28.50 30 31.50 V OV_BRK_TH=011B P_13.12.100 VS Overvoltage braking config 4 rising VOVBR,cfg4,r 29.45 31 32.55 V OV_BRK_TH=100B P_13.12.101 VS Overvoltage braking config 5 rising VOVBR,cfg5,r 30.40 32 33.60 V OV_BRK_TH=101B P_13.12.102 VS Overvoltage braking config 6 rising VOVBR,cfg6,r 31.35 33 34.65 V OV_BRK_TH=110B P_13.12.103 VS Overvoltage braking config 7 rising VOVBR,cfg7,r 32.30 34 35.70 V OV_BRK_TH=111B P_13.12.104 VS Overvoltage braking config 0 VHYS,cfg0 0.64 0.75 0.85 V OV_BRK_TH=000B P_13.12.105 Datasheet 162 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Supervision Functions Table 45 Electrical Characteristics (cont’d) VSINT = 5.5 V to 28 V; Tj = -40°C to +150°C; Normal Mode; all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified. Parameter Symbol Values Min. Typ. Max. Unit Note or Test Condition Number VS Overvoltage braking config 1 VHYS,cfg1 0.74 0.82 0.9 V OV_BRK_TH=001B P_13.12.109 VS Overvoltage braking config 2 VHYS,cfg2 0.80 0.89 0.98 V OV_BRK_TH=010B P_13.12.113 VS Overvoltage braking config 3 VHYS,cfg3 0.85 0.95 1.05 V OV_BRK_TH=011B P_13.12.117 VS Overvoltage braking config 4 VHYS,cfg4 0.93 1.03 1.13 V OV_BRK_TH=100B P_13.12.121 VS Overvoltage braking config 5 VHYS,cfg5 0.97 1.08 1.19 V OV_BRK_TH=101B P_13.12.125 VS Overvoltage braking config 6 VHYS,cfg6 1.03 1.15 1.27 V OV_BRK_TH=110B P_13.12.129 VS Overvoltage braking config 7 VHYS,cfg7 1.1 1.23 1.36 V OV_BRK_TH=111B P_13.12.133 VS and VSINT overvoltage braking filter time tOV_BR_FILT 10 15 20 µs 6) Operating common mode input voltage range referred to GND (CSAP GND) or (CSAN- GND) VCM -2.0 – 2.0 V Common Mode Rejection Ratio CMRR 63 69 75 77 – – – – – – – – dB 6) CSAG = (0,0) CSAG = (0,1) CSAG = (1,0) CSAG = (1,1) DC to 50 kHz VCM = -2 … 2 V VCSAP = VCSAN P_13.12.139 Settling time to 98% tSET – 1500 2000 ns 6) P_13.12.140 6) P_13.12.141 P_13.12.200 Current sense amplifier4) P_13.12.138 Settling time to 98% after gain change tSET_GAIN – – 5000 ns Input Offset voltage VOS -1 0 1 mV Current Sense Amplifier DC GDIFF10 Gain (uncalibrated) 9.91 10.04 10.17 V/V CSAG = (0,0) P_13.12.143 Current Sense Amplifier DC GDIFF20 Gain (uncalibrated) 19.79 20.05 20.31 V/V CSAG = (0,1) P_13.12.144 Current Sense Amplifier DC GDIFF40 Gain (uncalibrated) 39.53 40.05 40.57 V/V CSAG = (1,0) P_13.12.145 Datasheet 163 After gain change from CSN rising edge P_13.12.142 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Supervision Functions Table 45 Electrical Characteristics (cont’d) VSINT = 5.5 V to 28 V; Tj = -40°C to +150°C; Normal Mode; all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified. Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. Current Sense Amplifier DC GDIFF60 Gain (uncalibrated) 59.34 60.12 60.91 V/V CSAG = (1,1) P_13.12.146 Gain drift GDRIFT -0.5 – 0.5 % 6) Gain drift after calibration P_13.12.151 CSO single ended output voltage range (linear range) VCSO 0.5 – VCC1 0.5 V 6) P_13.12.152 Reference voltage for unidirectional CSAx VREF Unidir -1.25% VCC1/5 +1.25% V CSD = 0 VCSAP = VCSAN P_13.12.153 Reference voltage for bidirectional CSAx VREF Bidir -1% VCC1/2 +1% V CSD = 1 VCSAP = VCSAN P_13.12.154 Overcurrent filter time tFOC 4 7 40 80 6 10 50 100 8 13 60 120 µs 5)6) OCFILT = 00B OCFILT = 01B OCFILT = 10B OCFILT = 11B P_13.12.155 OC threshold, unidirectional VOCTH1 Unidir -4% VCC1/2 +4% V CSD = 0, OCTH[1:0]= 00B P_13.12.156 OC threshold, unidirectional VOCTH2 Unidir -4% VCC1/2 +4% + VCC1/10 V CSD = 0, OCTH[1:0]= 01B P_13.12.157 OC threshold, unidirectional VOCTH3 Unidir -4% VCC1/2 +4% + 2x VCC1/1 0 V CSD = 0, OCTH[1:0]= 10B P_13.12.158 OC threshold, unidirectional VOCTH4 Unidir -4% VCC1/2 +4% + 3x VCC1/10 V CSD = 0, OCTH[1:0]= 11B P_13.12.159 High OC threshold, bidirectional VOCTH1 BidirH -4% VCC1/2 +4% + 2x VCC1/20 V CSD = 1, OCTH[1:0]= 00B P_13.12.160 High OC threshold, bidirectional VOCTH2 BidirH -4% VCC1/2 +4% + 4x VCC1/20 V CSD = 1, OCTH[1:0]= 01B P_13.12.161 High OC threshold, bidirectional VOCTH3 BidirH -4% VCC1/2 +4% + 5x VCC1/20 V CSD = 1, OCTH[1:0]= 10B P_13.12.162 High OC threshold, bidirectional VOCTH4 BidirH -4% VCC1/2 +4% + 6x VCC1/20 V CSD = 1, OCTH[1:0]= 11B P_13.12.163 Overcurrent detection Datasheet 164 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Supervision Functions Table 45 Electrical Characteristics (cont’d) VSINT = 5.5 V to 28 V; Tj = -40°C to +150°C; Normal Mode; all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified. Parameter Symbol Values Min. Typ. Unit Note or Test Condition Number Max. Low OC threshold, bidirectional VOCTH1 BidirL -4% VCC1/2 - +4% 2x VCC1/20 V CSD = 1, OCTH[1:0]= 00B P_13.12.164 Low OC threshold, bidirectional VOCTH2 BidirL -4% VCC1/2 - +4% 4x VCC1/20 V CSD = 1, OCTH[1:0]= 01B P_13.12.165 Low OC threshold, bidirectional VOCTH3 BidirL -4% VCC1/2 - +4% 5x VCC1/20 V CSD = 1, OCTH[1:0]= 10B P_13.12.166 Low OC threshold, bidirectional VOCTH4 BidirL -4% VCC1/2 - +4% 6x VCC1/20 V CSD = 1, OCTH[1:0]= 11B P_13.12.167 60 – – dB 6) VCP modulated with sinewave (100 kHz, 1 Vpp P_13.12.168 Current Sense Amplifier Dynamic Parameters Power Supply Rejection Ratio PSRR Overtemperature Shutdown6) Thermal Prewarning Temperature TjPW 125 145 165 °C Tj rising P_13.12.169 Thermal Shutdown TSD1 TjTSD1 170 185 200 °C Tj rising P_13.12.170 Thermal Shutdown TSD2 TjTSD2 170 185 200 °C P_13.12.171 Thermal Shutdown hysteresis TjTSD,hys – 25 – °C Tj rising 6) TSD/TPW Filter Time tTSD_TPW_F 5 10 15 us rising and falling, P_13.12.173 applies to all thermal sensors (TPW, TSD1, TSD2) Deactivation time after thermal shutdown TSD2 tTSD2 0.8 1 1.2 s 2) P_13.12.172 P_13.12.174 1) It is ensured that the threshold VCC1,OV,r is always higher than the highest regulated VCC1 output voltage VCC1,out4. . 2) Not subject to production test, tolerance defined by internal oscillator tolerance. 3) This time applies for all failure entries except a device thermal shutdown (TSD2 has a typ. 1 s waiting time tTSD2). 4) 6 V ≤ VS ≤ 23 V 5) tFOC refers to the output of the current sense amplifier. The CSO settling time (2 µs max, tSET) and the analog propagation delay (< 1 µs)are not taken into account by the overcurrent filter time. 6) Not subject to production test, specified by design. Datasheet 165 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Serial Peripheral Interface 13 Serial Peripheral Interface The Serial Peripheral Interface is the communication link between the device and the microcontroller. The TLE9563-3QX is supporting multi-slave operation in full-duplex mode with 32-bit data access. The SPI behavior for the different device modes is as follows: • The SPI is enabled in Init Mode, Normal Mode and Stop Mode. • The SPI is OFF in Sleep Mode, Restart Mode and Fail-Safe Mode. 13.1 SPI Block Description The Control Input Word is read via the data input SDI, which is synchronized with the clock input CLK provided by the microcontroller. The output word appears synchronously at the data output SDO (see Figure 75 with a 32-bit data access example). The transmission cycle begins when the chip is selected by the input CSN (Chip Select Not), LOW active. After the CSN input returns from LOW to HIGH, the word that has been read is interpreted according to the content. The SDO output switches to tristate status (high impedance) at this point, thereby releasing the SDO bus for other use.The state of SDI is shifted into the input register with every falling edge on CLK. The state of SDO is shifted out of the output register after every rising edge on CLK. The SPI of the device is not daisy chain capable. CSN high to low: SDO is enabled. Status information transferred to output shift register CSN time CSN low to high: data from shift register is transferred to output functions CLK time Actual data LSB SDI 0 1 2 3 4 5 6 MSB 27 28 29 30 31 New data 0 1 + + time SDI: will accept data on the falling edge of CLK signal LSB SDO Actual status ERR 0 1 2 3 4 5 6 - MSB 27 28 29 30 31 New status ERR 0 + 1 + time SDO: will change state on the rising edge of CLK signal Figure 75 Datasheet SPI Data Transfer Timing (note the reversed order of LSB and MSB shown in this figure compared to the register description) 166 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Serial Peripheral Interface 13.2 Failure Signalization in the SPI Data Output When the microcontroller sends a wrong SPI command to the device, the device ignores the information. Wrong SPI commands are either invalid device mode commands or commands which are prohibited by the state machine to avoid undesired device or system states (see below). In this case the diagnosis bit SPI_FAIL is set and the SPI Write command is ignored (no partial interpretation). This bit can be only reset by actively clearing it via a SPI command. Invalid SPI Commands leading to SPI_FAIL are listed below (in this case the SPI command is ignored): • Illegal state transitions: - Going from Stop Mode to Sleep Mode. In this case the device enters Restart Mode. - Trying to go to Stop Mode or Sleep Mode from Init Mode1). In this case Normal Mode is entered. • Uneven parity in the data bit of the WD_CTRL register. In this case the watchdog trigger is ignored and/or the new watchdog settings are ignored respectively. • In Stop Mode: attempting to change any SPI settings, e.g. changing the watchdog configuration, PWM settings and HSx configuration settings during Stop Mode, etc.; the SPI command is ignored in this case; only WD trigger, returning to Normal Mode, triggering a device soft reset, and read & clear status registers commands are valid SPI commands in Stop Mode; Note: No failure handling is done for the attempt to go to Stop Mode when all bits in the registers BUS_CTRL and WK_CTRL are cleared because the microcontroller can leave this mode via SPI. • When entering Stop Mode and WK_STAT is not cleared; SPI_FAIL will not be set but the INTN pin will be triggered. • Changing from Stop Mode to Normal Mode and changing the other bits of the M_S_CTRL register. The other modifications will be ignored. • Sleep Mode: attempt to go to Sleep Mode without any wake source set, i.e. when all bits in the BUS_CTRL and WK_CTRL registers are cleared. In this case the SPI_FAIL bit is set and the device enters Restart Mode. Even though the Sleep Mode command is not entered in this case, the rest of the command is executed but restart values apply during Restart Mode; Note: At least one wake source must be activated in order to avoid a deadlock situation in Sleep Mode. If the only wake source is a timer and the timer is OFF, then the device will wake immediately from Sleep Mode and enter Restart Mode. • Setting a longer or equal on-time than the timer period of the respective timer. • SDI stuck at HIGH or LOW, e.g. SDI received all ‘0’ or all ‘1’. • Configured the HSx controlled by SYNC when the WK4/SYNC is not configured as SYNC-input. Note: There is no SPI fail information for unused addresses. Note: In case that the register or banking are accessed but they are not valid as address or banks, the SPI_FAIL is not triggered and the cmd is ignored. Signalization of the ERR Flag (high active) in the SPI Data Output (see Figure 75): The ERR flag presents an additional diagnosis possibility for the SPI communication. The ERR flag is being set for following conditions: 1) If the device is externally configured to use SPI with CRC (by PWM1/CRC pin), the attempt to go to Stop or Sleep from Init , will generate SPI_FAIL even if it is a SPI command with correct CRC. Still, the first SPI command will put the device from Init to Normal Mode even if CRC is not correct (CRC_FAIL status bit will be set). Datasheet 167 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Serial Peripheral Interface • in case the number of received SPI clocks is not 0 or 32. • in case RSTN is LOW and SPI frames are being sent at the same time. Note: In order to read the SPI ERR flag properly, CLK must be low when CSN is triggered, i.e. the ERR bit is not valid if the CLK is high on a falling edge of CSN. The number of received SPI clocks is not 0 or 32: The number of received input clocks is supervised to be 0 or 32 clock cycles and the input word is discarded in case of a mismatch (0 clock cycle to enable ERR signalization). The error logic also recognizes if CLK was high during CSN edges. Both errors ( 0 or 32 bit CLK mismatch or CLK high during CSN edges ) are flagged in the following SPI output by a “HIGH” at the data output (SDO pin, bit ERR) before the first rising edge of the clock is received. The complete SPI command is ignored in this case. RSTN is LOW and SPI frames are being sent at the same time: The ERR flag will be set when the RSTN pin is triggered (during device restart) and SPI frames are being sent to the device at the same time. The behavior of the ERR flag will be signalized at the next SPI command for below conditions: • If the command begins when RSTN is HIGH and it ends when RSTN is LOW. • If a SPI command will be sent while RSTN is LOW. • If a SPI command begins when RSTN is LOW and it ends when RSTN is HIGH. And the SDO output will behave as follows: • Always when RSTN is LOW then SDO will be HIGH. • When a SPI command begins when RSTN is LOW and ends when RSTN is HIGH, then the SDO should be ignored because wrong data will be sent. Note: It is possible to quickly check for the ERR flag without sending any data bits. i.e. only the CSN is pulled low and SDO is observed - no SPI Clocks are sent in this case. Note: The ERR flag could also be set after the device has entered Fail-Safe Mode because the SPI communication is stopped immediately. Datasheet 168 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Serial Peripheral Interface 13.3 SPI Programming For the TLE9563-3QX, 7 bits are used for the address selection (BIT 6...0). Bit 7 is used to decide between Read Only and Read & Clear for the status bits, and between Write and Read Only for configuration bits. For the actual configuration and status information, 16 data bits (BIT 23...8) are used. Writing, clearing and reading is done word wise. The SPI status bits are not cleared automatically and must be cleared by the microcontroller. Some of the configuration bits will automatically be cleared by the device (refer to the respective register descriptions for detailed information). In Restart Mode, the device ignores all SPI communication, i.e. it does not interpret it. There are two types of SPI registers: • Control registers: These registers are used to configure the device, e.g. mode, watchdog trigger, etc. • Status registers: These registers indicate the status of the device, e.g. wake events, warnings, failures, etc. For the status registers, the requested information is given in the same SPI command in the data out (SDO). For the control registers, the status of each byte is shown in the same SPI command as well. However, configuration changes of the same register are only shown in the next SPI command (configuration changes inside the device become valid only after CSN changes from low to high). See Figure 76. Writing of control registers is possible in Init and Normal Mode. During Stop Mode only the change to Normal Mode and triggering the watchdog is allowed as well as reading and clearing the status registers. No status information can be lost, even if a bit changes right after the first 7 SPI clock cycles before the SPI frame ends. In this case the status information field will be updated with the next SPI command. However, the flag is already set in the relevant status register.The device status information from the SPI status registers is transmitted in a compressed format with each SPI response on SDO in the so-called Status Information Field register (see also Table 46). The purpose of this register is to quickly signal changes in dedicated SPI status registers to the microcontroller. Table 46 Status Information Field Bit in Status Information Field Corresponding Address Bit Status Register Description 0 SUPPLY_STAT = OR of all bits on SUP_STAT register 1 TEMP_STAT = OR of all bits on THERM_STAT register 2 BUS_STAT= OR of all bits on BUS_STAT register 3 WAKE_UP = OR of all bits on WK_STAT register 4 HS_STAT = OR of all bits on HS_OL_OC_OT_STAT register 5 DEV_STAT = OR of all bits on DEV_STAT except CRC_STAT and SW_DEV 6 BD_STAT = OR of all bits on DSOV register 7 SPI_CRC_FAIL = (SPI_FAIL) OR (CRC_FAIL) Datasheet 169 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Serial Peripheral Interface MSB LSB DI 0 1 2 3 4 5 6 Address Bits 7 8 9 x x 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Data Bits R/W x x x x x x x CRC or Static Pattern x x x x x x x x x x x x x x x Register content of selected address DO 0 1 2 3 4 5 6 7 8 9 x x 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Status Information Field Data Bits x x x x x x x CRC or Static Pattern x x x x x x x x x x x x x x x time LSB is sent first in SPI message Figure 76 SPI Operation Mode 13.3.1 CRC The SPI interface includes also 8 Bits (bits 24 to 31) used for Cyclic Redundancy Check (CRC) to ensure data integrity on sent or received SPI command. The implemented CRC is based on Autosar specification of CRC Routines revision 4.3.0 and in particular the function CRC8-2FH. The specification are based on the follow table: Table 47 CRC8x2FH definition CRC result width: 8 bits Polynomial 2FH Initial Value FFH Input data reflected No Result data reflected No XOR value FFH Check DFH Magic check 42H Some examples of CRC calculation are shown in the follow table: Table 48 CRC8x2FH calculation example Data Bytes (hexadecimal) CRC 00 00 00 F2 01 83 0F AA 00 55 C6 00 FF 55 11 77 33 22 55 AA 92 6B 55 FF FF FF Datasheet 00 12 C2 BB CC DD EE FF 11 33 FF 6C 170 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Serial Peripheral Interface Polynominal The polynomial is: x8 + x5 + x3 + x2 + x1 + x0 (13.1) Calculation in SDI and SDO The calculation of the CRC is done considering the first 24 bits (BIT 0..23) either of SDI or SDO. The content of SDO Payload (BIT 8..23) is referring the previous data written at the addressed register via SDI. SDI Add. r w Payload - Configuration CRC ∑ PASS/FAIL SDO Status Info. Field From previous SPI cmd CRC ∑ Figure 77 CRC calculation CRC Activation and status information For CRC activation, refer to Chapter 5.2. The CRC status (CRC_STAT)and failure (CRC_FAIL) are readable on DEV_STAT. Read out of the register which contains the CRC_STAT and CRC_FAIL is done ignoring the CRC field and no failure flag are set. The DEV_STAT register shall be cleared considering the CRC setting (ON or OFF). The CRC_STAT bit is read only. The CRC_FAIL is set in the follow conditions: • If the CRC is enabled and the µC sends wrong CRC field. • If the CRC is disabled and the µC sends wrong static pattern (no A5H). CRC field in case of CRC disabled In case that the CRC is not activated, the bits needed for CRC field have to be filled with static pattern. In case of SDI, the CRC field has to be filled with A5H (bits 24:31). In case of SDO, the device will always answer with 5AH (bits 24:31). The status of the CRC is updated accordingly in CRC_STAT bit. Datasheet 171 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Serial Peripheral Interface 13.4 SPI Bit Mapping The following figures show the mapping of the registers and the SPI bits of the respective registers. The Control Registers are Read/Write Register with the following structure: • Device Control Registers from 000 0001B to 000 1011B. • Bridge Driver Control Registers from 001 0000B to 001 1101B. • SWK Control Registers from 011 0000B to 011 1111B. Depending on bit 7 the bits are only read (setting bit 7 to ‘0’) or also written (setting bit 7 to ‘1’). The new setting of the bit after a write can be seen with a new read / write command. The Status Registers are Read/Clear with the following structure: • Device Status Registers from 100 0000B to 100 0110B. • Bridge Driver Status Registers from 101 0000B to 101 1011B. • SWK Status Registers from 110 0000B to 110 0011B. • Product Family is 111 0000B. The registers can be read or can be cleared (if clearing is possible) depending on bit 7. To clear the payload of one of the Status Registers bit 7 must be set to 1. The registers WK_LVL_STAT, and FAM_PROD_STAT, SWK_OSC_CAL_STAT, SWK_ECNT_STAT, SWK_CDR_STAT are an exception as they show the actual voltage level at the respective WKx pin (LOW/HIGH), or a fixed family/ product ID respectively and can thus not be cleared. It is recommended for proper diagnosis to clear respective status bits for wake events or failure. When changing to a different device mode, certain configurations bits will be cleared automatically or modified: • The device mode bits are updated to the actual status, e.g. when returning to Normal Mode. • When changing to a low-power mode (Stop Mode or Sleep Mode), the diagnosis bits of the integrated module are not cleared. • When changing to Stop Mode, the CAN, control bits will not be modified. • When changing to Sleep Mode, the CAN, control bits will be modified if they were not OFF or wake capable before. Note: Datasheet The detailed behavior of the respective SPI bits and control functions is described in Chapter 13.5, Chapter 13.6.and in the respective module chapter. The bit type be marked as ‘rwh’ in case the device will modify respective control bits. 172 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Serial Peripheral Interface 16 Data Bits [bits 23...8] Bridge Driver Device Control Registers Control Registers for Configuration & Status Information Figure 78 Reg. Type 7 Address Bits [bits 6...0] for Register Selection Addresses: 000 0001 . . . 000 1011 Addresses: 100 0000 . . . 111 0000 The most important status registers are represented in the Status Information Field Status Information Field Bit Selective Wake Control Registers Addresses: 011 0000 . . . 011 1111 If CAN Partial Networking is not available for the respective variant then this address space will be reserved Status Registers Addresses: 001 0000 . . . 001 1101 SPI Register Mapping Structure The detailed register mappings for control registers and status registers are shown in Table 49 and Table 93 respectively. 13.4.1 Register Banking In order to minimize the number of configuration registers, seven registers follow a bank structure. The banked registers are: • WK_CTRL • PWM_CTRL • CCP_BLK • TPRECHG • HB_ICHG • HB_PCHG_INIT • TDON_HB_CTRL • TDOFF_HB_CTRL Datasheet 173 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Serial Peripheral Interface In these register, the first 3 bits of the payload (bit 8 to 10) select the bank that has to be configured. The rest of the payload is used to configure the selected bank (for more details refer to the specific banked register). In case that CRC is used, the CRC calculation is done considering the first 24 bits (from bit 0 to 23). The banked registers can be read like the other configuration registers but in the SDO one ‘0’ is automatically added after the status information field. Figure 79 shows the structure of SDO in banked register. SDI Add. r w B K 0 B K 1 B K 2 R e s Configuration of selected Bank B K 0 B K 1 B K 2 Selected Bank Content 0 CRC SDO Status Info. Filed Figure 79 Datasheet CRC Register read Out of banked register (3 bit banking) 174 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Serial Peripheral Interface 13.5 SPI control registers READ/WRITE Operation (see also Chapter 13.3): • The ‘POR / Soft Reset Value’ defines the register content after POR or device reset. • The ‘Restart Value’ defines the register content after device restart, where ‘x’ means the bit is unchanged. • There are different bit types: – ‘r’ = READ: read only bits (or reserved bits). – ‘rw’ = READ/WRITE: readable and writable bits. – ‘rwh’ = READ/WRITE/Hardware: readable/writable bits, which can also be modified by the device hardware. • Reserved bits are marked as “Reserved” and always read as “0”. The respective bits shall also be programmed as “0”. • Reading a register is done word wise by setting the SPI bit 7 to “0” (= Read Only). • SPI control bits are in general not cleared or changed automatically. This must be done by the microcontroller via SPI programming. Exceptions to this behavior are stated at the respective register description and the respective bit type is marked with a ‘h’ meaning that the device is able to change the register content. The registers are addressed wordwise. Table 49 Register Overview Register Short Name Register Long Name Offset Address Page Number SPI control registers, Device Control Registers M_S_CTRL Mode and Supply Control 0000001B 177 HW_CTRL Hardware Control 0000010B 179 WD_CTRL Watchdog Control 0000011B 181 BUS_CTRL CAN Control 0000100B 183 WK_CTRL Wake-up Control 0000101B 185 TIMER_CTRL Timer 1 and Timer 2 Control and Selection 0000110B 187 SW_SD_CTRL High-Side Switch Shutdown Control 0000111B 189 HS_CTRL High-Side Switch Control 0001000B 191 INT_MASK Interrupt Mask Control 0001001B 193 PWM_CTRL PWM Configuration Control 0001010B 195 SYS_STAT_CTRL System Status Control 0001011B 196 SPI control registers, Control registers bridge driver GENCTRL General Bridge Control 0010000B 197 CSA Current sense amplifier 0010001B 199 LS_VDS Drain-Source monitoring threshold 0010010B 201 HS_VDS Drain-Source monitoring threshold 0010011B 203 CCP_BLK CCP and times selection 0010100B 205 HBMODE Half-Bridge MODE 0010101B 206 TPRECHG PWM pre-charge and pre-discharge time 0010110B 208 Datasheet 175 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Serial Peripheral Interface Table 49 Register Overview (cont’d) Register Short Name Register Long Name Offset Address Page Number ST_ICHG Static charge/discharge current 0010111B 209 HB_ICHG PWM charge/discharge current 0011000B 210 HB_ICHG_MAX PWM max. pre-charge/pre-discharge current and diagnostic pull-down 0011001B 211 HB_PCHG_INIT PWM pre-charge/pre-discharge initialization 0011010B 213 TDON_HB_CTRL PWM inputs TON configuration 0011011B 214 TDOFF_HB_CTRL PWM inputs TOFF configuration 0011100B 215 BRAKE Brake control 0011101B 216 SPI control registers, Selective Wake Registers SWK_CTRL CAN Selective Wake Control 0110000B 218 SWK_BTL1_CTRL SWK Bit Timing Control 0110001B 219 SWK_ID1_CTRL SWK WUF Identifier bits 28...13 0110010B 220 SWK_ID0_CTRL SWK WUF Identifier bits 12...0 0110011B 221 SWK_MASK_ID1_CTRL SWK WUF Identifier Mask bits 28...13 0110100B 222 SWK_MASK_ID0_CTRL SWK WUF Identifier Mask bits 12...0 0110101B 224 SWK_DLC_CTRL SWK Frame Data Length Code Control 0110110B 226 SWK_DATA3_CTRL SWK Data7-Data6 Register 0110111B 227 SWK_DATA2_CTRL SWK Data5-Data4 Register 0111000B 228 SWK_DATA1_CTRL SWK Data3-Data2 Register 0111001B 229 SWK_DATA0_CTRL SWK Data1-Data0 Register 0111010B 230 SWK_CAN_FD_CTRL CAN FD Configuration Control Register 0111011B 231 SPI control registers, Selective Wake trim and configuration Registers SWK_OSC_TRIM_CTRL SWK Oscillator Trimming and option Register 0111100B 232 SWK_OSC_CAL_STAT SWK Oscillator Calibration Register 0111101B 233 SWK_CDR_CTRL Clock Data Recovery Control Register 0111110B 234 SWK_CDR_LIMIT SWK Clock Data Recovery Limit Control 0111111B 236 Datasheet 176 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Serial Peripheral Interface 13.5.1 Device Control Registers Mode and Supply Control M_S_CTRL Mode and Supply Control 15 14 13 12 MODE RES rwh r (000 0001B) 11 10 9 8 7 Reset Value: see Table 50 6 5 4 VCC1_OV_MO RSTN_ I_PEA RES RES D HYS K_TH rwh r rw r rw 3 2 1 0 RES VCC1_RT r rw Field Bits Type Description MODE 15:14 rwh Device Mode Control 00B NORMAL, Normal Mode 01B SLEEP, Sleep Mode 10B STOP, Stop Mode 11B RESET, Device reset: Soft reset is executed (configuration of RSTN triggering in bit SOFT_RESET_RO) RES 13:11 r Reserved, always reads as 0 VCC1_OV_MOD 10:9 rwh Reaction in case of VCC1 Over Voltage 00B NO, no reaction 01B INTN, INTN event is generated 10B RSTN, RSTN event is generated 11B FAILSAFE, Fail-Safe Mode is entered RES 8 r Reserved, always reads as 0 RSTN_HYS 7 rw VCC1 Undervoltage Reset Hysteresis Selection (see also Chapter 12.7.1 for more information) 0B DEFAULT, default hysteresis applies as specified in the electrical characteristics table 1B HIGHEST, the highest rising threshold (VRT1,R) is always used for the release of the undervoltage reset RES 6 r Reserved, always reads as 0 I_PEAK_TH 5 rw VCC1 Active Peak Threshold Selection 0B LOW, low VCC1 active peak threshold selected 1B HIGH, high VCC1 active peak threshold selected RES 4:2 r Reserved, always reads as 0 VCC1_RT 1:0 rw VCC1 Reset Threshold Control 00B VRT1, Vrt1 selected (highest threshold) 01B VRT2, Vrt2 selected 10B VRT3, Vrt3 selected 11B VRT4, Vrt4 selected Datasheet 177 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Serial Peripheral Interface Table 50 Reset of M_S_CTRL Register Reset Type Reset Values POR/Soft reset 0000 0000 0000 0000B Restart 0000 0000 x0x0 00xxB Reset Short Name Reset Mode Note Notes 1. It is not possible to change from Stop Mode to Sleep Mode via SPI Command. See also the State Machine Chapter. 2. After entering Restart Mode, the MODE bits will be automatically set to Normal Mode. 3. The SPI output will always show the previously written state with a Write Command (what has been programmed before) . Datasheet 178 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Serial Peripheral Interface Hardware Control HW_CTRL Hardware Control 15 14 13 (000 0010B) 12 11 10 9 8 TSD2_ VS_OV SH_DI RSTN_ DEL _SEL SABLE DEL RES r rw rw rw rw 7 RES r Reset Value: see Table 51 6 5 SOFT_ RESET RES _RO rw 4 3 2 1 0 RES WD_S TM_E N_1 RES r rwh r r Field Bits Type Description RES 15:13 r Reserved, always reads as 0 TSD2_DEL 12 rw TSD2 minimum Waiting Time Selection 0B 1s, Minimum waiting time until TSD2 is released again is always 1 s 1B 64s, Minimum waiting time until TSD2 is released again is 1 s, after >16 TSD2 consecutive events, it will extended x 64 VS_OV_SEL 11 rw VS OV comparator threshold change 0B 20V, Default threshold setting (VS,OVD1) 1B 30V, increased threshold setting (VS,OVD2) SH_DISABLE 10 rw Sample and hold circuitry disable 0B ENABLED, Gate driver S&H circuitry enabled 1B DISABLED, Gate driver S&H circuitry disabled RSTN_DEL 9 rw Reset delay time 0B 10ms, Reset delay time 10 ms (tRD1) 1B 2ms, Reset delay time to 2 ms (tRD2) RES 8:7 r Reserved, always reads as 0 SOFT_RESET_RO 6 rw Soft Reset Configuration 0B RSTN, RSTN will be triggered (pulled low) during a Soft Reset 1B NO_RSTN, no RSTN trigger during a Soft Reset RES 5 r Reserved, always reads as 0 RES 4:3 r Reserved, always reads as 0 WD_STM_EN_1 2 rwh Watchdog Deactivation during Stop Mode, bit1 0B ACTIVE, Watchdog is active in Stop Mode 1B INACTIVE, Watchdog is deactivated in Stop Mode RES 1:0 r Reserved, always reads as 0 Table 51 Reset of HW_CTRL Register Reset Type Reset Values POR 0000 0000 0000 0000B Soft reset 0000 00x0 0000 0000B Restart 000x 00x0 0x00 0000B Datasheet Reset Short Name Reset Mode 179 Note Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Serial Peripheral Interface Notes 1. WD_STM_EN_1 will also be cleared when changing from Stop Mode to Normal Mode . Datasheet 180 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Serial Peripheral Interface Watchdog Control WD_CTRL Watchdog Control 15 14 13 (000 0011B) 12 11 10 CHEC KSUM RES rw r 9 8 7 Reset Value: see Table 52 6 5 4 3 WD_S WD_E WD_C TM_E N_WK RES FG N_0 _BUS rwh rw rwh 2 1 0 WD_TIMER r rwh Field Bits Type Description CHECKSUM 15 rw Watchdog Setting Check Sum Bit 0B 0, Counts as 0 for checksum calculation 1B 1, Counts as 1 for checksum calculation RES 14:7 r Reserved, always reads as 0 WD_STM_EN_0 6 rwh Watchdog Deactivation during Stop Mode, bit0 0B ACTIVE, Watchdog is active in Stop Mode 1B INACTIVE, Watchdog is deactivated in Stop Mode WD_CFG 5 rw Watchdog Configuration 0B TIMEOUT, Watchdog works as a Time-Out watchdog 1B WINDOW, Watchdog works as a Window watchdog WD_EN_ WK_BUS 4 rwh Watchdog Enable after Bus Wake in Stop Mode 0B DISABLED, Watchdog will not start after a CAN wake-up event 1B ENABLED, Watchdog starts with a long open window after CAN Wake-up event RES 3 r Reserved, always reads as 0 WD_TIMER 2:0 rwh Watchdog Timer Period 000B 10ms, 10ms 001B 20ms, 20ms 010B 50ms, 50ms 011B 100ms, 100ms 100B 200ms, 200ms 101B 500ms, 500ms 110B 1s, 1s 111B 10s, 10s Table 52 Reset of WD_CTRL Register Reset Type Reset Values POR/Soft reset 0000 0000 0001 0100B Restart 0000 0000 000x 0100B Datasheet Reset Short Name Reset Mode 181 Note Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Serial Peripheral Interface Notes 1. See also Chapter 12.2.4 for more information on disabling the watchdog in Stop Mode. 2. See chapter Chapter 12.2.5 for more information on the effect of the bit WD_EN_WK_BUS. 3. See chapter Chapter 12.2.3 for calculation of checksum. Datasheet 182 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Serial Peripheral Interface CAN Control BUS_CTRL CAN Control 15 14 (000 0100B) 13 12 11 10 9 8 Reset Value: see Table 53 7 6 5 4 3 2 1 0 RES RES RES RES RES CAN r r r r r rwh Field Bits Type Description RES 15:8 r Reserved, always reads as 0 RES 7 r Reserved, always reads as 0 RES 6 r Reserved, always reads as 0 RES 5 r Reserved, always reads as 0 RES 4:3 r Reserved, always reads as 0 CAN 2:0 rwh HS-CAN Module Modes 000B OFF, CAN OFF 001B WAKE, CAN is wake capable (no SWK) 010B RECEIVE, CAN Receive Only Mode (no SWK) 011B NORMAL, CAN Normal Mode (no SWK) 100B OFF, CAN OFF 101B WAKE_SWK, CAN is wake capable with SWK 110B RECEIVE_SWK, CAN Receive Only Mode with SWK 111B NORMAL_SWK, CAN Normal Mode with SWK Table 53 Reset of BUS_CTRL Register Reset Type Reset Values POR/Soft reset 0000 0000 0010 0000 Restart 0000 0000 0000 0xyyB Reset Short Name Reset Mode Note Notes 1. The reset values for CAN, transceivers are marked with ‘y’ because they will vary depending on the cause of change. 2. See Figure 30, for detailed state changes of CAN, transceivers for different device modes. 3. The bit CAN_2 is not modified by the device but can only be changed by the user. Therefore, the bit type is ‘rw’ compared to bits CAN_0 and CAN_1. 4. In case SYSERR = 0 and the CAN transceiver is configured to ‘x11’ while going to Sleep Mode, it will be automatically set to wake capable (‘x01’). The SPI bits will be changed to wake capable. If configured to ‘x10’ and Sleep Mode is entered, then the transceiver is set to wake capable, while it will stay in Receive Only Mode when it had been configured to ‘x10’ when going to Stop Mode. If it had been configured to wake capable or OFF then the mode will remain unchanged.The Receive Only Mode has to be selected by the user before entering Stop Mode. Please refer to Chapter 5.9 for detailed information on the Selective Wake Mode changes. 5. Failure Handling Mechanism: When the device enters Fail-Safe Mode due to a failure, then BUS_CTRL is modified by the device to 0000 0000 xxx0 1001B to ensure that the device can be woken again. See also the Datasheet 183 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Serial Peripheral Interface description in Chapter 8.1, and Chapter 9.2.1 for WK_CTRL for other wake sources when entering Fail-Safe Mode. 6. When in Software Development Mode the POR/Soft Reset value are: CAN=001B , . Datasheet 184 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Serial Peripheral Interface Wake-up Control WK_CTRL Wake-up Control 13 (000 0101B) 12 11 10 9 8 7 Reset Value: see Table 54 15 14 6 5 4 3 2 1 0 RES RES WK_FILT WK_PUPD RES WK_EN RES WK_BNK r r rw rw r rw r rw Field Bits Type Description RES 15 r Reserved, always reads as 0 RES 14 r Reserved, always reads as 0 WK_FILT 13:11 rw Wake-up Filter Time Configuration 000B 16us, Filter with 16 µs filter time (static sensing) 001B 64us, Filter with 64 µs filter time (static sensing) 010B TIMER1, Filtering at the end of the on-time; filter time of 16 µs (cyclic sensing) is selected, Timer1 011B TIMER2, Filtering at the end of the on-time; filter time of 16 µs (cyclic sensing) is selected, Timer2 100B SYNC, Filter at the end of settle time (80 µs), filter time of 16 µs (cyclic sensing) is selected, SYNC1)2) 101B , reserved 110B , reserved 111B , reserved WK_PUPD 10:9 rw WKx Pull-Up/Pull-Down Configuration 00B NO, No pull-up/pull-down selected 01B PULL_DOWN, Pull-down resistor selected 10B PULL_UP, Pull-up resistor selected3) 11B AUTO, Automatic switching to pull-up or pulldown RES 8:7 r Reserved, always reads as 0 WK_EN 6:5 rw WKx Enable 00B WK_OFF, WKx module OFF 01B WK_ON, WKx module ON 10B SYNC, OFF or (in case of WK4), it is configured as SYNC input 11B OFF, OFF RES 4:3 r Reserved, always reads as 0 WK_BNK 2:0 rw WKs input Banking 011B WK4, WK4 Module (Bank 4) 100B WK5, WK5 Module (Bank 5)3) 101B , reserved 110B , reserved 111B , reserved 1) This setting is available only in case of WK4 configured as WK_EN=10B. 2) The min TON time for cyclic sense with SYNC is 100 µs. 3) WK5 has a fixed pull-up resistor and is not configurable. So in Bank 5, the WK_PUPD field is reserved. Datasheet 185 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Serial Peripheral Interface Table 54 Reset of WK_CTRL Register Reset Type Reset Values POR/Soft reset 0000 0000 0010 0000B Restart 00xx xxx0 0xx0 0000B Reset Short Name Reset Mode Note Notes 1. The SYNC functionality is accessable only if the Bank 4 is selected. 2. When selecting a filter time configuration, the user must make sure to also assign the respective timer/SYNC to at least one HS switch during cyclic sense operation. 3. At Fail-Safe Mode entry WK_EN will be automatically changed (by the device) in “01”. WK4 if configured as SYNC previously 4. During Fail-Safe Mode the WK_FILT bits are ignored and static-sense with 16 µs filter time is used by default. Datasheet 186 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Serial Peripheral Interface Timer 1 and Timer2 Control and Selection TIMER_CTRL Timer 1 and Timer2 Control and Selection 15 14 13 12 11 10 (000 0110B) 9 8 7 Reset Value: see Table 55 6 5 4 3 2 1 0 TIMER2_ON RES TIMER2_PER CYCWK TIMER1_ON RES TIMER1_PER rwh r rwh rwh rwh r rwh Field Bits Type Description TIMER2_ON 15:13 rwh Timer2 On-Time Configuration 000B OFF_LOW, OFF / Low (timer not running, HSx output is low) 001B 100us, 0.1ms on-time 010B 300us, 0.3ms on-time 011B 1ms, 1.0ms on-time 100B 10ms, 10ms on-time 101B 20ms, 20ms on-time 110B OFF_HIGH, OFF / HIGH (timer not running, HSx output is high) 111B , reserved, same behaviour as 110B RES 12 r Reserved, always reads as 0 TIMER2_PER 11:9 rwh Timer2 Period Configuration 000B 10ms, 10ms 001B 20ms, 20ms 010B 50ms, 50ms 011B 100ms, 100ms 100B 200ms, 200ms 101B 500ms, 500ms 110B 1s, 1s 111B 2s, 2s CYCWK 8:7 rwh Cyclic Wake Configuration 00B DISABLED, Timer1 and Timer2 disabled as wakeup sources 01B TIMER1, Timer1 is enabled as wake-up source (Cyclic Wake) 10B TIMER2, Timer2 is enabled as wake-up source (Cyclic Wake) 11B , reserved Datasheet 187 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Serial Peripheral Interface Field Bits Type Description TIMER1_ON 6:4 rwh Timer1 On-Time Configuration 000B OFF_LOW, OFF / Low (timer not running, HSx output is low) 001B 100us, 0.1ms on-time 010B 300us, 0.3ms on-time 011B 1ms, 1.0ms on-time 100B 10ms, 10ms on-time 101B 20ms, 20ms on-time 110B OFF_HIGH, OFF / HIGH (timer not running, HSx output is high) 111B , reserved, same behaviour as 110B RES 3 r Reserved, always reads as 0 TIMER1_PER 2:0 rwh Timer1 Period Configuration 000B 10ms, 10ms 001B 20ms, 20ms 010B 50ms, 50ms 011B 100ms, 100ms 100B 200ms, 200ms 101B 500ms, 500ms 110B 1s, 1s 111B 2s, 2s Table 55 Reset of TIMER_CTRL Register Reset Type Reset Values POR/Soft reset 0000 0000 0000 0000B Restart 0000 0000 0000 0000B Reset Short Name Reset Mode Note Notes 1. The timer must be first assigned and is then automatically activated as soon as the on-time is configured. 2. If cyclic sense is selected and the HSx switch is cleared during Restart Mode then also the timer settings (period and on-time) are cleared to avoid incorrect switch detection. However, the timer settings are not cleared in case of failure not leading to Restart Mode. 3. In case the timer is set as wake sources and cyclic sense is running, then both cyclic sense and cyclic wake will be active at the same time. 4. Timer accuracy is linked to the oscillator accuracy (see Parameter P_13.12.43). Datasheet 188 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Serial Peripheral Interface High-Side Switch Shutdown Control SW_SD_CTRL High-Side Switch Shutdown Control 15 14 13 12 11 10 (000 0111B) 9 8 7 Reset Value: see Table 56 6 5 4 3 HS3_ HS2_ HS1_ HS_O HS_U HS3_ HS2_ HS1_ HS_O HS_U RES OV_RE OV_RE OV_RE T_SD_ RES OV_S OV_S OV_S V_SDS V_SD_ RES V_REC DN_DI DN_DI DN_DI _DIS DIS C C C DIS S S S r rw rw rw rw r rw rw rw rw rw r rw 2 1 0 RES r Field Bits Type Description RES 15 r Reserved, always reads as 0 HS3_OV_REC 14 rw Switch recovery after removal of VS Overvoltage for HS3 0B DISABLED, Switch recovery is disabled 1B PREVIOUS, Previous state before VS Overvoltage is enabled after Overvoltage considtion is removed HS2_OV_REC 13 rw Switch recovery after removal of VS Overvoltage for HS2 0B DISABLED, Switch recovery is disabled 1B PREVIOUS, Previous state before VS Overvoltage is enabled after Overvoltage considtion is removed HS1_OV_REC 12 rw Switch recovery after removal of VS Overvoltage for HS1 0B DISABLED, Switch recovery is disabled 1B PREVIOUS, Previous state before VS Overvoltage is enabled after Overvoltage considtion is removed HS_OT_SD_DIS 11 rw Shutdown Disabling of all HS in case of Overtemperature event 0B ALL, shudown for all HSx in case of Overtemperature 1B INDIVIDUAL, individual shudown in case of Overtemperature RES 10 r Reserved, always reads as 0 HS3_OV_SDN_DIS 9 rw Shutdown Disabling of HS3 in case of input supply overvoltage in Normal Mode 0B ENABLED, shudown enabled in case of VS Overvoltage 1B DISABLED, shudown disabled in case of VS Overvoltage Datasheet 189 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Serial Peripheral Interface Field Bits Type Description HS2_OV_SDN_DIS 8 rw Shutdown Disabling of HS2 in case of input supply overvoltage in Normal Mode 0B ENABLED, shudown enabled in case of VS Overvoltage 1B DIASBLED, shudown disabled in case of VS Overvoltage HS1_OV_SDN_DIS 7 rw Shutdown Disabling of HS1 in case of input supply overvoltage in Normal Mode 0B ENABLED, shudown enabled in case of VS Overvoltage 1B DISABLED, shudown disabled in case of VS Overvoltage HS_OV_SDS_DIS 6 rw Shutdown Disabling of HSx in case of input supply overvoltage in Stop Mode or Sleep Mode 0B ENABLED, shudown enabled in case of VS Overvoltage 1B DISABLED, shudown disabled in case of VS Overvoltage HS_UV_SD_DIS 5 rw Shutdown Disabling of HSx in case of input supply undervoltage 0B ENABLED, shudown enabled in case of VS Undervoltage 1B DISABLED, shudown disabled in case of VS Undervoltage RES 4 r Reserved, always reads as 0 HS_UV_REC 3 rw Switch recovery after removal of Undervoltage for HSx 0B DISABLED, Switch recovery is disabled 1B PREVIOUS, Previous state before VS Undervoltage is enabled after Undervoltage considtion is removed RES 2:0 r Reserved, always reads as 0 Table 56 Reset of SW_SD_CTRL Register Reset Type Reset Values POR/Soft reset 0000 0000 0000 0000B Restart 0xxx x0xx xxx0 x000B Datasheet Reset Short Name Reset Mode 190 Note Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Serial Peripheral Interface High-Side Switch Control HS_CTRL High-Side Switch Control 15 14 13 12 (000 1000B) 11 10 9 8 7 Reset Value: see Table 57 6 5 4 3 2 1 RES HS3 HS2 HS1 r rwh rwh rwh 0 Field Bits Type Description RES 15:12 r Reserved, always reads as 0 HS3 11:8 rwh HS3 Configuration 0000BOFF, OFF 0001BON, ON 0010BTIMER1, Controlled by Timer1 0011BTIMER2, Controlled by Timer2 0100BPWM1, Controlled by PWM1 0101BPWM2, Controlled by PWM2 0110BPWM3, Controlled by PWM3 0111BPWM4, Controlled by PWM4 1000BWK4_SYNC, Synchronized with WK4/SYNC 1001B, reserved 1010B, reserved 1011B, reserved 1100B, reserved 1101B, reserved 1110B, reserved 1111B, reserved HS2 7:4 rwh HS2 Configuration 0000BOFF, OFF 0001BON, ON 0010BTIMER1, Controlled by Timer1 0011BTIMER2, Controlled byTimer2 0100BPWM1, Controlled by PWM1 0101BPWM2, Controlled by PWM2 0110BPWM3, Controlled by PWM3 0111BPWM4, Controlled by PWM4 1000BWK4_SYNC, Synchronized with WK4/SYNC 1001B, reserved 1010B, reserved 1011B, reserved 1100B, reserved 1101B, reserved 1110B, reserved 1111B, reserved Datasheet 191 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Serial Peripheral Interface Field Bits Type Description HS1 3:0 rwh HS1 Configuration 0000BOFF, OFF 0001BON, ON 0010BTIMER1, Controlled by Timer1 0011BTIMER2, Controlled by Timer2 0100BPWM1, Controlled by PWM1 0101BPWM2, Controlled by PWM2 0110BPWM3, Controlled by PWM3 0111BPWM4, Controlled by PWM4 1000BWK4_SYNC, Synchronized with WK4/SYNC 1001B, reserved 1010B, reserved 1011B, reserved 1100B, reserved 1101B, reserved 1110B, reserved 1111B, reserved Table 57 Reset of HS_CTRL Register Reset Type Reset Values POR/Soft reset 0000 0000 0000 0000B Restart 0000 0000 0000 0000B Reset Short Name Reset Mode Note PWMx in this register designates the internal PWM generators for the integrated high-side switches. Datasheet 192 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Serial Peripheral Interface Interrupt Mask Control1) INT_MASK Interrupt Mask Control 15 14 13 12 (000 1001B) 11 10 9 8 7 Reset Value: see Table 58 6 5 4 3 2 1 0 INTN_ WD_S SPI_C SUPP WD_S BD_ST HS_ST BUS_S TEMP CYC_E DM_DI RC_FA LY_ST DM AT AT TAT _STAT N SABLE IL AT RES r rw rw rw rw rw rw rw rw rw Field Bits Type Description RES 15:9 r Reserved, always reads as 0 INTN_CYC_EN 8 rw Periodical INTN generation 0B DISABLED, no periodical INTN event generated in case of pending interrupts 1B ENABLED, periodical INTN event generated in case of pending interrupts WD_SDM_DISABLE 7 rw Disable Watchdog in Software Development Mode 0B ENABLED, WD is enabled in Software Development Mode 1B DISABLED, WD is disabled in Software Development Mode WD_SDM 6 rw Watchdog failure in Software Development Mode 0B DISABLED, no INTN event generated in case of WD trigger failure in Software Development Mode 1B ENABLED, one INTN event is generated in case of WD trigger failure in Software Development Mode SPI_CRC_FAIL 5 rw SPI and CRC interrupt generation 0B DISABLED, no INTN event generated in case of SPI_FAIL or CRC_FAIL 1B ENABLED, one INTN event is generated n case of SPI_FAIL or CRC_FAIL BD_STAT 4 rw Bridge Driver Interrupt generation 0B DISABLED, no INTN event generated in case BD_STAT (on Status Information Field) is set 1B ENABLED, one INTN event generated in case BD_STAT (on Status Information Field) is set HS_STAT 3 rw High Side Interrupt generation 0B DISABLED, no INTN event generated in case HS_STAT (on Status Information Field) is set 1B ENABLED, one INTN event generated in case HS_STAT (on Status Information Field) is set 1) Every event will generate a signal on the INTN pin (when masked accordingly). Even if the status-bit was already set in the corresponding status-register it can still trigger a signal on the INTN pin. Datasheet 193 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Serial Peripheral Interface Field Bits Type Description BUS_STAT 2 rw BUS Interrupt generation 0B DISABLED, no INTN event generated in case BUS_STAT (on Status Information Field) is set 1B ENABLED, one INTN event generated in case BUS_STAT (on Status Information Field) is set TEMP_STAT 1 rw Temperature Interrupt generation 0B DISABLED, no INTN event generated in case TEMP_STAT (on Status Information Field) is set 1B ENABLED, one INTN event generated in case TEMP_STAT (on Status Information Field) is set SUPPLY_STAT 0 rw SUPPLY Status Interrupt generation 0B DISABLED, no INTN event generated in case SUPPLY_STAT (on Status Information Field) is set 1B ENABLED, one INTN event generated in case SUPPLY_STAT (on Status Information Field) is set Table 58 Reset of INT_MASK Register Reset Type Reset Values POR/Soft reset 0000 0001 0100 0000B Restart 0000 000x xxxx xxxxB Datasheet Reset Short Name Reset Mode 194 Note Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Serial Peripheral Interface PWM Configuration Control PWM_CTRL PWM Configuration Control 13 12 (000 1010B) 11 10 9 8 7 Reset Value: see Table 59 15 14 6 5 4 3 2 1 0 RES PWM_ FREQ PWM_DC RES PWM_BNK r rw rw r rw Field Bits Type Description RES 15 r Reserved, always reads as 0 PWM_FREQ 14 rw PWM generator Frequency Setting 0B 100Hz, 100Hz is selected 1B 200Hz, 200Hz is selected PWM_DC 13:4 rw PWM Duty Cycle Setting (bit4 = LSB; bit13 = MSB) 00 0000 0000B, 100% OFF, i.e. HS = OFF xx xxxx xxxxB, ON with duty cycle fraction of 1024 11 1111 1111B, 100% ON, i.e. HS = ON RES 3 r Reserved, always reads as 0 PWM_BNK 2:0 rw Internal PWM generator selection 000B PWM1, PWM1 Module 001B PWM2, PWM2 Module 010B PWM3, PWM3 Module 011B PWM4, PWM4 Module 1xxB , Don’t care Table 59 Reset of PWM_CTRL Register Reset Type Reset Values POR/Soft reset 0000 0000 0000 0000B Restart 0xxx xxxx xxxx 0000B Reset Short Name Reset Mode Note PWMx in this register designates the internal PWM generators for the integrated high-side switches. Notes 1. 2. 3. 4. 0% and 100% duty cycle settings are used to have the switch turned ON or OFF respectively. The desired duty cycle should be set first before the HSx is enabled as PWM. The PWM signal is correct only after at least one PWM pulse. PWM generator accuracy is linked to the oscillator accuracy (see parameter P_13.12.43). Datasheet 195 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Serial Peripheral Interface System Status Control SYS_STAT_CTRL System Status Control 15 14 13 12 (000 1011B) 11 10 9 8 7 Reset Value: see Table 60 6 5 4 3 2 1 0 SYS_STAT rw Field Bits Type Description SYS_STAT 15:0 rw System Status Control (bit0=LSB; bit15=MSB) Dedicated bytes for system configuration, access only by microcontroller. Cleared after power up and soft reset. Table 60 Reset of SYS_STAT_CTRL Register Reset Type Reset Values POR / Soft reset 0000 0000 0000 0000B Restart xxxx xxxx xxxx xxxxB Note: Datasheet Reset Short Name Reset Mode Note This register is intended for storing system configuration of the ECU by the microcontroller and is only accessible in Normal Mode. The register is not accessible by the TLE9563-3QX and is also not cleared after Fail-Safe or Restart Mode. It allows the microcontroller to quickly store system configuration without loosing data. 196 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Serial Peripheral Interface 13.5.2 Control registers bridge driver General Bridge Control GENCTRL General Bridge Control 15 14 13 BDFR EQ RES RES rw r r 12 (001 0000B) 11 10 9 8 7 CPUV FET_L CPST BDOV IPCHG TH VL GA _REC ADT rw rw rw rw rw Reset Value: see Table 61 6 5 AGC CPEN rw rw 4 3 2 1 0 EN_GE FMOD POCH AGCFI N_CH IHOLD GDIS LT E ECK rw rw rw rw rw Field Bits Type Description BDFREQ 15 rw Bridge driver synchronization frequency 0B 18MHz, typ. 18.75 MHz (default) 1B 37MHz, typ. 37.5 MHz RES 14 r Reserved, always reads as 0 RES 13 r Reserved, always reads as 0 CPUVTH 12 rw Charge pump under voltage (referred to VS) 0B TH1, (default) CPUV threshold 1 for FET_LVL = 0, CPUV threshold 1 for FET_LVL = 1 1B TH2, CPUV threshold 2 for FET_LVL = 0, CPUV threshold 2 for FET_LVL = 1 FET_LVL 11 rw External MOSFET normal / logic level selection 0B LOGIC, Logic level MOSFET selected 1B NORMAL, Normal level MOSFET selected(default) CPSTGA 10 rw Automatic switchover between dual and single charge pump stage 0B INACTIVE, Automatic switch over deactivated (default) 1B ACTIVE, Automatic switch over activated BDOV_REC 9 rw Bridge driver recover from VS and VSINT Overvoltage 0B INACTIVE, Recover deactivated (default) 1B ACTIVE, Recover activated IPCHGADT 8 rw Adaptation of the pre-charge and pre-discharge current 0B 1STEP, 1 current step (default) 1B 2STEPS, 2 current steps Datasheet 197 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Serial Peripheral Interface Field Bits Type Description AGC 7:6 rw Adaptive gate control 00B INACTIVE1, (default) Adaptive gate control disabled, pre-charge and pre-discharge disabled 01B INACTIVE2, Adaptive gate control disabled, precharge is enabled with IPRECHG = IPCHGINIT, predischarge is enabled with IPREDCHG = IPDCHGINIT 10B ACTIVE, Adaptive gate control enabled, IPRECHG and IPREDCHG are self adapted 11B , reserved. Adaptive gate control enabled, IPRECHG and IPREDCHG are self adapted CPEN 5 rw CPEN 0B DISABLED, Charge pump disabled (default) 1B ENABLED, Charge pump enabled POCHGDIS 4 rw Postcharge disable bit 0B ENABLED, The postcharge phase is enabled during PWM (default) 1B DISABLED, The postcharge phase is disabled during PWM AGCFILT 3 rw Filter for adaptive gate control 0B NO_FILT, No filter applied (default) 1B FILT_APPL, Filter applied EN_GEN_CHECK 2 rw Detection of active / FW MOSFET 0B DISABLED, Detection disabled (default) 1B ENABLED, Detection enabled IHOLD 1 rw Gate driver hold current IHOLD 0B TH1, (default) Charge: ICHG15, discharge IDCHG15. 1B TH2, Charge: ICHG20, discharge: IDCHG20 FMODE 0 rw Frequency modulation of the charge pump 0B NO, No modulation 1B 15KHz, Modulation frequency 15.6 kHz (default) Table 61 Reset of GENCTRL Register Reset Type Reset Values POR/Soft reset 0000 1000 0000 0001B Restart x00x xxxx xxxx xxxxB Datasheet Reset Short Name Reset Mode 198 Note Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Serial Peripheral Interface Current sense amplifier CSA Current sense amplifier 15 14 13 12 (001 0001B) 11 10 9 PWM_ CSO_ NB CAP RES r rw 8 7 Reset Value: see Table 62 6 5 4 3 2 1 0 CSD OCFILT CSA_O FF OCTH CSAG OCEN rw rw rw rw rw rw rw Field Bits Type Description RES 15:11 r Reserved, always reads as 0 PWM_NB 10 rw Selection of 3 or 6 PWM inputs 0B 3PWM, 3 PWM inputs (default) 1B 6PWM, 6 PWM inputs CSO_CAP 9 rw Capacitance connected to the current sense amplifier output (CCSO), see also Chapter 12.12.4 0B 400pF, CCSO < 400 pF (default) 1B 2nF, 400 pF < CCSO < 2.2 nF CSD 8 rw Direction of the current sense amplifier 0B UNI, Unidirectional 1B BI, Bidirectional (default) OCFILT 7:6 rw Overcurrent filter time of CSO 00B 6us, 6 µs (default) 01B 10us, 10 µs 10B 50us, 50 µs 11B 100us, 100 µs CSA_OFF 5 rw CSA OFF 0B CSA_ON, CSA enabled 1B CSA_OFF, CSA disabled (default) OCTH 4:3 rw Overcurrent detection threshold of CSO 00B TH1, VCSO > VCC1/2+2 x VCC1/20 or VCSOx< VCC1/2- 2x VCC1/20 (default) 01B TH2, VCSO > VCC1/2+ 4x VCC1/20 or VCSOx< VCC1/2- 4x VCC1/20 10B TH3, VCSO > VCC1/2+ 5 x VCC1/20 or VCSOx< VCC1/2- 5 xVCC1/20 11B TH4, VCSO > VCC1/2+ 6x VCC1/20 or VCSOx< VCC1/2- 6x VCC1/20 CSAG 2:1 rw Gain of the current sense amplifier 00B 10VV, GDIFF10 (default) 01B 20VV, GDIFF20 10B 40VV, GDIFF40 11B 60VV, GDIFF60 OCEN 0 rw Overcurrent shutdown Enable 0B DISABLED, Disabled 1B ENABLED, Enabled (default) Datasheet 199 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Serial Peripheral Interface Table 62 Reset of CSA Register Reset Type Reset Values POR/Soft reset 0000 0001 0010 0001B Restart 0000 0xxx xxxx xxx1B Datasheet Reset Short Name Reset Mode 200 Note Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Serial Peripheral Interface Drain-Source monitoring threshold LS1-3 LS_VDS VDS monitoring threshold LS1-3 15 14 13 12 (001 0010B) 11 10 9 8 7 Reset Value: see Table 63 6 5 4 3 2 1 0 RES TFVDS RES LS3VDSTH LS2VDSTH LS1VDSTH r rw r rw rw rw Field Bits Type Description RES 15:14 r Reserved. Always read as 0 TFVDS 13:12 rw Filter time of drain-source voltage monitoring 00B 500ns, 0.5 µs (default) 01B 1us, 1 µs 10B 2us, 2 µs 11B 6us, 6 µs RES 11:9 r Reserved, always reads as 0 LS3VDSTH 8:6 rw LS3 drain-source overvoltage threshold 000B 160mV, 0.16 V 001B 200mV, 0.20 V (default) 010B 300mV, 0.30 V 011B 400mV, 0.40 V 100B 500mV, 0.50 V 101B 600mV, 0.60 V 110B 800mV, 0.80 V 111B 2V, 2.0 V LS2VDSTH 5:3 rw LS2 drain-source overvoltage threshold 000B 160mV, 0.16V 001B 200mV, 0.20 V (default) 010B 300mV, 0.30 V 011B 400mV, 0.40 V 100B 500mV, 0.50 V 101B 600mV, 0.60 V 110B 800mV, 0.80 V 111B 2V, 2.0 V LS1VDSTH 2:0 rw LS1 drain-source overvoltage threshold 000B 160mV, 0.16 V 001B 200mV, 0.20 V (default) 010B 300mV, 0.30 V 011B 400mV, 0.40 V 100B 500mV, 0.50 V 101B 600mV, 0.60 V 110B 800mV, 0.80 V 111B 2V, 2.0 V Datasheet 201 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Serial Peripheral Interface Table 63 Reset of LS_VDS Register Reset Type Reset Values Reset Short Name POR/Soft reset 0000 0000 0100 1001B 0000 0000 0000 0000 Restart 0000 000x xxxx xxxxB Datasheet 202 Reset Mode Note Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Serial Peripheral Interface Drain-Source monitoring Threshold HS1-3 HS_VDS VDS monitoring threshold HS1-3 15 14 (001 0011B) 11 10 9 8 7 Reset Value: see Table 64 13 12 6 5 4 3 2 1 0 RES RES DEEP_ ADAP RES HS3VDSTH HS2VDSTH HS1VDSTH r rw rw r rw rw rw Field Bits Type Description RES 15:14 r Reserved. Always read as 0 RES 13 rw Reserved. This bit must be programmed to ‘0‘ DEEP_ADAP 12 rw Deep adaptation enable 0B NO_DEEP_ADAP, Deep adaptation disabled (default) 1B DEEP_ADAP, Deep adaptation enabled RES 11:9 r Reserved, always reads as 0 HS3VDSTH 8:6 rw HS3 drain-source overvoltage threshold 000B 160mV, 0.16 V 001B 200mV, 0.20 V (default) 010B 300mV, 0.30 V 011B 400mV, 0.40 V 100B 500mV, 0.50 V 101B 600mV, 0.60 V 110B 800mV, 0.80 V 111B 2V, 2.0 V HS2VDSTH 5:3 rw HS2 drain-source overvoltage threshold 000B 160mV, 0.16 V 001B 200mV, 0.20 V (default) 010B 300mV, 0.30 V 011B 400mV, 0.40 V 100B 500mV, 0.50 V 101B 600mV, 0.60 V 110B 800mV, 0.80 V 111B 2V, 2.0 V HS1VDSTH 2:0 rw HS1 drain-source overvoltage threshold 000B 160mV, 0.16 V 001B 200mV, 0.20 V (default) 010B 300mV, 0.30 V 011B 400mV, 0.40 V 100B 500mV, 0.50 V 101B 600mV, 0.60 V 110B 800mV, 0.80 V 111B 2V, 2.0 V Datasheet 203 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Serial Peripheral Interface Table 64 Reset of HS_VDS Register Reset Type Reset Values POR/Soft reset 0000 0000 0100 1001B Restart 00xx 000x xxxx xxxxB Datasheet Reset Short Name Reset Mode 204 Note Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Serial Peripheral Interface CCP and times selection CCP_BLK CCP and times selection 15 14 13 12 (001 0100B) 11 10 9 8 7 Reset Value: see Table 65 6 5 4 3 2 1 0 TBLANK TCCP RES CCP_BNK rw rw r rw Field Bits Type Description TBLANK 15:12 rw Blank time nom. tHBxBLANK = 587 ns + 266 x T[3:0]D The CCP_BNK bits select the blank time for the FW or active MOSFET and the half-bridge HBx Reset of active and FW tHBxBLANK: 2450 ns typ. TCCP 11:8 rw Cross-current protection time nom. tHBxCCP = 587 ns + 266 x TCCP[3:0]D The CCP_BNK bits select the cross-current protection time for the FW or active MOSFET and the half-bridge HBx Reset of all active and FW tHBxCCP: 2450 ns typ. RES 7:3 r Reserved, always reads as 0 CCP_BNK 2:0 rw Cross-current and time banking 000B ACT_HB1, Active blank and cross-current prot. times for HB1 (default) 001B ACT_HB2, Active blank and cross-current prot. times for HB2 010B ACT_HB3, Active blank and cross-current prot. times for HB3 011B RES, reserved 100B FW_HB1, FW blank and cross-current prot. times for HB1 101B FW_HB2, FW blank and cross-current prot. times for HB2 110B FW_HB3, FW blank and cross-current prot. for times for HB3 111B RES, reserved Table 65 Reset of CCP_BLK Register Reset Type Reset Values POR/Soft reset 0111 0111 0000 0000B Restart xxxx xxxx 0000 0000B Datasheet Reset Short Name Reset Mode 205 Note Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Serial Peripheral Interface Half-Bridge MODE HBMODE Half-Bridge MODE 15 14 13 (001 0101B) 12 11 10 RES HB3MODE r rw 9 8 7 HB3_ AFW3 PWM_ EN rw rw Reset Value: see Table 66 6 HB2MODE rw 5 4 HB2_ AFW2 PWM_ EN rw rw 3 2 HB1MODE rw 1 0 HB1_ AFW1 PWM_ EN rw rw Field Bits Type Description RES 15:12 r Reserved, always reads as 0 HB3MODE 11:10 rw Half-bridge 3 MODE selection 00B PASSIVE_OFF, LS3 and HS3 are off by passive discharge (default) 01B LS3_ON, LS3 is ON 10B HS3_ON, HS3 is ON 11B ACTIVE_OFF, LS3 and HS3 kept off by the active discharge AFW3 9 rw Active freewheeling for half-bridge 3 during PWM 0B DISABLED, active freewheeling disabled 1B ENABLED, active freewheeling enabled (default) HB3_PWM_EN 8 rw PWM mode for half-bridge 3 0B INACTIVE, PWM deactivated for HB2(default) 1B ACTIVE, PWM activated for HB2 HB2MODE 7:6 rw Half-bridge 2 MODE selection 00B PASSIVE_OFF, LS2 and HS2 are off by passive discharge (default) 01B LS2_ON, LS2 is ON 10B HS2_ON, HS2 is ON 11B ACTIVE_OFF, LS2 and HS2 kept off by the active discharge AFW2 5 rw Active freewheeling for half-bridge 2 during PWM 0B DISABLED, active freewheeling disabled 1B ENABLED, active freewheeling enabled (default) HB2_PWM_EN 4 rw PWM mode for half-bridge 2 0B INACTIVE, PWM deactivated for HB2(default) 1B ACTIVE, PWM activated for HB2 HB1MODE 3:2 rw Half-bridge 1 MODE selection 00B PASSIVE_OFF, LS1 and HS1 are off by passive discharge (default) 01B LS1_ON, LS1 is ON 10B HS1_ON, HS1 is ON 11B ACTIVE_OFF, LS1 and HS1 kept off by the active discharge Datasheet 206 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Serial Peripheral Interface Field Bits Type Description AFW1 1 rw Active freewheeling for half-bridge 1 during PWM 0B DISABLED, active freewheeling disabled 1B ENABLED, active freewheeling enabled (default) HB1_PWM_EN 0 rw PWM mode for half-bridge 1 0B INACTIVE, PWM deactivated for HB1 (default) 1B ACTIVE, PWM activated for HB1 Table 66 Reset of HBMODE Register Reset Type Reset Values POR/Soft reset 0000 0010 0010 0010B Restart 0000 0010 0010 0010B Datasheet Reset Short Name Reset Mode 207 Note Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Serial Peripheral Interface HB pre-charge and pre-discharge time TPRECHG HB pre-charge and pre-discharge time 15 14 13 12 11 10 (001 0110B) 9 8 7 Reset Value: see Table 67 6 5 4 3 2 1 0 RES TPCHG3 TPCHG2 TPCHG1 RES TPCHG_BNK r rw rw rw r rw Field Bits Type Description RES 15:13 r Reserved, always reads as 0 TPCHG3 12:10 rw If TPCHG_BNK=0: precharge time of HB 3, If TPCHG_BNK=1: predischarge time of HB 3 TPCHG2 9:7 rw If TPCHG_BNK=0: precharge time of HB 2, If TPCHG_BNK=1: predischarge time of HB 2 TPCHG1 6:4 rw If TPCHG_BNK=0: precharge time of HB 1, If TPCHG_BNK=1: predischarge time of HB 1 RES 3 r Reserved, always read as 0 TPCHG_BNK 2:0 rw Precharge/predischarge time selection 000B PRECHARGE, Precharge time selected (default) 001B PREDISCHARGE, Predischarge time selected x1xB , wrong setting of TPCHG_BNK 1xxB , wrong setting of TPCHG_BNK Table 67 Reset of TPRECHG Register Reset Type Reset Values POR/Soft reset 0000 0000 0000 0000B Restart 000x xxxx xxxx 0000B Datasheet Reset Short Name Reset Mode 208 Note Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Serial Peripheral Interface Static charge/discharge current ST_ICHG Static charge/discharge current 15 14 13 12 11 (001 0111B) 10 9 8 7 Reset Value: see Table 68 6 5 4 3 2 1 RES ICHGST3 ICHGST2 ICHGST1 r rw rw rw 0 Field Bits Type Description RES 15:12 r Reserved, always read as 0 ICHGST3 11:8 rw Static charge and discharge currents of HB3 Refer to Table 27 Default: 0100B - charge: ICHG16,15.3 mA typ., discharge: IDCHG16, 15.1 mA typ. ICHGST2 7:4 rw Static charge and discharge currents of HB2 Refer to Default: 0100B - charge: ICHG16,15.3 mA typ., discharge: IDCHG16, 15.1 mA typ. ICHGST1 3:0 rw Static charge and discharge currents of HB1 Refer to Table 27 Default: 0100B - charge: ICHG16,15.3 mA typ., discharge: IDCHG16, 15.1 mA typ. Table 68 Reset of ST_ICHG Register Reset Type Reset Values POR/Soft reset 0000 0100 0100 0100B Restart 0000 xxxx xxxx xxxxB Datasheet Reset Short Name Reset Mode 209 Note Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Serial Peripheral Interface HB charge/discharge currents for PWM operation HB_ICHG HB charge/discharge currents for PWM operation (001 1000B) 15 14 13 12 11 10 9 8 7 Reset Value: see Table 69 6 5 4 3 2 1 0 IDCHG ICHG RES ICHG_BNK rw rw r rw Field Bits Type Description IDCHG 15:10 rw If ICHG_BNK =0xxB: Discharge current of HBx active MOSFET If ICHG_BNK=1xxB: Reserved. Always read as ‘0’ Default value for all active MOSFETs discharge currents: 001111B, IDCHG15 Refer to Table 35 for the configuration of the discharge current ICHG 9:4 rw If ICHG_BNK=0xxB: Charge current of HBx active MOSFET If ICHG_BNK=1xxB: Charge and discharge current of HBx FW MOSFETs Default value for all active MOSFETs charge currents and all FW MOSFETs charge/discharge currents: 001101B, ICHG13 Refer to Table 34 for the configuration of the charge current of the active and FW MOSFET Refer to Table 35 for the configuration of the discharge current of the FW MOSFET RES 3 r Reserved, always read as 0 ICHG_BNK 2:0 rw Banking bits for charge and discharge currents of active MOSFETs 000B ACT_HB1, Active MOSFET of HB1 is selected (default) 001B ACT_HB2, Active MOSFET of HB2 is selected 010B ACT_HB3, Active MOSFET of HB3 is selected 011B RES, reserved 100B FW_HB1, FW MOSFET of HB1 is selected 101B FW_HB2, FW MOSFET of HB2 is selected 110B FW_HB3, FW MOSFET of HB3 is selected 111B RES, reserved Table 69 Reset of HB_ICHG Register Reset Type Reset Values POR/Soft reset 0011 1100 1101 0000B Restart xxxx xxxx xxxx 0000B Datasheet Reset Short Name Reset Mode Note POR value valid for ICHG_BNK = 0 210 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Serial Peripheral Interface HB max. pre-charge/pre-discharge in PWM operation current and diagnostic pull-down HB_ICHG_MAX HB max. pre-charge/pre-discharge in PWM operation current and diagnostic pull-down Reset Value: see Table 70 (001 1001B) 15 RES 14 13 12 11 HB3ID HB2ID HB1ID IAG IAG IAG r rrw rw rw 10 9 8 7 6 5 4 3 2 1 0 RES RES ICHGMAX3 ICHGMAX2 ICHGMAX1 r r rw rw rw Field Bits Type Description RES 15 r Reserved, always read as 0 HB3IDIAG 14 rrw Control of HB3 off-state current source and current sink 0B INACTIVE, Pull-down deactivated (default) 1B ACTIVE, Pull-down activated HB2IDIAG 13 rw Control of HB2 pull-down for off-state diagnostic 0B INACTIVE, Pull-down deactivated (default) 1B ACTIVE, Pull-down activated HB1IDIAG 12 rw Control of HB1 pull-down for off-state diagnostic 0B INACTIVE, Pull-down deactivated (default) 1B ACTIVE, Pull-down activated RES 11:8 r Reserved, always read as 0 RES 7:6 r Reserved, always reads as 0 ICHGMAX3 5:4 rw Maximum drive current of HB3 during the precharge and pre-discharge phases1) 00B 31mA, charge ICHG24: typ. 31.6 mA, discharge IDCHG24: typ. 30.9 mA (default) 01B 52mA, charge ICHG32: typ. 52.5 mA, discharge IDCHG32: typ. 51.5 mA 10B 112mA, charge ICHG52: typ. 112.2mA, discharge IDCHG52: typ. 110.8 mA 11B 150mA, charge ICHG63: typ. 150 mA, discharge IDCHG63: typ. 150 mA ICHGMAX2 3:2 rw Maximum drive current of HB2 during the precharge phase and pre-discharge phases1) 00B 31mA, charge ICHG24: typ. 31.6 mA, discharge IDCHG24: typ. 30.9 mA (default) 01B 52mA, charge ICHG32: typ. 52.5 mA, discharge IDCHG32: typ. 51.5 mA 10B 112mA, charge ICHG52: typ. 112.2mA, discharge IDCHG52: typ. 110.8 mA 11B 150mA, charge ICHG63: typ. 150 mA, discharge IDCHG63: typ. 150 mA Datasheet 211 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Serial Peripheral Interface Field Bits Type Description ICHGMAX1 1:0 rw Maximum drive current of HB1 during the precharge and pre-discharge phases1) 00B 31mA, charge ICHG24: typ. 31.6 mA, discharge IDCHG24: typ. 30.9 mA (default) 01B 52mA, charge ICHG32: typ. 52.5 mA, discharge IDCHG32: typ. 51.5 mA 10B 112mA, charge ICHG52: typ. 112.2mA, discharge IDCHG52: typ. 110.8 mA 11B 150mA, charge ICHG63: typ. 150 mA, discharge IDCHG63: typ. 150 mA 1) ICHGMAX is also the current applied during the post-charge of the PWM MOSFET. Table 70 Reset of HB_ICHG_MAX Register Reset Type Reset Values POR/Soft reset 0000 0000 0000 0000B Restart 0xxx 0000 00xx xxxxB Datasheet Reset Short Name Reset Mode 212 Note Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Serial Peripheral Interface HBx pre-charge/pre-dischage initialization configuration in PWM operation HB_PCHG_INIT HBx pre-charge/pre-discharge initialization configuration in PWM operation Reset Value: see Table 71 (001 1010B) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PDCHGINIT PCHGINIT RES INIT_BNK rw rw r rw Field Bits Type Description PDCHGINIT 15:10 rw Initial predischarge current of HBx, IPDCHGINITx The INIT_BNK bits select the addressed half-bridge Default: 001111B Refer to Table 34 PCHGINIT 9:4 rw Initial precharge current of HBx, IPCHGINITx The INIT_BNK bits select the addressed half-bridge Default: 001101B Refer to Table 34 RES 3 r Reserved, always reads as 0 INIT_BNK 2:0 rw Banking bits for Precharge an Predischarge Initial Current 000B HB1, precharge/discharge init. for HB1 selected (default) 001B HB2, precharge/discharge init. for HB2 selected 010B HB3, precharge/discharge init. for HB3 selected 010B RES, reserved 011B RES, reserved 1xxB , wrong setting of INIT_BANK Table 71 Reset of HB_PCHG_INIT Register Reset Type Reset Values POR/Soft reset 0011 1100 1101 0000B Restart xxxx xxxx xxxx 0000B Datasheet Reset Short Name Reset Mode 213 Note Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Serial Peripheral Interface HBx inputs TDON configuration TDON_HB_CTRL HBx inputs TDON configuration 15 14 13 12 11 (001 1011B) 10 9 8 7 Reset Value: see Table 72 6 5 4 3 2 1 0 RES TDON RES HB_TDON_BNK r rw r rw Field Bits Type Description RES 15:14 r Reserved, always read as 0 TDON 13:8 rw Turn-on delay time of active MOSFET of HBx The HB_TDON_BNK bits selects the turn-on delay time of the active MOSFET of the half-bridge HBx Nominal tDON = 53.3 ns x TDON[5:0]D Default: 00 1100B : 640 ns typ. RES 7:3 r Reserved, always read as 0 HB_TDON_BNK 2:0 rw Banking bits for turn-on delay time 000B HB1, tDON of HB1 selected (default) 001B HB2, tDON of HB2 selected 010B HB3, tDON of HB3 selected 011B RES, reserved 1xxB , wrong setting of PWM_TDON_BNK Table 72 Reset of TDON_HB_CTRL Register Reset Type Reset Values POR/Soft reset 0000 1100 0000 0000B Restart 00xx xxxx 0000 0000B Datasheet Reset Short Name Reset Mode 214 Note Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Serial Peripheral Interface HBx TDOFF configuration TDOFF_HB_CTRL HBx TDOFF configuration 15 14 13 12 (001 1100B) 11 10 9 8 7 Reset Value: see Table 73 6 5 4 3 2 1 0 RES TDOFF RES HB_TDOFF_BNK r rw r rw Field Bits Type Description RES 15:14 r Reserved, always read as 0 TDOFF 13:8 rw Turn-off delay time of active MOSFET of HBx The HB_TDOFF_BNK bits selects the turn-off delay time of the active MOSFET of the half-bridge HBx Nominal tDOFF = 53.3 ns x TDOFF[5:0]D Default: 0000 1100B : 640 ns RES 7:3 r Reserved, always read as 0 HB_TDOFF_BNK 2:0 rw Banking bits for turn-off delay time 000B HB1, tDOFF of HB1 selected (default) 001B HB2, tDOFF of HB2 selected 010B HB3, tDOFF of HB3 selected 1xxB , wrong setting of PWM_TDOFF_BNK Table 73 Reset of TDOFF_HB_CTRL Register Reset Type Reset Values POR/Soft reset 0000 1100 0000 0000B Restart 00xx xxxx 0000 0000B Datasheet Reset Short Name Reset Mode 215 Note Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Serial Peripheral Interface Brake control BRAKE Brake control 15 (001 1101B) 14 RES 13 12 11 10 9 8 7 Reset Value: see Table 74 6 5 4 SLAM SLAM SLAM VDST PARK_ OV_B TBLK_ BRK_E RK_E RES _LS3_ _LS2_ _LS1_ SLAM H_BR BRK DIS DIS DIS K N N r r rw rw rw rw rw rw rw rw 3 2 1 0 RES OV_BRK_TH rw rw Field Bits Type Description RES 15:14 r Reserved, always read as 0 RES 13 r Reserved, always read as 0 SLAM_LS3_DIS 12 rw LS3 output disable during SLAM mode 0B ACTIVE, LS3 control active in Slam mode (default) 1B DISABLED, LS3 control disabled in Slam mode SLAM_LS2_DIS 11 rw LS2 output disable during SLAM mode 0B ACTIVE, LS2 control active in Slam mode (default) 1B DISABLED, LS2 control disabled in Slam mode SLAM_LS1_DIS 10 rw LS1 output disable during SLAM mode 0B ACTIVE, LS1 control active in Slam mode (default) 1B DISABLED, LS1 control disabled in Slam mode SLAM 9 rw Slam mode 0B INACTIVE, Slam mode deactivated (default) 1B AVTIVE, Slam mode activated VDSTH_BRK 8 rw VDS Overvoltage for LS1-3 during braking 0B 800mV, VVDSMONTH0_BRAKE, 0.8 V, typ. (default) 1B 220mV, VVDSMONTH1_BRAKE, 0.22 V typ. TBLK_BRK 7 rw Blank time of VDS overvoltage during braking 0B 7uS, tBLK_BRAKE1,7 µs typ. 1B 11uS, tBLK_BRAKE2, 11 µs typ. (default) PARK_BRK_EN 6 rw Parking brake enable 0B DISABLED, Parking brake disabled (default) 1B ENABLED, Parking brake enabled OV_BRK_EN 5 rw Overvoltage brake enable 0B DISABLED, Overvoltage brake disabled 1B ENABLED, Overvoltage brake enabled (default) RES 4:3 rw Reserved, to be set to 0 Datasheet 216 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Serial Peripheral Interface Field Bits Type Description OV_BRK_TH 2:0 rw Overvoltage brake threshold 000B 27V, typ. 27V (default) 001B 28V, typ. 28V 010B 29V, typ. 29V 011B 30V, typ. 30V 100B 31V, typ. 31V 101B 32V, typ. 32V 110B 33V, typ. 33V 111B 34V, typ. 34V Table 74 Reset of BRAKE Register Reset Type Reset Values POR/Soft reset 0000 0000 1010 0000B Restart 000x xxxx xxx0 0xxxB Note: Datasheet Reset Short Name Reset Mode Note For min and max values of OV_BRK_TH, refer to Chapter 12.13. 217 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Serial Peripheral Interface 13.5.3 Selective Wake Registers CAN Selective Wake Control SWK_CTRL CAN Selective Wake Control 15 14 13 12 (011 0000B) 11 10 9 8 7 Reset Value: see Table 75 6 5 4 3 2 1 0 RES OSC_ CAL TRIM_EN CANT O_MA SK RES CFG_V AL r rw rw rw r rwh Field Bits Type Description RES 15:8 r Reserved, always reads as 0 OSC_CAL 7 rw Oscillator Calibration Mode 0B DISABLED, Oscillator Calibration is disabled 1B ENABLED, Oscillator Calibration is enabled TRIM_EN 6:5 rw (Un)locking mechanism of oscillator recalibration 00B LOCKED, locked 01B LOCKED, locked 10B LOCKED, locked 11B UNLOCKED, unlocked CANTO_ MASK 4 rw CAN Time Out Masking 0B MASKED, CAN time-out is masked - no interrupt (on pin INTN) is triggered 1B UNMASKED, CAN time-out is signaled on INTN RES 3:1 r Reserved, always reads as 0 CFG_VAL 0 rwh SWK Configuration valid 0B NOT_VALID, Configuration is not valid (SWK not possible) 1B VALID, SWK configuration valid, needs to be set to enable SWK Table 75 Reset of SWK_CTRL Register Reset Type Reset Values POR/Soft reset 0000 0000 0000 0000B Restart 0000 0000 xxxx 0000B Reset Short Name Reset Mode Note Notes 1. TRIM_EN unlocks the oscillation calibration mode. Only the bit combination ‘11’ is the valid unlock. The pin TXDCAN is used for oscillator synchronisation (trimming). 2. The microcontroller needs to validate the SWK configuration and set ‘CFG_VAL’ to ‘1’. The device will only enable SWK if CFG_VAL’ to ‘1’. The bit will be cleared automatically by the device after a wake up or POR or if a SWK configuration data is changed by the microcontroller. Datasheet 218 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Serial Peripheral Interface 3. CANTO bit will only be updated inside BUS_STAT while CAN_2 is set. Therefore, an interrupt is only signaled upon occurrence of CANTO while CAN_2 (SWK is enabled) is set in Normal Mode and Stop Mode. SWK Bit Timing Control SWK_BTL1_CTRL SWK Bit Timing Control 15 14 13 12 (011 0001B) 11 10 9 8 7 Reset Value: see Table 76 6 5 4 3 SP RES TBIT rw r rw 2 1 0 Field Bits Type Description SP 15:10 rw Sampling Point Position Represents the sampling point position (fractional number < 1). Example: 0011 0011 = 0.796875 (~80%) RES 9:8 r Reserved, always reads as 0 TBIT 7:0 rw Number of Time Quanta in a Bit Time Represents the number of time quanta in a bit time. Quanta is depending on x from the x register. Table 76 Reset of SWK_BTL1_CTRL Register Reset Type Reset Values POR/Soft reset 1100 1100 1001 0110B Restart xxxx xx00 xxxx xxxxB Datasheet Reset Short Name Reset Mode 219 Note Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Serial Peripheral Interface SWK WUF Identifier bits SWK_ID1_CTRL SWK WUF Identifier bits 28...13 (011 0010B) Reset Value: see Table 77 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID28 ID27 ID26 ID25 ID24 ID23 ID22 ID21 ID20 ID19 ID18 ID17 ID16 ID15 ID14 ID13 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Field Bits Type Description ID28 15 rw WUF Identifier Bit 28 ID27 14 rw WUF Identifier Bit 27 ID26 13 rw WUF Identifier Bit 26 ID25 12 rw WUF Identifier Bit 25 ID24 11 rw WUF Identifier Bit 24 ID23 10 rw WUF Identifier Bit 23 ID22 9 rw WUF Identifier Bit 22 ID21 8 rw WUF Identifier Bit 21 ID20 7 rw WUF Identifier Bit 20 ID19 6 rw WUF Identifier Bit 19 ID18 5 rw WUF Identifier Bit 18 ID17 4 rw WUF Identifier Bit 17 ID16 3 rw WUF Identifier Bit 16 ID15 2 rw WUF Identifier Bit 15 ID14 1 rw WUF Identifier Bit 14 ID13 0 rw WUF Identifier Bit 13 Table 77 Reset of SWK_ID1_CTRL Register Reset Type Reset Values POR/Soft reset 0000 0000 0000 0000B Restart xxxx xxxx xxxx xxxxB Datasheet Reset Short Name Reset Mode 220 Note Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Serial Peripheral Interface SWK WUF Identifier bits SWK_ID0_CTRL SWK WUF Identifier bits 12...0 (011 0011B) Reset Value: see Table 78 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID12 ID11 ID10 ID9 ID8 ID7 ID6 ID5 RES ID4 ID3 ID2 ID1 ID0 RTR IDE rw rw rw rw rw rw rw rw r rw rw rw rw rw rw rw Field Bits Type Description ID12 15 rw WUF Identifier Bit 12 ID11 14 rw WUF Identifier Bit 11 ID10 13 rw WUF Identifier Bit 10 ID9 12 rw WUF Identifier Bit 9 ID8 11 rw WUF Identifier Bit 8 ID7 10 rw WUF Identifier Bit 7 ID6 9 rw WUF Identifier Bit 6 ID5 8 rw WUF Identifier Bit 5 RES 7 r Reserved, always reads as 0 ID4 6 rw WUF Identifier Bit 4 ID3 5 rw WUF Identifier Bit 3 ID2 4 rw WUF Identifier Bit 2 ID1 3 rw WUF Identifier Bit 1 ID0 2 rw WUF Identifier Bit 0 RTR 1 rw Remote Transmission Request Field (acc. ISO118982:2016) 0B NORMAL, Normal Data Frame 1B REMOTE, Remote Transmission Request IDE 0 rw Identifier Extension Bit 0B STD, Standard Identifier Length (11 bit) 1B EXT, Extended Identifier Length (29 bit) Table 78 Reset of SWK_ID0_CTRL Register Reset Type Reset Values POR/Soft reset 0000 0000 0000 0000B Restart xxxx xxxx 0xxx xxxxB Datasheet Reset Short Name Reset Mode 221 Note Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Serial Peripheral Interface SWK WUF Identifier Mask bits 28...13 SWK_MASK_ID1_CTRL SWK WUF Identifier Mask bits 28...13 15 14 13 12 11 10 (011 0100B) 9 8 7 Reset Value: see Table 79 6 5 4 3 2 1 0 MASK MASK MASK MASK MASK MASK MASK MASK MASK MASK MASK MASK MASK MASK MASK MASK _ID28 _ID27 _ID26 _ID25 _ID24 _ID23 _ID22 _ID21 _ID20 _ID19 _ID18 _ID17 _ID16 _ID15 _ID14 _ID13 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Field Bits Type Description MASK_ID28 15 rw WUF Identifier Mask Bit 28 0B UNMASKED, Unmasked - bit is ignored 1B MASKED, Masked - bit is compared in CAN frame MASK_ID27 14 rw WUF Identifier Mask Bit 27 0B UNMASKED, Unmasked - bit is ignored 1B MASKED, Masked - bit is compared in CAN frame MASK_ID26 13 rw WUF Identifier Mask Bit 26 0B UNMASKED, Unmasked - bit is ignored 1B MASKED, Masked - bit is compared in CAN frame MASK_ID25 12 rw WUF Identifier Mask Bit 25 0B UNMASKED, Unmasked - bit is ignored 1B MASKED, Masked - bit is compared in CAN frame MASK_ID24 11 rw WUF Identifier Mask Bit 24 0B UNMASKED, Unmasked - bit is ignored 1B MASKED, Masked - bit is compared in CAN frame MASK_ID23 10 rw WUF Identifier Mask Bit 23 0B UNMASKED, Unmasked - bit is ignored 1B MASKED, Masked - bit is compared in CAN frame MASK_ID22 9 rw WUF Identifier Mask Bit 22 0B UNMASKED, Unmasked - bit is ignored 1B MASKED, Masked - bit is compared in CAN frame MASK_ID21 8 rw WUF Identifier Mask Bit 21 0B UNMASKED, Unmasked - bit is ignored 1B MASKED, Masked - bit is compared in CAN frame MASK_ID20 7 rw WUF Identifier Mask Bit 20 0B UNMASKED, Unmasked - bit is ignored 1B MASKED, Masked - bit is compared in CAN frame MASK_ID19 6 rw WUF Identifier Mask Bit 19 0B UNMASKED, Unmasked - bit is ignored 1B MASKED, Masked - bit is compared in CAN frame MASK_ID18 5 rw WUF Identifier Mask Bit 18 0B UNMASKED, Unmasked - bit is ignored 1B MASKED, Masked - bit is compared in CAN frame Datasheet 222 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Serial Peripheral Interface Field Bits Type Description MASK_ID17 4 rw WUF Identifier Mask Bit 17 0B UNMASKED, Unmasked - bit is ignored 1B MASKED, Masked - bit is compared in CAN frame MASK_ID16 3 rw WUF Identifier Mask Bit 16 0B UNMASKED, Unmasked - bit is ignored 1B MASKED, Masked - bit is compared in CAN frame MASK_ID15 2 rw WUF Identifier Mask Bit 15 0B UNMASKED, Unmasked - bit is ignored 1B MASKED, Masked - bit is compared in CAN frame MASK_ID14 1 rw WUF Identifier Mask Bit 14 0B UNMASKED, Unmasked - bit is ignored 1B MASKED, Masked - bit is compared in CAN frame MASK_ID13 0 rw WUF Identifier Mask Bit 13 0B UNMASKED, Unmasked - bit is ignored 1B MASKED, Masked - bit is compared in CAN frame Table 79 Reset of SWK_MASK_ID1_CTRL Register Reset Type Reset Values POR/Soft reset 0000 0000 0000 0000B Restart xxxx xxxx xxxx xxxxB Datasheet Reset Short Name Reset Mode 223 Note Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Serial Peripheral Interface SWK WUF Identifier Mask bits 12...0 SWK_MASK_ID0_CTRL SWK WUF Identifier Mask bits 12...0 15 14 13 12 11 10 (011 0101B) 9 8 7 Reset Value: see Table 80 6 5 4 3 2 MASK MASK MASK MASK MASK MASK MASK MASK MASK MASK MASK MASK MASK RES _ID4 _ID3 _ID2 _ID1 _ID0 _ID12 _ID11 _ID10 _ID9 _ID8 _ID7 _ID6 _ID5 rw rw rw rw rw rw rw rw r rw rw rw rw rw 1 0 RES r Field Bits Type Description MASK_ID12 15 rw WUF Identifier Mask Bit 12 0B UNMASKED, Unmasked - bit is ignored 1B MASKED, Masked - bit is compared in CAN frame MASK_ID11 14 rw WUF Identifier Mask Bit 11 0B UNMASKED, Unmasked - bit is ignored 1B MASKED, Masked - bit is compared in CAN frame MASK_ID10 13 rw WUF Identifier Mask Bit 10 0B UNMASKED, Unmasked - bit is ignored 1B MASKED, Masked - bit is compared in CAN frame MASK_ID9 12 rw WUF Identifier Mask Bit 9 0B UNMASKED, Unmasked - bit is ignored 1B MASKED, Masked - bit is compared in CAN frame MASK_ID8 11 rw WUF Identifier Mask Bit 8 0B UNMASKED, Unmasked - bit is ignored 1B MASKED, Masked - bit is compared in CAN frame MASK_ID7 10 rw WUF Identifier Mask Bit 7 0B UNMASKED, Unmasked - bit is ignored 1B MASKED, Masked - bit is compared in CAN frame MASK_ID6 9 rw WUF Identifier Mask Bit 6 0B UNMASKED, Unmasked - bit is ignored 1B MASKED, Masked - bit is compared in CAN frame MASK_ID5 8 rw WUF Identifier Mask Bit 5 0B UNMASKED, Unmasked - bit is ignored 1B MASKED, Masked - bit is compared in CAN frame RES 7 r Reserved, always reads as 0 MASK_ID4 6 rw WUF Identifier Mask Bit 4 0B UNMASKED, Unmasked - bit is ignored 1B MASKED, Masked - bit is compared in CAN frame MASK_ID3 5 rw WUF Identifier Mask Bit 3 0B UNMASKED, Unmasked - bit is ignored 1B MASKED, Masked - bit is compared in CAN frame MASK_ID2 4 rw WUF Identifier Mask Bit 2 0B UNMASKED, Unmasked - bit is ignored 1B MASKED, Masked - bit is compared in CAN frame Datasheet 224 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Serial Peripheral Interface Field Bits Type Description MASK_ID1 3 rw WUF Identifier Mask Bit 1 0B UNMASKED, Unmasked - bit is ignored 1B MASKED, Masked - bit is compared in CAN frame MASK_ID0 2 rw WUF Identifier Mask Bit 0 0B UNMASKED, Unmasked - bit is ignored 1B MASKED, Masked - bit is compared in CAN frame RES 1:0 r Reserved, always reads as 0 Table 80 Reset of SWK_MASK_ID0_CTRL Register Reset Type Reset Values POR/Soft reset 0000 0000 0000 0000B Restart xxxx xxxx 0xxx xx00B Datasheet Reset Short Name Reset Mode 225 Note Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Serial Peripheral Interface SWK Frame Data Length Code Control SWK_DLC_CTRL SWK Frame Data Length Code Control 15 14 13 12 11 (011 0110B) 10 9 8 7 Reset Value: see Table 81 6 5 4 3 2 1 RES DLC r rw Field Bits Type Description RES 15:4 r Reserved, always reads as 0 DLC 3:0 rw Payload length in number of bytes 0000B0, Frame Data Length = 0 or cleared 0001B1, Frame Data Length = 1 0010B2, Frame Data Length = 2 0011B3, Frame Data Length = 3 0100B4, Frame Data Length = 4 0101B5, Frame Data Length = 5 0110B6, Frame Data Length = 6 0111B7, Frame Data Length = 7 1000B8, to 1111B Frame Data Length = 8 Table 81 Reset of SWK_DLC_CTRL Register Reset Type Reset Values POR/Soft reset 0000 0000 0000 0000B Restart 0000 0000 0000 xxxxB Note: Datasheet 0 Reset Short Name Reset Mode Note The number of transmitted bytes in the data field has to be indicated by the DLC. The DLC value consists of four bits. The admissible number of data bytes for a data frame is in a range from zero to eight. DLCs in the range of zero to seven indicates data fields of length of zero to seven bytes. DLCs in the range from eight to fifteen indicate data fields with a length of eight bytes. The configured DLC value has to match bit by bit with the DLC in the received wake-up frame (refer also to Chapter 5.9.2.2). 226 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Serial Peripheral Interface SWK Data7-Data6 Register SWK_DATA3_CTRL SWK Data7-Data6 Register 15 14 13 12 (011 0111B) 11 10 9 8 7 Reset Value: see Table 82 6 5 4 3 DATA7 DATA6 rw rw 2 Field Bits Type Description DATA7 15:8 rw Data7 byte content(bit0=LSB; bit7=MSB) DATA6 7:0 rw Data6 byte content(bit0=LSB; bit7=MSB) Table 82 0 Reset of SWK_DATA3_CTRL Register Reset Type Reset Values POR/Soft reset 0000 0000 0000 0000B Restart xxxx xxxx xxxx xxxxB Datasheet 1 Reset Short Name Reset Mode 227 Note Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Serial Peripheral Interface SWK Data5-Data4 Register SWK_DATA2_CTRL SWK Data5-Data4 Register 15 14 13 12 (011 1000B) 11 10 9 8 7 Reset Value: see Table 83 6 5 4 3 DATA5 DATA4 rw rw 2 Field Bits Type Description DATA5 15:8 rw Data5 byte content(bit0=LSB; bit7=MSB) DATA4 7:0 rw Data4 byte content(bit0=LSB; bit7=MSB) Table 83 0 Reset of SWK_DATA2_CTRL Register Reset Type Reset Values POR/Soft reset 0000 0000 0000 0000B Restart xxxx xxxx xxxx xxxxB Datasheet 1 Reset Short Name Reset Mode 228 Note Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Serial Peripheral Interface SWK Data3-Data2 Register SWK_DATA1_CTRL SWK Data3-Data2 Register 15 14 13 12 (011 1001B) 11 10 9 8 7 Reset Value: see Table 84 6 5 4 3 DATA3 DATA2 rw rw 2 Field Bits Type Description DATA3 15:8 rw Data3 byte content(bit0=LSB; bit7=MSB) DATA2 7:0 rw Data2 byte content(bit0=LSB; bit7=MSB) Table 84 0 Reset of SWK_DATA1_CTRL Register Reset Type Reset Values POR/Soft reset 0000 0000 0000 0000B Restart xxxxx xxxx xxxx xxxxB Datasheet 1 Reset Short Name Reset Mode 229 Note Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Serial Peripheral Interface SWK Data1-Data0 Register SWK_DATA0_CTRL SWK Data1-Data0 Register 15 14 13 12 (011 1010B) 11 10 9 8 7 Reset Value: see Table 85 6 5 4 3 DATA1 DATA0 rw rw 2 Field Bits Type Description DATA1 15:8 rw Data1 byte content(bit0=LSB; bit7=MSB) DATA0 7:0 rw Data0 byte content(bit0=LSB; bit7=MSB) Table 85 0 Reset of SWK_DATA0_CTRL Register Reset Type Reset Values POR/Soft reset 0000 0000 0000 0000B Restart xxxx xxxx xxxx xxxxB Datasheet 1 Reset Short Name Reset Mode 230 Note Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Serial Peripheral Interface CAN FD Configuration Control Register SWK_CAN_FD_CTRL CAN FD Configuration Control Register 15 14 13 12 11 10 (011 1011B) 9 8 7 Reset Value: see Table 86 6 5 4 DIS_E RR_C RES NT RES r rwh r 3 2 1 0 FD_FILTER CAN_F D_EN rw rw Field Bits Type Description RES 15:6 r Reserved, always reads as 0 DIS_ERR_ CNT 5 rwh Error Counter Disable Function 0B ENABLED, Error Counter is enabled during SWK 1B DISABLED, Error counter is disabled during SWK only if CAN_FD_EN = ‘1’ RES 4 r Reserved, always reads as 0 FD_FILTER 3:1 rw CAN FD Dominant Filter Time 000B 50ns, 50 ns 001B 100ns, 100 ns 010B 150ns, 150 ns 011B 200ns, 200 ns 100B 250ns, 250 ns 101B 300ns, 300 ns 110B 350ns, 350 ns 111B 775ns, 775 ns CAN_FD_EN 0 rw Enable CAN FD Tolerant Mode 0B DISABLED, CAN FD Tolerant Mode disabled 1B ENABLED, CAN FD Tolerant Mode enabled Table 86 Reset of SWK_CAN_FD_CTRL Register Reset Type Reset Values POR/Soft reset 0000 0000 0000 0000B Restart 0000 0000 00x0 xxxxB Reset Short Name Reset Mode Note Notes 1. DIS_ERR_ CNT is cleared by the device at tsilence expiration. 2. The Normal Mode CAN Receiver (RX_WK_SEL = 0B) has to selected with a CAN FD tolerant operation for baud rates > 2 MBit/s. Datasheet 231 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Serial Peripheral Interface 13.5.4 Selective Wake trim and configuration Registers SWK Oscillator Trimming and option Register SWK_OSC_TRIM_CTRL SWK Oscillator Trimming and option Register (011 1100B) 13 12 11 10 9 8 7 Reset Value: see Table 87 15 14 6 5 4 3 2 RES RX_W K_SEL RES TEMP_COEF TRIM_OSC r rw r rw rw 1 0 Field Bits Type Description RES 15 r Reserved, always reads as 0 RX_WK_SEL 14 rw SWK Receiver selection (only accessible if TRIM_EN = ‘11’) 0B LOW_POWER, Low-Power Receiver selected during SWK 1B STD, Standard Receiver selected during SWK RES 13:12 r Reserved, always reads as 0 TEMP_COEF 11:7 rw Trimming of temp_coef (only writable if TRIM_EN = ‘11’) TRIM_OSC 6:0 rw Trimming of oscillator (only writable if TRIM_EN = ‘11’) Table 87 Reset of SWK_OSC_TRIM_CTRL Register Reset Type Reset Values POR/Soft reset 0000 0000 0000 0000B Restart 0x00 xxxx xxxx xxxx B Reset Short Name Reset Mode Note Notes 1. The bit RX_WK_SEL is used to select the respective receiver during Selective Wake operation. The lowest quiescent current during Frame Detect Mode is achieved with the default setting RX_WK_SEL = ‘0’, i.e. the Low-Power Receiver is already selected. 2. TRIM_OSC[6:0] represent the 128-steps coarse trimming range, which is not monotonous. It is not recommended to change these values. Datasheet 232 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Serial Peripheral Interface SWK Oscillator Calibration Register SWK_OSC_CAL_STAT SWK Oscillator Calibration Register 15 14 13 12 11 10 (011 1101B) 9 8 7 Reset Value: see Table 88 6 5 4 3 OSC_CAL_H OSC_CAL_L r r 2 Field Bits Type Description OSC_CAL_H 15:8 r Oscillator Calibration High Register OSC_CAL_L 7:0 r Oscillator Calibration Low Register Table 88 0 Reset of SWK_OSC_CAL_STAT Register Reset Type Reset Values POR/Soft reset 0000 0000 0000 0000B Restart xxxx xxxx xxxx xxxx B Datasheet 1 Reset Short Name Reset Mode 233 Note Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Serial Peripheral Interface Clock Data Recovery Control Register SWK_CDR_CTRL Clock Data Recovery Control Register 15 14 13 12 11 10 (011 1110B) 9 8 Reset Value: see Table 89 7 6 5 4 3 2 1 0 RES SEL_OSC_CL K RES SELFILT RES CDR_E N r rw r rw r rw Field Bits Type Description RES 15:7 r Reserved, always reads as 0 SEL_OSC_CLK 6:5 rw Input Frequency for CDR module See Table 90 and Table 91 RES 4 r Reserved, always reads as 0 SELFILT 3:2 rw Select Time Constant of Filter 00B 8, Time constant 8 01B 16, Time constant 16 (default) 10B 32, Time constant 32 11B ADAPTIVE, adapt distance between falling edges 2, 3 bit: Time constant 32 distance between f. edges 4, 5, 6, 7, 8 bit: Time constant 16 distance between falling edges 9, 10 bit: Time constant 8 RES 1 r Reserved, always reads as 0 CDR_EN 0 rw Enable CDR 0B DISABLED, CDR disabled 1B ENABLED, CDR enabled Table 89 Reset of SWK_CDR_CTRL Register Reset Type Reset Values POR/Soft reset 0000 0000 0000 0100B Restart 0000 0000 0xx0 xx0xB Table 90 Reset Short Name Reset Mode Frequency Settings of Internal Clock for the CDR SEL_OSC_CLK[1:0] int. Clock for CDR 00 75 MHz 01 37.5 MHz 10 18.75 MHz 11 9.375 MHz Datasheet Note 234 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Serial Peripheral Interface Table 91 Recommended CDR Settings for Different Baud Rates SEL_OSC_CLK [1:0] Baudrate SWK_BTL1_CTRL Value SWK_CDR_LIMIT Value 00 500k xxxx xxxx 1001 0110 1001 1101 1000 1111 01 500k xxxx xxxx 0100 1011 0100 1110 0100 0111 10 500k CDR Setting not recommended for this baudrate due to insufficient precision 11 500k CDR Setting not recommended for this baudrate due to insufficient precision 00 250k CDR Setting not to be used due to excessive time quanta (counter overflow) 01 250k xxxx xxxx 1001 0110 1001 1101 1000 1111 10 250k xxxx xxxx 0100 1011 0100 1110 0100 0111 11 250k CDR Setting not recommended for this baudrate due to insufficient precision 00 125k CDR Setting not to be used due to excessive time quanta (counter overflow) 01 125k CDR Setting not to be used due to excessive time quanta (counter overflow) 10 125k xxxx xxxx 1001 0110 1001 1101 1000 1111 11 125k xxxx xxxx 0100 1011 0100 1110 0100 0111 Datasheet 235 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Serial Peripheral Interface SWK Clock Data Recovery Limit Control SWK_CDR_LIMIT SWK Clock Data Recovery Limit Control 15 14 13 12 11 10 (011 1111B) 9 8 7 Reset Value: see Table 92 6 5 4 3 CDR_LIM_H CDR_LIM_L rw rw 2 1 0 Field Bits Type Description CDR_LIM_H 15:8 rw Upper Bit Time Detection Range of Clock and Data Recovery x values > + 5% will be clamped CDR_LIM_L 7:0 rw Lower Bit Time Detection Range of Clock and Data Recovery x values > - 5% will be clamped Table 92 Reset of SWK_CDR_LIMIT Register Reset Type Reset Values POR/Soft reset 1001 1101 1000 1111B Restart xxxx xxxx xxxx xxxxB Datasheet Reset Short Name Reset Mode 236 Note Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Serial Peripheral Interface 13.6 SPI status information registers READ/CLEAR Operation (see also Chapter 13.3): • One 32-bit SPI command consist of four bytes: - The 7-bit address and one additional bit for the register access mode and - following the two data bytes and the CRC. The numbering of following bit definitions refers to the data byte and correspond to the bits D0...D7 and to the SPI bits 8...23 (see also figure). • There are two different bit types: - ‘r’ = READ: read only bits (or reserved bits). - ‘rc’ = READ/CLEAR: readable and clearable bits. • Reading a register is done word wise by setting the SPI bit 7 to “0” (= Read Only). • Clearing a register is done word wise by setting the SPI bit 7 to “1”. No single bits can be cleared. Therefore the content of a SPI message (bit 8..23) doesn’t matter. • SPI status registers are in general not cleared or changed automatically (an exception are the x bits). This must be done by the microcontroller via SPI command. The registers are addressed wordwise. Table 93 Register Overview Register Short Name Register Long Name Offset Address Page Number SPI status information registers, Device Status Registers SUP_STAT Supply Voltage Fail Status 1000000B 239 THERM_STAT Thermal Protection Status 1000001B 241 DEV_STAT Device Information Status 1000010B 242 BUS_STAT Bus Communication Status 1000011B 244 WK_STAT Wake-up Source and Information Status 1000100B 246 WK_LVL_STAT WK Input Level 1000101B 247 HS_OL_OC_OT_STAT High-Side Switch Status 1000110B 248 SPI status information registers, Status registers bridge driver GEN_STAT GEN Status register 1010000B 250 TDREG Turn-on/off delay regulation register 1010001B 252 DSOV Drain-source overvoltage HBVOUT 1010010B 254 EFF_TDON_OFF1 Effective MOSFET turn-on/off delay - PWM halfbridge 1 1010011B 256 EFF_TDON_OFF2 Effective MOSFET turn-on/off delay - PWM halfbridge 2 1010100B 257 EFF_TDON_OFF3 Effective MOSFET turn-on/off delay - PWM halfbridge 3 1010101B 258 TRISE_FALL1 MOSFET rise/fall time - PWM half-bridge 1 1010111B 259 TRISE_FALL2 MOSFET rise/fall time - PWM half-bridge 2 1011000B 260 TRISE_FALL3 MOSFET rise/fall time - PWM half-bridge 3 1011001B 261 1100000B 262 SPI status information registers, Selective wake status registers SWK_STAT Datasheet Selective Wake Status 237 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Serial Peripheral Interface Table 93 Register Overview (cont’d) Register Short Name Register Long Name Offset Address Page Number SWK_ECNT_STAT Selective Wake ECNT Status 1100001B 263 SWK_CDR_STAT Selective Wake CDR Status 1100011B 264 1110000B 265 SPI status information registers, Family and product information register FAM_PROD_STAT Datasheet Family and Product Identification Register 238 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Serial Peripheral Interface 13.6.1 Device Status Registers Supply Voltage Fail Status SUP_STAT Supply Voltage Fail Status 15 14 13 POR RES rc r 12 (100 0000B) 11 10 9 8 7 Reset Value: see Table 94 6 5 4 3 2 1 0 CP_O VCC1_ HS_U HS_O VSINT VSINT VCC1_ VCC1_ VCC1_ VCC1_ VS_UV VS_OV CP_UV T UV_FS V V _UV _OV SC UV OV WARN rc rc rc rc rc rc rc rc rc rc rc rc rc Field Bits Type Description POR 15 rc Power-On reset detection 0B NO_POR, No POR 1B POR, POR occurred RES 14:13 r Reserved, always reads as 0 CP_OT 12 rc Charge pump overtemperature 0B NO_CP_OT, No charge pump OT detected 1B CP_OT, Charge pump OT detected VCC1_UV_FS 11 rc 4th consecutive VCC1 UV-Detection 0B NO_FAILSAFE, No Fail-Safe Mode entry due to 4th consecutive VCC1_UV 1B FAILSAFE, Fail-Safe Mode entry due to 4th consecutive VCC1_UV HS_UV 10 rc HS Supply UV-Detection 0B NO_UV, No Undervoltage 1B UV_EVENT, HS Supply Undervoltage detected HS_OV 9 rc HS Supply OV-Detection 0B NO_OV, No Overvoltage 1B OV_EVENT, HS Supply Overvoltage detected VSINT_UV 8 rc VSINT UV-Detection 0B NO_UV, No Undervoltage 1B UV_EVENT, VSINT Undervoltage detected VSINT_OV 7 rc VSINT OV-Detection 0B NO_OV, No Overvoltage 1B OV_EVENT, VSINT Overvoltage detected VS_UV 6 rc VS Undervoltage Detection (VS,UV) 0B NO_VS, No VS undervoltage detected 1B VS_EVENT, VS undervoltage detected (detection is only active when VCC1 is enabled) VS_OV 5 rc VS Overvoltage Detection (VS,OV) 0B NO_OV, No VS overvoltage detected 1B OV_EVENT, VS overvoltage detected (detection is only active when VCC1 is enabled) Datasheet 239 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Serial Peripheral Interface Field Bits Type Description CP_UV 4 rc CP_UV 0B NO_UV, No CP undervoltage detected 1B UV_EVENT, CP undervoltage detected VCC1_SC 3 rc VCC1 SC 0B NO_SC, No VCC1 short to GND detected 1B SC_EVENT, VCC1 short to GND VCC1_UV 2 rc VCC1 UV-Detection (due to Vrtx reset) 0B NO_UV, No VCC1_UV detection 1B UV_EVENT, VCC1 undervoltage detected VCC1_OV 1 rc VCC1 Overvoltage Detection 0B NO_OV, No VCC1 overvoltage warning 1B OV_EVENT, VCC1 overvoltage detected VCC1_WARN 0 rc VCC1 Undervoltage Prewarning 0B NO_UV, No VCC1 undervoltage prewarning 1B UV_PREWARN, VCC1 undervoltage prewarning detected Table 94 Reset of SUP_STAT Register Reset Type Reset Values POR/Soft reset y000 0000 0000 0000B Restart x00x xxxx xxxx xxxxB Reset Short Name Reset Mode Note Notes 1. The VCC1 undervoltage prewarning threshold VPW,f / VPW,r is a fixed threshold and independent of the VCC1 undervoltage reset thresholds. 2. VSINT undervoltage monitoring is not available in Stop Mode due to current consumption saving requirements. Exception: VSINT undervoltage detection is also available in Stop Mode if the VCC1 load current is above the active peak threshold (I_PEAK_TH) or if VCC1 is below the VCC1 prewarning threshold (VCC1_WARN is set). 3. The MSB of the POR/Soft Reset value is marked as ‘y’: the default value of the POR bit is set after Power-on reset (POR value = 1000 0000). However it will be cleared after a device Soft Reset command (Soft Reset value = 0000 0000). 4. During Sleep Mode, the bits VCC1_SC, VCC1_OV and VCC1_UV will not be set when VCC1 is off. 5. The VCC1_UV bit is never updated in Restart Mode, in Init Mode it is only updated after RSTN was released, it is always updated in Normal Mode and Stop Mode, and it is always updated in any device modes in a VCC1_SC condition (after VCC1_UV = 1 for > 2 ms). Datasheet 240 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Serial Peripheral Interface Thermal Protection Status THERM_STAT Thermal Protection Status 15 14 13 12 (100 0001B) 11 10 9 8 7 Reset Value: see Table 95 6 5 4 3 2 1 0 TSD2_ TSD2 TSD1 TPW SAFE RES r rc rc rc rc Field Bits Type Description RES 15:4 r Reserved, always reads as 0 TSD2_SAFE 3 rc TSD2 Thermal Shut-Down Safe State Detection 0B NO_TSD2_SF, No TSD2 safe state detected 1B TSD2_SF, TSD2 safe state detected: >16 consecutive TSD2 events occurred, next TSD2 waiting time will be 64s TSD2 2 rc TSD2 Thermal Shut-Down Detection 0B NO_TSD2, No TSD2 event 1B TSD2_EVENT, TSD2 OT detected - leading to FailSafe Mode TSD1 1 rc TSD1 Thermal Shut-Down Detection 0B NO_TSD1, No TSD1 fail 1B TSD1_EVENT, TSD1 OT detected (affected module is disabled) TPW 0 rc Thermal Pre Warning 0B NO_TPW, No Thermal Pre warning 1B TPW, Thermal Pre warning detected Table 95 Reset of THERM_STAT Register Reset Type Reset Values POR/Soft reset 0000 0000 0000 0000B Restart 0000 0000 0000 xxxxB Note: Datasheet Reset Short Name Reset Mode Note Temperature warning and shutdown bits are not reset automatically, even if the temperature pre warning or the TSD condition is not present anymore. 241 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Serial Peripheral Interface Device Information Status DEV_STAT Device Information Status 15 14 13 12 (100 0010B) 11 10 9 8 7 CRC_S CRC_F TAT AIL RES r r rc Reset Value: see Table 96 6 5 4 3 2 DEV_STAT RES SW_D EV WD_FAIL rc r rh rh 1 0 SPI_F FAILU AIL RE rc rc Field Bits Type Description RES 15:10 r Reserved, always read as 0 CRC_STAT 9 r CRC STAT Information 0B DISABLED, CRC disabled 1B ENABLED, CRC enabled CRC_FAIL 8 rc CRC Fail Information1) 0B NO_FAIL, No CRC Failure 1B FAIL, CRC Failure detected DEV_STAT 7:6 rc Device Status before Restart Mode 00B CLEARED, Cleared (Register must be actively cleared) 01B RESTART, Restart due to failure (WD fail, TSD2, VCC1_UV, trial to access Sleep Mode without any wake source activated); also after a wake from Fail-Safe Mode 10B SLEEP, Sleep Mode 11B , reserved RES 5 r Reserved, always reads 0 SW_DEV 4 rh Status of Operating Mode 0B NORMAL, Normal operation 1B SW_DEV, Software Development Mode is enabled WD_FAIL 3:2 rh Number of WD-Failure Events 00B NO_FAIL, No WD Fail 01B 1x, 1x WD Fail, 10B 2x, 2x WD Fail 11B 3x, more than 3xWD Fail SPI_FAIL 1 rc SPI Fail Information 0B NO_FAIL, No SPI fail 1B INVALID, Invalid SPI command detected FAILURE 0 rc Failure detection 0B NO_FAIL, No Failure 1B FAIL, Failure occured 1) The CRC_FAIL bit will not be set in case the static CRC enabling / disabling sequence is sent (see Chapter 5.2). Datasheet 242 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Serial Peripheral Interface Table 96 Reset of DEV_STAT Register Reset Type Reset Values POR/Soft reset 0000 0000 0000 0000B Restart 0000 00xx xx0x xxxxB Reset Short Name Reset Mode Note Notes 1. The bits DEV_STAT show the status of the device before exiting Restart Mode. Either the device came from regular Sleep Mode or a failure (Restart Mode or Fail-Safe Mode) occurred. Coming from Sleep Mode will also be shown if there was a trial to enter Sleep Mode without having cleared all wake flags before. 2. The WD_FAIL bits are implemented as a counter and are the only status bits, which are cleared automatically by the device. 3. The SPI_FAIL bit can only be cleared via SPI command. 4. The bit CRC_STAT and CRC_FAIL can be read regardless the CRC setting. The SPI read command on DEV_STAT ignores the CRC field. Datasheet 243 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Serial Peripheral Interface Bus Communication Status BUS_STAT Bus Communication Status 15 14 13 12 (100 0011B) 11 10 9 8 7 Reset Value: see Table 97 6 5 RES RES r r 4 3 CANT SYSER O R rc 2 1 0 CAN_FAIL VCAN_ UV rc rc rc Field Bits Type Description RES 15:7 r Reserved, always reads as 0 RES 6:5 r Reserved, always reads as 0 CANTO 4 rc CAN Time Out Detection 0B NO_FAIL, Normal operation 1B TIME_OUT, CAN Time Out detected SYSERR 3 rc SWK System Error 0B NO_FAIL, Selective Wake Mode is possible 1B FAIL, System Error detected, SWK enabling not possible CAN_FAIL 2:1 rc CAN failure status 00B NO_ERR, No error 01B CAN_TSD, CAN Thermal shutdown 10B CAN_TXD_DOM_TO, CAN_TXD_DOM: TXD dominant time out detected 11B CAN_BUS_DOM_TO, CAN_BUS_DOM: BUS dominant time out detected VCAN_UV 0 rc Under Voltage CAN Bus Supply 0B NORMAL, Normal operation 1B UNDERVOLTAGE, CAN Supply undervoltage detected. Transmitter disabled Table 97 Reset of BUS_STAT Register Reset Type Reset Values POR/Soft reset 0000 0000 0000 0000B Restart 0000 0000 0xxx xxxxB Reset Short Name Reset Mode Note Notes 1. The VCAN_UV comparator is enabled if CAN Normal or CAN Receive Only Mode. 2. CAN Recovery Conditions: 1.) TXD Time Out: TXD goes HIGH or transmitter is set to wake capable or switched off. 2.) Bus dominant time out: Bus will become recessive or transceiver is set to wake capable or switched off. 3.) Supply under voltage: as soon as the threshold is crossed again, i.e. VCAN > VCAN_UV for CAN. 4.) In all cases (also for TSD shutdown): to enable the Bus transmission again, TXD needs to be HIGH (recessive) for a certain time (transmitter enable time). Datasheet 244 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Serial Peripheral Interface 3. CANTO will be set only if CAN2 = 1 (=SWK Mode enabled). It will be set as soon as CANSIL was set and will stay set even in CANSIL it is reset. An interrupt is issued in Stop Mode and Normal Mode as soon as CANTO is set and the interrupt is not masked out, i.e. CANTO_MASK must be set to 1. 4. The SYSERR Flag is set in case of a configuration error and in case of an error counter overflow (n > 32) It is only updated if SWK is enabled (CAN_2 = ‘1’). See also chapter x. 5. CANTO is set asynchronously to the INTN pulse. In order to prevent undesired clearing of CANTO and thus possibly missing this interrupt, the bit will be prevented from clearing (i.e. cannot be cleared) until the next falling edge of INTN. Datasheet 245 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Serial Peripheral Interface Wake-up Source and Information Status WK_STAT Wake-up Source and Information Status 15 14 13 12 11 (100 0100B) 10 RES RES r r 9 8 7 Reset Value: see Table 98 6 CAN_ TIMER TIMER WU 2_WU 1_WU rc rc rc 5 RES r 4 WK5_ WK4_ WU WU rc Field Bits Type Description RES 15:11 r Reserved, always reads as 0 RES 10 r Reserved, always reads as 0 CAN_WU 9 rc Wake up via CAN Bus 0B NO_WU, No Wake up 1B WU, Wake up detected TIMER2_WU 8 rc Wake up via Timer2 0B NO_WU, No Wake up 1B WU, Wake up detected TIMER1_WU 7 rc Wake up via Timer1 0B NO_WU, No Wake up 1B WU, Wake up detected RES 6:5 r Reserved, always reads as 0 WK5_WU 4 rc Wake up via WK5 0B NO_WU, No Wake up 1B WU, Wake up detected WK4_WU 3 rc Wake up via WK4 0B NO_WU, No Wake up 1B WU, Wake up detected RES 2 r Reserved, always reads as 0 RES 1 r Reserved, always reads as 0 RES 0 r Reserved, always reads as 0 Table 98 POR/Soft reset 0000 0000 0000 0000B Restart 0000 0xxx x000 00x0B Datasheet rc 2 1 0 RES RES RES r r r Reset of WK_STAT Register Reset Type Reset Values Note: 3 Reset Short Name Reset Mode Note At Fail-Safe Mode entry, the WK_STAT register is automatically cleared by the device. 246 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Serial Peripheral Interface WK Input Level WK_LVL_STAT WK Input Level 15 14 (100 0101B) 13 12 11 10 9 8 7 Reset Value: see Table 99 6 5 4 WK5_ WK4_ LVL LVL RES r r Field Bits Type Description RES 15:5 r Reserved, always reads as 0 WK5_LVL 4 r Status of WK5 0B LOW, Low Level (=0) 1B HIGH, High Level (=1) WK4_LVL 3 r Status of WK4 0B LOW, Low Level (=0) 1B HIGH, High Level (=1) RES 2 r Reserved, always reads as 0 RES 1 r Reserved, always reads as 0 RES 0 r Reserved, always reads as 0 Table 99 POR/Soft reset 0000 0000 0000 00x0B Restart 0000 0000 0000 00x0B Datasheet r 2 1 0 RES RES RES r r r Reset of WK_LVL_STAT Register Reset Type Reset Values Note: 3 Reset Short Name Reset Mode Note WK_LVL_STAT is updated in Normal Mode and Stop Mode and also in Init and Restart Mode. In cyclic sense or wake mode, the registers contain the sampled level, i.e. the registers are updated after every sampling. 247 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Serial Peripheral Interface High-Side Switch Status HS_OL_OC_OT_STAT High-Side Switch Status 15 14 13 RES RES r r 12 (100 0110B) 11 10 HS3_ HS2_ HS1_ OT OT OT rc rc rc 9 8 RES RES r r 7 Reset Value: see Table 100 6 5 HS3_ HS2_ HS1_ OL OL OL rc rc rc 4 3 RES RES r r 2 rc Bits Type Description RES 15:14 r Reserved, always reads as 0 RES 13 r Reserved, always reads as 0 HS3_OT 12 rc Overtemperature Detection on HS3 0B NO_OT, No OT 1B OT, OT detected HS2_OT 11 rc Overtemperature Detection on HS2 0B NO_OT, No OT 1B OT, OT detected HS1_OT 10 rc Overtemperature Detection on HS1 0B NO_OT, No OT 1B OT, OT detected RES 9 r Reserved, always reads as 0 RES 8 r Reserved, always reads as 0 HS3_OL 7 rc Open-Load Detection on HS3 0B NO_OL, No OL 1B OL, OL detected HS2_OL 6 rc Open-Load Detection on HS2 0B NO_OL, No OL 1B OL, OL detected HS1_OL 5 rc Open-Load Detection on HS1 0B NO_OL, No OL 1B OL, OL detected RES 4 r Reserved, always reads as 0 RES 3 r Reserved, always reads as 0 HS3_OC 2 rc Overcurrent Detection on HS3 0B NO_OC, No OC 1B OC, OC detected HS2_OC 1 rc Overcurrent Detection on HS2 0B NO_OC, No OC 1B OC, OC detected HS1_OC 0 rc Overcurrent Detection on HS1 0B NO_OC, No OC 1B OC, OC detected 248 0 HS3_ HS2_ HS1_ OC OC OC Field Datasheet 1 rc rc Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Serial Peripheral Interface Table 100 Reset of HS_OL_OC_OT_STAT Register Reset Type Reset Values POR/Soft reset 0000 0000 0000 0000B Restart 00xx xxxx xxxx xxxxB Datasheet Reset Short Name Reset Mode 249 Note Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Serial Peripheral Interface 13.6.2 Status registers bridge driver General Status register GEN_STAT General Status register 15 14 13 12 (101 0000B) 11 10 9 RES RES r r 8 7 Reset Value: see Table 101 6 5 4 3 2 1 0 HB3V HB2V HB1V PWM6 PWM5 PWM4 PWM3 PWM2 PWM1 OUT OUT OUT STAT STAT STAT STAT STAT STAT r r r r r r r r r Field Bits Type Description RES 15:10 r Reserved, always reads as 0 RES 9 r Reserved, always reads as 0 HB3VOUT 8 r Voltage level at VSH3 when HB3MODE[1:0] = 11 and CPEN=11) 0B LOW, VSH3 = Low : VS - VSH3 > VHS3VDSTHx 1B HIGH, VSH3 = High: VS - VSH3 ≤ VHS3VDSTHx HB2VOUT 7 r Voltage level at VSH2 when HB2MODE[1:0] = 11 and CPEN=11) 0B LOW, VSH2 = Low : VS - VSH2 > VHS2VDSTHx 1B HIGH, VSH2 = High: VS - VSH2 ≤ VHS2VDSTHx HB1VOUT 6 r Voltage level at VSH1 when HB1MODE[1:0] = 11 and CPEN=11) 0B LOW, VSH1 = Low : VS - VSH1 > VHS1VDSTHx 1B HIGH, VSH1 = High: VS - VSH1 ≤ VHS1VDSTHx PWM6STAT 5 r PWM6 status 0B LOW, PWM6 is Low 1B HIGH, PWM6 is High PWM5STAT 4 r PWM5 status 0B LOW, PWM5 is Low 1B HIGH, PWM5 is High PWM4STAT 3 r PWM4 Status 0B LOW, PWM4 is Low 1B HIGH, PWM4 is High PWM3STAT 2 r PWM3 status 0B LOW, PWM3 is Low 1B HIGH, PWM3 is High PWM2STAT 1 r PWM2 Status 0B LOW, PWM2 is Low 1B HIGH, PWM2 is High PWM1STAT 0 r PWM1/CRC status 0B LOW, PWM1/CRC is Low 1B HIGH, PWM1/CRC is High 1) HBxVOUT = 0 if (CPEN=1 and HBxMODE ≠ 11) or CPEN=0. Datasheet 250 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Serial Peripheral Interface Table 101 Reset of GEN_STAT Register Reset Type Reset Values POR/Soft reset 0000 0000 0000 0000B Restart 0000 0000 xx00 000xB Datasheet Reset Short Name Reset Mode 251 Note Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Serial Peripheral Interface Turn-on/off delay regulation register TDREG Turn-on/off delay regulation register 15 14 13 12 11 RES RES r r 10 (101 0001B) 9 8 7 Reset Value: see Table 102 6 5 4 3 IPDCH IPDCH IPDCH IPCHG IPCHG IPCHG RES RES G3_ST G2_ST G1_ST 3_ST 2_ST 1_ST r r r r r r r r 2 1 0 TDRE TDRE TDRE G3 G2 G1 r r r Field Bits Type Description RES 15:12 r Reserved, always reads as 0 RES 11 r Reserved, always reads as 0 IPDCHG3_ST 10 r HB3 predischarge status 0B CLAMP, the predischarge current is equal to 0.5 mA typ. or ICHGMAX3 if AGC[1:0] = 10B or 11B, and HB3_PWM_EN = 11) 1B NO_CLAMP, 0.5 mA < predischarge current < ICHGMAX31) IPDCHG2_ST 9 r HB2 predischarge status 0B CLAMP, the predischarge current is equal to 0.5 mA typ. or ICHGMAX2 if AGC[1:0] = 10B or 11B, and HB2_PWM_EN = 11) 1B NO_CLAMP, 0.5 mA < predischarge current < ICHGMAX21) IPDCHG1_ST 8 r HB1 predischarge status 0B CLAMP, the predischarge current is equal to the 0.5 mA typ. or ICHGMAX1 if AGC[1:0] = 10B or 11B, and HBx_PWM_EN = 11) 1B NO_CLAMP, 0.5 mA < predischarge current < ICHGMAX11) RES 7 r Reserved, always reads as 0 IPCHG3_ST 6 r HB3 precharge status 0B CLAMP, the precharge current is equal to 0.5 mA typ. or ICHGMAX3 if AGC[1:0] = 10B or 11B, and HB3_PWM_EN = 11) 1B NO_CLAMP, 0.5 mA < precharge current < ICHGMAX31) IPCHG2_ST 5 r HB2 precharge status 0B CLAMP, the precharge current is equal to 0.5 mA typ. or ICHGMAX2 if AGC[1:0] = 10B or 11B, and HB2_PWM_EN = 11) 1B NO_CLAMP, 0.5 mA < precharge current < ICHGMAX21) Datasheet 252 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Serial Peripheral Interface Field Bits Type Description IPCHG1_ST 4 r HB1 precharge status 0B CLAMP, the precharge current is equal to the 0.5 mA typ. or ICHGMAX1 if AGC[1:0] = 10B or 11B, and HB1_PWM_EN = 11) 1B NO_CLAMP, 0.5 mA < precharge current < ICHGMAX11) RES 3 r Reserved, always reads as 0 TDREG3 2 r HB3 Regulation of turn-on/off delay 0B NO_REG, tDON3 and tDOFF3 are not in regulation 1B REG, tDON3 and/or tDOFF3 are in regulation TDREG2 1 r HB2 Regulation of turn-on/off delay 0B NO_REG, tDON2 and tDOFF2 are not in regulation 1B REG, tDON2 and/or tDOFF2 are in regulation TDREG1 0 r HB1 Regulation of turn-on/off delay 0B NO_REG, tDON and tDOFF are not in regulation 1B REG, tDON and/or tDOFF are in regulation 1) IPCHGx_ST = 1 otherwise (PWM disabled, HB in high impedance or AGC[1:0] = 00B or 01B ). Table 102 Reset of TDREG Register Reset Type Reset Values POR/Soft reset 0000 0000 0000 0000B Restart 0000 0000 xx00 000xB Datasheet Reset Short Name Reset Mode 253 Note Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Serial Peripheral Interface Drain-source overvoltage status DSOV Drain-source overvoltage 15 RES r 14 13 12 VSINT VSOV OC_C OVBR BRAK SA AKE_S E_ST T rc rc rc (101 0010B) 11 RES 10 9 8 7 LS3DS LS2DS LS1DS OV_B OV_B OV_B RES RK RK RK r rc rc rc r Reset Value: see Table 103 6 RES r 5 4 3 2 1 0 LS3DS HS3D LS2DS HS2D LS1DS HS1D OV SOV OV SOV OV SOV rc rc rc rc rc rc Field Bits Type Description RES 15 r Reserved, always reads as 0 OC_CSA 14 rc CSA Overcurrent detection 0B NO_OC, No overcurrent detected 1B OC, Overcurrent detected VSINTOVBRAKE_ST 13 rc VSINT Brake status 0B NOT_DETECT, VSINT overvoltage brake condition is not detected 1B DETECT, VSINT overvoltage brake conditions is detected VSOVBRAKE_ST 12 rc VS Brake status 0B NOT_DETECT, VS overvoltage brake conditions is not detected 1B DETECT, VS overvoltage brake conditions is detected RES 11 r Reserved, always reads as 0 LS3DSOV_BRK 10 rc Drain-source overvoltage on low-side 3 during braking 0B NO_OV, No drain-source overvoltage on LS3 1B OV, Drain-source overvoltage on LS3 LS2DSOV_BRK 9 rc Drain-source overvoltage on low-side 2 during braking 0B NO_OV, No drain-source overvoltage on LS2 1B OV, Drain-source overvoltage on LS2 LS1DSOV_BRK 8 rc Drain-source overvoltage on low-side 1 during braking 0B NO_OV, No drain-source overvoltage on LS1 1B OV, Drain-source overvoltage on LS1 RES 7 r Reserved, always reads as 0 RES 6 r Reserved, always reads as 0 LS3DSOV 5 rc Drain-source overvoltage on low-side 3 0B NO_OV, No drain-source overvoltage on LS3 1B OV, Drain-source overvoltage on LS3 Datasheet 254 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Serial Peripheral Interface Field Bits Type Description HS3DSOV 4 rc Drain-source overvoltage on high-side 3 0B NO_OV, No drain-source overvoltage on HS3 1B OV, Drain-source overvoltage on HS3 LS2DSOV 3 rc Drain-source overvoltage on low-side 2 0B NO_OV, No drain-source overvoltage on LS2 1B OV, Drain-source overvoltage on LS2 HS2DSOV 2 rc Drain-source overvoltage on high-side 2 0B NO_OV, No drain-source overvoltage on HS2 1B OV, Drain-source overvoltage on HS2 LS1DSOV 1 rc Drain-source overvoltage on low-side 1 0B NO_OV, No drain-source overvoltage on LS1 1B OV, Drain-source overvoltage on LS1 HS1DSOV 0 rc Drain-source overvoltage on high-side 1 0B NO_OV, No drain-source overvoltage on HS1 1B OV, Drain-source overvoltage on HS1 Table 103 Reset of DSOV Register Reset Type Reset Values POR/Soft reset 0000 0000 0000 0000B Restart 0xxx 0xxx 00xx xxxxB Datasheet Reset Short Name Reset Mode 255 Note Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Serial Peripheral Interface Effective MOSFET turn.on/off delay - PWM half-bridge 1 EFF_TDON_OFF1 Effective MOSFET turn.on/off delay - HB1 15 14 13 12 11 10 (101 0011B) 9 8 Reset Value: see Table 104 7 6 5 4 3 2 RES TDOFF1EFF RES TDON1EFF r r r r 1 0 Field Bits Type Description RES 15:14 r Reserved, always reads as 0 TDOFF1EFF 13:8 r Effective active MOSFET turn-off delay HB1 Nominal effective tDOFF1 = 53.3 ns x TDOFF1EFF[13:8]D RES 7:6 r Reserved, always reads as 0 TDON1EFF 5:0 r Effective active MOSFET turn-on delay HB1 Nominal effective tDON1 = 53.3 ns x TDON1EFF[5:0]D Table 104 Reset of EFF_TDON_OFF1 Register Reset Type Reset Values POR/Soft reset 0000 0000 0000 0000B Restart 00xx xxxx 00xx xxxxB Datasheet Reset Short Name Reset Mode 256 Note Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Serial Peripheral Interface Effective MOSFET turn.on/off delay - PWM half-bridge 2 EFF_TDON_OFF2 Effective MOSFET turn.on/off delay - HB 2 15 14 13 12 11 10 (101 0100B) 9 8 Reset Value: see Table 105 7 6 5 4 3 2 RES TDOFF2EFF RES TDON2EFF r r r r 1 0 Field Bits Type Description RES 15:14 r Reserved, always reads as 0 TDOFF2EFF 13:8 r Effective active MOSFET turn-off delay HB2 Nominal effective tDOFF2 = 53.3 ns x TDOFF2EFF[13:8]D RES 7:6 r Reserved, always reads as 0 TDON2EFF 5:0 r Effective active MOSFET turn-on delay HB2 Nominal effective tDON2 = 53.3 ns x TDON2EFF[5:0]D Table 105 Reset of EFF_TDON_OFF2 Register Reset Type Reset Values POR/Soft reset 0000 0000 0000 0000B Restart 00xx xxxx 00xx xxxxB Datasheet Reset Short Name Reset Mode 257 Note Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Serial Peripheral Interface Effective MOSFET turn.on/off delay - PWM half-bridge 3 EFF_TDON_OFF3 Effective MOSFET turn.on/off delay - HB3 15 14 13 12 11 10 (101 0101B) 9 8 Reset Value: see Table 106 7 6 5 4 3 2 RES TDOFF3EFF RES TDON3EFF r r r r 1 0 Field Bits Type Description RES 15:14 r Reserved, always reads as 0 TDOFF3EFF 13:8 r Effective active MOSFET turn-off delay HB3 Nominal effective tDOFF3 = 53.3 ns x TDO3EFF[13:8]D RES 7:6 r Reserved, always reads as 0 TDON3EFF 5:0 r Effective active MOSFET turn-on delay HB3 Nominal effective tDON3 = 53.3 ns x TDON3EFF[5:0]D Table 106 Reset of EFF_TDON_OFF3 Register Reset Type Reset Values POR/Soft reset 0000 0000 0000 0000B Restart 00xx xxxx 00xx xxxxB Datasheet Reset Short Name Reset Mode 258 Note Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Serial Peripheral Interface MOSFET rise/fall time - PWM half-bridge 1 TRISE_FALL1 MOSFET rise/fall time - HB1 15 14 13 12 (101 0111B) 11 10 9 8 Reset Value: see Table 107 7 6 5 4 3 2 RES TFALL1 RES TRISE1 r r r r Field Bits Type Description RES 15:14 r Reserved, always reads as 0 TFALL1 13:8 r Active MOSFET fall time HB1 Nominal tFALL1 = 53.3 ns x TFALL1[5:0]D RES 7:6 r Reserved, always reads as 0 TRISE1 5:0 r Active MOSFET rise time HB1 Nominal tRISE1 = 53.3 ns x TRISE1[5:0]D 1 0 Table 107 Reset of TRISE_FALL1 Register Reset Type Reset Values POR/Soft reset 0000 0000 0000 0000B Restart 00xx xxxx 00xx xxxxB Datasheet Reset Short Name Reset Mode 259 Note Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Serial Peripheral Interface MOSFET rise/fall time - PWM half-bridge 2 TRISE_FALL2 MOSFET rise/fall time - HB2 15 14 13 12 (101 1000B) 11 10 9 8 Reset Value: see Table 108 7 6 5 4 3 2 RES TFALL2 RES TRISE2 r r r r Field Bits Type Description RES 15:14 r Reserved, always reads as 0 TFALL2 13:8 r Active MOSFET fall time HB2 Nominal tFALL2 = 53.3 ns x TFALL2[5:0]D RES 7:6 r Reserved, always reads as 0 TRISE2 5:0 r Active MOSFET rise time HB2 Nominal tRISE2 = 53.3 ns x TRISE2[5:0]D 1 0 Table 108 Reset of TRISE_FALL2 Register Reset Type Reset Values POR/Soft reset 0000 0000 0000 0000B Restart 00xx xxxx 00xx xxxxB Datasheet Reset Short Name Reset Mode 260 Note Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Serial Peripheral Interface MOSFET rise/fall time - PWM half-bridge 3 TRISE_FALL3 MOSFET rise/fall time - HB3 15 14 13 12 (101 1001B) 11 10 9 8 Reset Value: see Table 109 7 6 5 4 3 2 RES TFALL3 RES TRISE3 r r r r Field Bits Type Description RES 15:14 r Reserved, always reads as 0 TFALL3 13:8 r Active MOSFET fall time HB3 Nominal tFALL3 = 53.3 ns x TFALL3[5:0]D RES 7:6 r Reserved, always reads as 0 TRISE3 5:0 r Active MOSFET rise time HB3 Nominal tRISE3 = 53.3 ns x TRISE3[5:0]D 1 0 Table 109 Reset of TRISE_FALL3 Register Reset Type Reset Values POR/Soft reset 0000 0000 0000 0000B Restart 00xx xxxx 00xx xxxxB Datasheet Reset Short Name Reset Mode 261 Note Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Serial Peripheral Interface 13.6.3 Selective wake status registers Selective Wake Status SWK_STAT Selective Wake Status 15 14 13 12 (110 0000B) 11 10 9 8 7 RES Reset Value: see Table 110 6 5 SYNC WUP r r rc 4 WUF 3 2 CANSI SWK_ L SET rc r r 1 0 RES r Field Bits Type Description RES 15:7 r Reserved, always reads as 0 SYNC 6 r Synchronisation (at least one CAN frame without fail must have been received) 0B NO_SYNC, SWK function not working or not synchronous to CAN bus 1B SYNC, Valid CAN frame received, SWK function is synchronous to CAN bus WUP 5 rc Wake-up Pattern Detection 0B NO_WUP, No WUP 1B WUP_DETECTED, WUP detected WUF 4 rc SWK Wake-up Frame Detection 0B NO_WUF, No WUF 1B WUF_DETECTED, WUF detected CANSIL 3 r CAN Silent Time during SWK operation 0B NO_SIL, tsilence not exceeded 1B SIL_EXCEEDED, set if tsilence is exceeded. SWK_SET 2 r Selective Wake Activity 0B INACTIVE, Selective Wake is not active 1B ACTIVE, Selective Wake is activated RES 1:0 r Reserved, always reads as 0 Table 110 Reset of SWK_STAT Register Reset Type Reset Values POR/Soft reset 0000 0000 0000 0000B Restart 0000 0000 0xxx xx00B Note: Datasheet Reset Short Name Reset Mode Note SWK_SET is set to flag that the selective wake functionality is activated (SYSERR = 0, CFG_VAL = 1, CAN_2 = 1). The selective wake function is activated via a CAN mode change, except if CAN = ‘100’. 262 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Serial Peripheral Interface Selective Wake ECNT Status SWK_ECNT_STAT Selective Wake ECNT Status 15 14 13 12 (110 0001B) 11 10 9 8 7 Reset Value: see Table 111 6 5 4 3 2 RES ECNT r r 1 0 Field Bits Type Description RES 15:6 r Reserved, always reads as 0 ECNT 5:0 r SWK CAN Frame Error Counter 00 0000BNO_ERR, No Frame Error 01 1111B31, 31 Frame Errors have been counted 10 0000BOVERFLOW, Error counter overflow - SWK function will be disabled Table 111 Reset of SWK_ECNT_STAT Register Reset Type Reset Values POR/Soft reset 0000 0000 0000 0000B Restart 0000 0000 00xx xxxxB Note: Datasheet Reset Short Name Reset Mode Note If a frame has been received that is valid according to ISO11898-2:2016 and the counter is not zero, then the counter shall be decremented. If the counter has reached a value of 32, the following actions shall be performed: Selective Wake function shall be disabled, SYSERR shall be set and CAN wake capable function shall be enabled, which leads to a wake with the next WUP. 263 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Serial Peripheral Interface Selective Wake CDR Status SWK_CDR_STAT Selective Wake CDR Status 15 14 13 12 (110 0011B) 11 10 9 8 7 Reset Value: see Table 112 6 5 4 3 2 1 N_AVG RES r r 0 Field Bits Type Description N_AVG 15:4 r Output Value from Filter Block N_AVG is representing the integer part of the number of selected input clock frequency per CAN bus bit. RES 3:0 r Reserved, always reads as 0 Table 112 Reset of SWK_CDR_STAT Register Reset Type Reset Values POR/Soft reset 1010 0000 0000 0000B Restart xxxx xxxx xxxx 0000B Datasheet Reset Short Name Reset Mode 264 Note Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Serial Peripheral Interface 13.6.4 Family and product information register Family and Product Identification Register FAM_PROD_STAT Family and Product Identification Register 15 14 13 12 11 10 (111 0000B) 9 8 7 Reset Value: see Table 113 6 5 4 3 RES FAM PROD r r r 2 1 0 Field Bits Type Description RES 15:11 r Reserved, always reads as 0 FAM 10:7 r Device Family Identifier 1000B, BLDC Motor System IC PROD 6:0 r Device Product Identifier 000 0000BTLE9562-3QX/QX, TLE9562-3QX/-3QXJ/QX 000 0001BTLE9561-3QX/QX, TLE9561-3QX/-3QXJ/QX 000 0010BTLE9563-3QX, TLE9563-3QX/-3QXJ 000 0011BTLE9564QX, TLE9564QX,TLE9185QX 001 0000BTLE9562-3QX V33, TLE9562-3QX V33 001 0010BTLE9563-3QX V33, TLE9563-3QX V33 001 0011BTLE9564QX V33, TLE9564QX V33,TLE9185QX V33 001 1000BTLE9560QX, TLE9560-3QX/-3QXJ Table 113 Reset of FAM_PROD_STAT Register Reset Type Reset Values POR/Soft reset 0000 0100 0000 0010B Restart 0000 0100 0000 0010B Datasheet Reset Short Name Reset Mode 265 Note Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Serial Peripheral Interface 13.7 Electrical Characteristics Table 114 Electrical Characteristics: Power Stage VSINT = 5.5 V to 28 V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note or Test Condition Number P_14.7.1 Min. Typ. Max. – – 6.0 MHz 1) SPI frequency Maximum SPI frequency fSPI,max VCC1 > 3 V SPI Interface; Logic Inputs SDI, CLK and CSN H-input Voltage Threshold VIH – – 0.7 × VCC1 V – P_14.7.2 L-input Voltage Threshold VIL 0.3 × VCC1 – – V – P_14.7.3 Hysteresis of input Voltage VIHY – 0.12 × VCC1 – V 1) P_14.7.4 Pull-up Resistance at pin CSN RICSN 20 40 80 kΩ – P_14.7.5 Pull-down Resistance at pin RICLK/SDI SDI and CLK 20 40 80 kΩ VSDI/CLK = 0.2 × VCC1 P_14.7.6 Input Capacitance at pin CSN, SDI or CLK CI – 10 – pF 1) VCSN, VSDI, VCLK = VCC1 P_14.7.7 H-output Voltage Level VSDOH 0.8 × VCC1 – – V IDOH = -2 mA P_14.7.8 L-output Voltage Level VSDOL – – 0.2 × VCC1 V IDOL = 2 mA P_14.7.9 ‘Tri-state Input Capacitance CSDO – 10 15 pF 1) VCSN, VSDI, VCLK = VCC1 P_14.7.11 Tri-state Leakage Current ISDOLK –10 – 10 µA 1) VCSN= VCC1, 0V < VSDO< VCC1 P_14.7.38 Clock Period tpCLK 160 – – ns – P_14.7.12 Clock HIGH Time tCLKH 70 – – ns – P_14.7.13 Clock LOW Time tCLKL 70 – – ns – P_14.7.14 Clock LOW before CSN LOW tbef 70 – – ns – P_14.7.15 CSN Setup Time tlead 160 – – ns – P_14.7.16 CLK Setup Time tlag 160 – – ns – P_14.7.17 Clock LOW after CSN HIGH tbeh 70 – – ns – P_14.7.18 SDI Setup Time tDISU 60 – – ns – P_14.7.19 SDI Hold Time tDIHO 40 – – ns – P_14.7.20 Logic Output SDO Data Input Timing1) Datasheet 266 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Serial Peripheral Interface Table 114 Electrical Characteristics: Power Stage (cont’d) VSINT = 5.5 V to 28 V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. Input Signal Rise Time at pin trIN SDI, CLK and CSN – – 20 ns – P_14.7.21 Input Signal Fall Time at pin tfIN SDI, CLK and CSN – – 20 ns – P_14.7.22 tDel,Mode – – 5 µs 3) P_14.7.23 tCSN(high) 3 – – µs – P_14.7.24 SDO Rise Time trSDO – 30 40 ns CL = 50 pF, 0.2 × VCC1 P_14.7.25 to 0.8 × VCC1 SDO Fall Time tfSDO – 30 40 ns CL = 50 pF, 0.8 × VCC1 P_14.7.26 to 0.2 × VCC1 SDO Enable Time tENSDO – – 40 ns LOW impedance P_14.7.27 SDO Disable Time tDISSDO – – 40 ns HIGH impedance P_14.7.28 SDO Valid Time tVASDO – – 40 ns CL = 50 pF P_14.7.29 Delay Time for Mode Changes2) CSN HIGH Time Data Output Timing 1) 1) Not subject to production test; specified by design. 2) Applies to all mode changes triggered via SPI commands. 3) Guaranteed by design. 24 CSN 15 16 13 17 14 18 CLK 19 SDI 27 SDO 20 LSB not defined MSB 28 29 Flag LSB MSB Figure 80 SPI Timing Diagram Note: Numbers in drawing correlate with the last 2 digits of the Number field in the Electrical Characteristics table. Datasheet 267 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Application Information 14 Application Information Note: The following information is given as a hint for the implementation of the device only and shall not be regarded as a description or warranty of a certain functionality, condition or quality of the device. 14.1 Application Diagrams VCC1 Drev1 Trev1 CVCC1 Cin3 Cin2 L1 VSINT SDI VS Cin4 Rrev1 Cin1 Drev2 VBAT Cin5 SDO CCP CLK CP Rrev2 CPC1N CCP1 CPC1P CSN Trev2 Rrev3 Drev3 RSTN CPC2N INTN CPC2P CCP2 RLED Cin2b HS1 CHS2 CHS1 CHS2 CHS1 CHS2 RLED HS2 GHx Q1 Bridge x3 CHS1 RLED HS3 CHB1x CHB2x SHx TLE9563 Microcontroller WK4/SYNC GLx Q2 WK5 to other bridges VBAT RFILT1 CSAP CFILT1 RWK4 SL CSAN CWK2 RSENSE PWM1 PWM2 RFILT2 RCSO CFILT3 CFILT2 PWM3 PWM4 CSO PWM5 ADC IN CCSO PWM6 VCAN CANH VCC1 CVCAN CANL TxD_CAN RxD_CAN RCAN RCAN GND CCAN Figure 81 TLE9563-3QX Application Diagram Note: This is a very simplified example of an application circuit. The function must be always verified in the real application. Datasheet 268 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Application Information Table 115 Bill of Material Ref. Typical Value Purpose / Comment Cin1 100 nF ±20% ceramic Input filter battery capacitor for optimum EMC behavior Cin2 100 µF ±20%, 50 V Electrolytic Buffering capacitor to cut off battery spikes, depending on the application Cin2b 470 µF ±20%, 50 V Electrolytic Buffering capacitor for bridges. Cut off battery spikes, depending on the application Cin3 100 nF ±20%, 50 V Ceramic Input capacitor Cin4 100 nF ±20%, 50 V Ceramic Input capacitor Cin5 470 µF ±20%, 50 V Electrolytic Buffering capacitor for bridges. Cut off battery spikes, depending on the application CCP 470 nF ±20%, 50 V Ceramic Charge-Pump buffering capacitor CCP1/ CCP2 220 nF ±20%, 50 V Ceramic Charge-Pump flying capacitor to be placed as closed as possible to the device pins, in order to minimize the length of the PCB tracks CFILT1 1.5 nF ±20%, 16 V Ceramic Current-sense filtering CFILT2 / CFILT3 22 nF ±20%, 16 V Ceramic Current-sense filtering CCSO 16 V Ceramic CSO buffering cap for a stable ADC voltage. Max 400 pF in case no resistor is used. With 50 Ω resistor up to 2.2 nF. (See CSA configuration register) CCAN 4.7 nF / OEM dependent Split termination stability CVCC1 2.2 uF ±20%, 16 V Blocking capacitor. Low ESR. Minimum 1 uF effective capacitance CVCAN 1 uF ... 4.7 uF Input filter CAN supply. The capacitor must be placed close to the VCAN pin. For optimum EMC and CAN FD performances, the capacitor has to be ≥ 2.2 µF CHB1x 10 nF ±20%, 50 V Ceramic Half-Bridge EME (electromagnetic emission) and ESD suppression filter to be placed close to the connector. Other capacitance values might be needed depending on application CHB2x 560 pF ±20%, 50 V Ceramic Optional filter for EMI immunity to be placed close to the SHx pin (PCB footprints highly recommended). Other capacitance values might be needed depending on application CHS1 47 pF / OEM dependent Only required om case of off-board connection to optimize EMC behavior, place close to pin CHS2 33 nF / OEM dependent As required by application, mandatory protection for off-board connection Capacitances Datasheet 269 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Application Information Table 115 Bill of Material (cont’d) Ref. Typical Value Purpose / Comment CWK1 / CWK2 47 nF / OEM dependent Spike filtering, as required by application, mandatory protection for off-board connections 4 uH ... 6 uH Input filter for power stage - consider high current rating (application dependent) RREV1 100 kΩ ±5% Other values needed depending on application RREV2 10 kΩ ±5% Device protection against reverse battery RREV3 10 kΩ ±5% RSENSE 5 mΩ ±1% Current-sense resistor RFILT1 / RFILT2 4.7 Ω ±5% Current-sense filtering RCSO 50 Ω ±5% Compensation for internal opamp.Depending on SPI configuration RCAN 60 Ω / OEM dependent CAN bus termination RLED 1k Limit LED-current RWK1 / RWK2 / RWK3 / RWK4 10 kΩ ±5% Inductances L1 Resistances Active Components DREV1 RR268MM600 Reverse polarity protection DREV2 BZX84C16 Gate protection. Limit VGS DREV3 BAS21 TREV1 IPZ40N04S5L-2R8 TREV2 BC846 Q1 / Q2 IPZ40N04S5-3R1 Datasheet Reverse battery protection, N-MOS Main power switches 270 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Application Information 14.2 ESD Tests 14.2.1 ESD according to IEC61000-4-2 Tests for ESD robustness according to IEC61000-4-2 “GUN test” (150 pF, 330 Ω) have been performed. The results and test condition are available in a test report. The values for the test are listed below. Table 116 ESD “GUN test”1)2) Performed Test Result Unit Remarks ESD at pin CANH, CANL, HSx, VS,VSINT,VS, WKx versus GND >6 kV positive pulse ESD at pin CANH, CANL, HSx, VS,VSINT,VS, WKx versus GND < -6 kV negative pulse 1) ESD susceptibility “ESD GUN” according to EMC 1.3 Test specification, Section 4.3 (IEC 61000-4-2). Tested by external test house (IBEE Zwickau, EMC Test report Nr. 20.12.20). 2) ESD Test “Gun Test” is specified with external components for pins VS, VSINT, VS, WKx, HSx. See the application diagram in Chapter 14.1 for more information. 14.2.2 ESD according to SAE J2962 Tests for ESD robustness according to SAE J2962 have been performed. Table 117 ESD according to SAE J2962 Performed Test Unit Remarks ESD at pin CANH, CANL, versus GND ± 4 kV Unpowered, contact discharge ESD at pin CANH, CANL versus GND ± 8 kV Powered, contact discharge ESD at pin CANH, CANL versus GND ± 15 kV Powered, air discharge Datasheet Result 271 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Application Information 14.3 Thermal Behavior of Package Top view Figure 82 Bottom view cooling area Detail solder pads and vias Board Setup Board setup is defined according JESD 51-2, -5, -7. Board: 76.2 × 114.3 × 1.5 mm3 with 2 inner copper layers (35 µm thick), with thermal via array under the exposed pad contacting the first inner copper layer and 300 mm2 cooling area on the bottom layer (70 µm). 14.4 Further Application Information • The VS pin supplies the bridge driver and the charge pump, and is the sense pin for the high-side MOSFETs drain voltage. It is therefore highly recommended to connect a 100 nF / 50V ceramic by-pass capacitor as close as possible to the VS pin with a short PCB trace to GND. • Please contact us for information regarding the FMEA pin • For further information you may contact http://www.infineon.com/ Datasheet 272 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Package Outlines Package Outlines 0.1±0.03 .0 ±0 1) 1 13 12 0.05 MAX. 5) (0.2) 1) Vertical burr 0.03 max., all sides 2) These four metal areas have exposed diepad potential Figure 83 (6) 48 13 .3 C 2) 37 (0 Index Marking 0.15 ±0.05 0.1 ±0.05 24 SEATING PLANE 7 ±0.1 6.8 48x 0.08 0.4 x 45° 36 25 0. +0.03 26 B 0.5 0. 6.8 11 x 0.5 = 5.5 0.5 ±0.07 A (5.2) 7 ±0.1 0.9 MAX. (0.65) 5 15 0.23 ±0.05 (5.2) Index Marking 48x 0.1 M A B C (6) PG-VQFN-48-29, -31-PO V05 PG-VQFN-481) Green Product (RoHS compliant) To meet the world-wide customer requirements for environmentally friendly products and to be compliant with government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020). Further information on packages https://www.infineon.com/packages 1) Dimensions in mm Datasheet 273 Rev. 1.0 2021-01-21 TLE9563-3QX BLDC Motor System IC Revision History 16 Revision History Revision Date Changes 1.0 First release Datasheet 2021-01-21 274 Rev. 1.0 2021-01-21 Trademarks All referenced product or service names and trademarks are the property of their respective owners. Edition 2021-01-21 Published by Infineon Technologies AG 81726 Munich, Germany © 2021 Infineon Technologies AG. All Rights Reserved. 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