TLF50281ELV50
2.2 MHz Step-Down Regulator 500 mA, 5 V, lo w qui escent current
1
Overview
Features
•
500 mA step down voltage regulator
•
5 V Output voltage
•
±2% output voltage tolerance
•
Low quiescent current (less than 45 µA at nominal battery voltage)
•
Integrated power transistor
•
Current mode PWM regulation
•
PFM mode for light load current
•
Input voltage range from 4.75 V to 45 V
•
2.2 MHz switching frequency
•
100% Duty cycle
•
Synchronization input
•
Very low shutdown current consumption (< 2 µA)
•
Soft-start function
•
Reset generator
•
Watchdog
•
Input undervoltage lockout
•
Suited for automotive applications: Tj = -40°C to 150°C
•
Green Product (RoHS compliant)
Potential applications
•
Applications with a 5.0 V switching regulator as replacement for linear voltage regulator with low
quiescent current, such as:
– dashboard
– engine management
– braking
– body
– infotainment
Data Sheet
www.infineon.com
1
Rev. 1.1
2018-03-07
TLF50281ELV50
2.2 MHz Step-Down Regulator 500 mA, 5 V, low quiescent current
Overview
Product validation
Qualified for automotive applications. Product Validation according to AEC-Q100/101.
Description
The TLF50281EL is a high frequency PWM step-down DC/DC converter with an integrated PMOS power switch,
packaged in a small PG-SSOP-14 with exposed pad. The wide input voltage range from 4.75 V to 45 V makes
the TLF50281EL suitable for a wide variety of applications. The device is designed to be used under harsh
automotive environmental conditions.
The switching frequency of nominal 2.2 MHz allows the use of small and cost-effective inductors and
capacitors, resulting in a low, predictable output voltage ripple and in minimized consumption of board
space.
In light load condition the device operates in Pulse Frequency Modulation (PFM) to optimize the efficiency.
Between the single pulses, all internal controlling circuitry is switched off to reduce the internal power
consumption.
The TLF50281EL includes protection features such as a cycle-by-cycle current limitation, overtemperature
shutdown and input undervoltage lockout. The enable function, in shutdown mode with less than 2 µA
current consumption, enables easy power management in battery-powered systems.
The voltage regulation loop provides an excellent line and load regulation, the stability of the loop is ensured
by an internal compensation network. This compensation network combined with a current mode regulation
control guarantees a highly effective line transient rejection. During start-up the integrated soft-start limits
the inrush current peak and prevents output voltage overshoot.
Type
Package
Marking
TLF50281EL
PG-SSOP-14
TLF50281
Data Sheet
2
Rev. 1.1
2018-03-07
TLF50281ELV50
2.2 MHz Step-Down Regulator 500 mA, 5 V, low quiescent current
Table of contents
1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Potential applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Product validation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3
3.1
3.2
Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4
4.1
4.2
4.3
General product characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5
5.1
5.1.1
5.1.2
5.1.3
5.2
5.3
Buck regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Regulator loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
PWM (Pulse Width Modulation) mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
PFM (Pulse Frequency Modulation) mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Electrical characteristics buck regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Performance graphs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6
6.1
6.2
6.3
6.4
Reset and watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Description reset function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical characteristics reset function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Description watchdog function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical characteristics watchdog function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7
7.1
7.2
Enable and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Electrical characteristics Enable, bias and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
8
8.1
8.2
Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Electrical characteristics buck regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
9
9.1
9.2
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
General layout recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Further application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
10
Package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
11
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Data Sheet
3
7
7
8
8
19
19
21
22
26
Rev. 1.1
2018-03-07
TLF50281ELV50
2.2 MHz Step-Down Regulator 500 mA, 5 V, low quiescent current
Block diagram
2
Block diagram
VS
13
TLF50281EL
Over
Temperature
Shutdown
EN
Enable
14
Buck
Converter
FREQ
5
SYNC
4
11
SWO
Oscillator
INT.
SUPPLY
Bandgap
Reference
7
FB
6
RTADJ
1
RO
Soft Start
Ramp
Generator
WI
3
Reset
Generator
Watchdog
WO
Figure 1
Data Sheet
2
8
9
10
12
WMSEL
GND
GND
N.C.
Block diagram
4
Rev. 1.1
2018-03-07
TLF50281ELV50
2.2 MHz Step-Down Regulator 500 mA, 5 V, low quiescent current
Pin configuration
3
Pin configuration
3.1
Pin assignment
RO
1
WO
TLF50281EL
14
EN
2
13
VS
WI
3
12
N.C.
SYNC
4
11
SWO
FREQ
5
10
GND
RTADJ
6
9
GND
FB
7
8
WMSEL
PG-SSOP14
Figure 2
Pin configuration
3.2
Pin definitions and functions
Pin Symbol Function
1
RO
Reset Output
Provides the reset output signal. Open collector output, connect a pull up resistor to VCC or
another voltage source, if feature is used, if not, leave open. Might be connected in parallel with
pin WO, if necessary.
2
WO
Watchdog Output
Provides the watchdog output signal. Open collector output, connect a pull up resistor to VCC
or another voltage source, if feature is used, if not, leave open. Might be connected in parallel
with pin RO, if necessary.
3
WI
Watchdog Input
Connect Watchdog Input signal, if feature is used. If not used, connect to GND.
4
SYNC
Synchronization input
Connect to an external clock signal in order to synchronize/adjust the switching frequency.
This feature is not functionally in PFM mode.
5
FREQ
Frequency adjustment pin
Connect an external resistor to GND to adjust the switching frequency, do not leave open. In
case the synchronization option is used, the resistor must be dimensioned close to the desired
synchronization frequency.
6
RTADJ
Reset Threshold Adjust pin
Connect an external resistor divider to adjust the Reset threshold. If function is not used,
connect to VCC.
Data Sheet
5
Rev. 1.1
2018-03-07
TLF50281ELV50
2.2 MHz Step-Down Regulator 500 mA, 5 V, low quiescent current
Pin configuration
Pin Symbol Function
7
FB
Feedback input
Connect this pin directly to the output capacitor. Also input for internal power supply. The
internal power supply is taken from the output voltage.
8
WMSEL Watchdog Mode Select pin
Connect to VCC for Watchdog slow mode or to GND for Watchdog fast mode. If not used, connect
to GND to avoid EMC related influence to Watchdog function.
9
GND
Ground
Connect this pin directly with low inductive and broad trace to ground, do not leave open.
10
GND
Ground
Connect this pin directly with low inductive and broad trace to ground, do not leave open.
11
SWO
Buck Switch Output
Drain of the integrated power-PMOS transistor. Connect directly to the cathode of the catch
diode and the buck circuit inductance.
12
N.C.
Not Connected
Internally not connected. Leave open or connect to GND.
13
VS
Supply Voltage input
Connect to supply voltage source.
14
EN
Enable input
Switch to high level to enable the device, switch to low level to disable the device.
Exposed pad Connect to heatsink area and GND by low inductance wiring.
Data Sheet
6
Rev. 1.1
2018-03-07
TLF50281ELV50
2.2 MHz Step-Down Regulator 500 mA, 5 V, low quiescent current
General product characteristics
4
General product characteristics
4.1
Absolute maximum ratings
Table 1
Absolute maximum ratings1)
Tj = -40°C to 150°C; all voltages with respect to ground (unless otherwise specified)
Parameter
Symbol
Values
Min. Typ. Max.
Unit Note or
Number
Test Condition
Voltages
Enable input
VEN
-40
–
45
V
–
P_4.1.1
Synchronization input
VSYNC
-0.3 –
5.5
V
–
P_4.1.2
6.2
V
t < 10 s 2)
P_4.1.3
5.5
V
–
P_4.1.4
Frequency adjustment pin
Watchdog input
Watchdog output
Watchdog mode selection pin
Reset threshold adjust pin
Reset output
Feedback Input
VFREQ
-0.3 –
VWI
-0.3 –
VWO
-0.3 –
VWMSEL
-0.3 –
VRTADJ
-0.3 –
VRO
-0.3 –
VFB
-0.3 –
6.2
V
t < 10 s
5.5
V
–
2)
P_4.1.5
P_4.1.6
6.2
V
t < 10 s
5.5
V
–
2)
P_4.1.7
P_4.1.8
2)
6.2
V
t < 10 s
5.5
V
–
P_4.1.10
6.2
V
t < 10 s 2)
P_4.1.11
5.5
V
–
P_4.1.12
6.2
V
t < 10 s
5.5
V
–
V
t < 10 s
5.5
V
–
V
P_4.1.13
P_4.1.14
6.2
6.2
2)
P_4.1.9
2)
P_4.1.15
P_4.1.16
t < 10 s
2)
P_4.1.17
Buck switch output
VSWO
-2.0 –
VVS + 0.3 V
–
P_4.1.18
Supply voltage input
VVS
-0.3 –
45
V
–
P_4.1.19
Junction temperature
Tj
-40
–
150
°C
–
P_4.1.20
Storage temperature
Tstg
-55
–
150
°C
–
P_4.1.21
VESD
-2
–
2
kV
HBM
Temperatures
ESD susceptibility
ESD resistivity
ESD resistivity to GND
ESD resistivity corner pins to GND
VESD
-500 –
VESD
-750 –
500
750
V
V
P_4.1.22
CDM
3)
P_4.1.23
CDM
3)
P_4.1.24
1) Not subject to production test, specified by design
2) ESD susceptibility HBM according to ANSI/ESDA/JEDEC JS-001.
3) ESD susceptibility, Charged Device Model “CDM” EIA/JESD22-C101 or ESDA STM5.3.1
Data Sheet
7
Rev. 1.1
2018-03-07
TLF50281ELV50
2.2 MHz Step-Down Regulator 500 mA, 5 V, low quiescent current
General product characteristics
Notes
1. Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
2. Integrated protection functions are designed to prevent IC destruction under fault conditions described in
the data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions
are not designed for continuous repetitive operation.
4.2
Functional range
Table 2
Functional range
Parameter
Symbol
Values
Number
Min.
Unit Note or
Test Condition
Typ. Max.
Supply voltage
VS
4.75
–
45
V
–
P_4.2.1
Buck inductor
LBU
3.3
–
22
µH
–
P_4.2.2
Buck capacitor
CBU1
10
–
50
µF
–
Buck capacitor ESR
ESRBU1
0.015 –
0.100 Ω
–
Junction temperature
Tj
-40
150
–
–
°C
P_4.2.3
1)
P_4.2.4
P_4.2.5
1) See section “Application information” on Page 30” for loop compensation requirements and refer to Application
Note for dimensioning the output filter.
Note:
Within the functional range the IC operates as described in the circuit description. The electrical
characteristics are specified within the conditions given in the related electrical characteristics
table.
4.3
Thermal resistance
Table 3
Thermal resistance
Parameter
Junction to case1)
Junction to ambient
2)
Symbol
Values
Unit Note or
Number
Test Condition
Min. Typ. Max.
RthJC
–
10
–
K/W –
P_4.3.1
RthJA
–
47
–
K/W 2s2p
P_4.3.2
RthJA
–
54
–
K/W 1s0p + 600 mm2 P_4.3.3
RthJA
–
64
–
K/W 1s0p + 300 mm2 P_4.3.4
1) Not subject to production test, specified by design.
2) Specified RthJA value is according to JEDEC 2s2p (JESD 51-7) + (JESD 51-5) and JEDEC 1s0p (JESD 51-3) + heatsink area
at natural convection on FR4 board.
Data Sheet
8
Rev. 1.1
2018-03-07
TLF50281ELV50
2.2 MHz Step-Down Regulator 500 mA, 5 V, low quiescent current
Buck regulator
5
Buck regulator
5.1
Description
The TLF50281EL is a monolithic current mode step down converter with adjustable switching frequency fOSC.
It is capable to operate either in Pulse Width Modulation (PWM) or in Pulse Frequency Modulation (PFM) Mode.
5.1.1
Regulator loop
Power stage
The supply voltage is connected to pin VS. Between pin VS and pin SWO there is an internal shunt resistor and
the internal PMOS power stage. The PMOS is driven by the driver stage.
Regulator block
The feedback signal VFB is connected to pin FB. Between pin FB and pin GND is an internal resistor divider. An
error amplifier and a comparator are connected to this resistor divider: The error amplifier EA-gmV, which is
controlling the output voltage in PWM mode, and the PFM comparator, which will switch the TLF50281EL into
PFM mode and trigger the pulses. The error amplifier EA-gmV is connected to the PWM comparator. The
regulation loop operates in current mode: The output current of EA-gmV is subtracted from the sum of the
current loop CS-gmI and the slope compensation ISLOPE. The result is evaluated by PWM Comp (a current
comparator). The output of PWM Comp defines duty cycle (pulse-width-modulated signal) in PWM mode.
The Slope Compensation added to the signal from the error amplifier EA-gmV to the PWM Comparator ensures
that no sub harmonics will occur on the input current.
The PWM comparator output and the PFM comparator output are connected to the PWM /PFM logic.
An external resistor at pin FREQ is required to set the switching frequency (for details please refer to chapter
8 Module Oscillator). The TLF50281EL may also be synchronized to an external frequency. In this case an
external clock signal should be connected to pin SYNC. The frequency setting resistor at pin FREQ is still
necessary, it has to be selected according to the desired synchronization frequency (for details please refer to
Chapter 8 Oscillator.
The TLF50281EL can only be synchronized to an external frequency source in PWM mode, this function does
not work in PFM mode.
The clock manager is clocking the PWM/PFM logic. The PWM/PFM logic is triggering the driver to apply pulses
to the internal PMOS power stage.
Safety features
The shunt resistor in line with the internal PMOS power stage (between pin VS and the power stage) is
connected to a current sense amplifier CS-gml. It detects the voltage above the shunt resistor. The amplifier
creates a signal which shuts the pulse down in case that the shunt voltage exceeds the reference limit. The
current limitation acts as a cycle-by-cycle limitation. Cycle-by-cycle limitation means, that every pulse is
switched off as soon as the current through the PMOS exceeds the buck peak over current limit IBUOC. The next
pulse starts and will also be switched off as soon as the current limit is exceeded again. This results in a
lowered output voltage whilst the output current is limited to a certain value.
Input undervoltage shutdown: If the input voltage is below the input undervoltage shutdown threshold VS,off
the device will shut down.
Output overvoltage protection: If the output voltage exceeds the PFM threshold the device will switch from
PWM to PFM. Pulses will then be generated only depending on the value of the output voltage VCC.
Data Sheet
9
Rev. 1.1
2018-03-07
TLF50281ELV50
2.2 MHz Step-Down Regulator 500 mA, 5 V, low quiescent current
Buck regulator
Soft start function: An integrated soft start function of duration tstart ensures, that the inrush current will be
limited. After an overtemperature shutdown the regulator always restarts with a soft start.
Overtemperature shutdown: An internal temperature sensor detects the temperature of the device. It will be
switched off if the junction temperature exceeds the overtemperature shutdown threshold Tj,sd and restart
with a certain hysteresis Tj,sd_hyst (for details please refer to Chapter 7 Enable and thermal shutdown).
Biasing
The internal biasing is taken from pin VS as well as from pin FB (connected to VCC) (for details please refer to
Chapter 7 Enable and thermal shutdown). Thus the power consumption from the supply voltage VS can be
minimized.
VS
+
VBG
CS-gmI
PFM
Comparator
+
FB
-
GateD
+
-
PWM Comp
EA-gmV
PWM
PFM
Logic
Driver
SWO
SYNC_IN
FREQ
Clock
Manager
CK_A
SoftStart
Slope
Comp.
CLK
GND
Figure 3
Block diagram buck regulator
5.1.2
PWM (Pulse Width Modulation) mode
Under normal conditions the TLF50281EL will operate with a constant switching frequency fOSC in PWM mode.
The ratio between switch-on-time TON and switch-off-time TOFF is mainly determined by the ratio between the
input voltage VS and the output voltage VCC and is influenced by the output current ICC.
In PWM mode the device may operate with 100% duty cycle, in this case the internal PMOS is constantly
conducting current. The current limitation feature is operating under this condition.
If the switch-on-time TON should theoretically be below the minimum threshold TON,min (due to low load or due
to the ratio between input voltage VS and output voltage VCC depending on the switching frequency), it will be
reduced to the minimum value switch-on-time TON,min and stay there. As a consequence the output voltage VCC
will increase. The PFM comparator detects the PFM threshold and will then switch the device into PFM mode.
There is no possibility to disable the PFM function.
Data Sheet
10
Rev. 1.1
2018-03-07
TLF50281ELV50
2.2 MHz Step-Down Regulator 500 mA, 5 V, low quiescent current
Buck regulator
5.1.3
PFM (Pulse Frequency Modulation) mode
To optimize the efficiency and to reduce the current consumption, the TLF50281EL automatically switches to
PFM mode under low load conditions. In PFM mode the internal power stage including the driver stage is
switched off and will only be switched on for applying pulses to charge the output capacitor. The pulses will
be created by monitoring the voltage of the output filter capacitor COUT. Thus in PFM mode the repetition time
of pulses depend on the output current and/or the ratio between input voltage VS and output voltage VCC.
Transition from PWM to PFM
Figure 4 shows the transition from Pulse Width Modulation to Pulse Frequency Modulation under the
assumption, that the input voltage VS will be constant and only the output current ICC will vary. The diagram
shows the principle, in reality the signals might look slightly different. The diagram is without scale in respect
of time, voltage and current values.
Starting from left of the figure a certain output current, here named i1, is applied to the regulator output. This
results in a duty cycle D1 with the on-time TON1 of the internal power stage. The switching frequency fOSC is
constant as set by the frequency setting resistor RFREQ. The regulator is in PWM mode, the output voltage is
VREF_PWM which is equal to VFB in PWM mode.
At point t1 the output current decreases from i1 to a lower i2. This results in a duty cycle D2 with the on-time
TON2 of the internal power stage. Due to the reduced output load the on-time TON2 is shorter (the regulator is
in Discontinuous Conduction Mode DCM) than TON1. The switching frequency fOSC is constant as set by the
frequency setting resistor RFREQ. The regulator is still in PWM mode, the output voltage is VREF_PWM which is
equal to VFB in PWM mode. In Continuous Conduction Mode CCM the variation from TON1 to TON2 will be very
small due to smaller conduction losses.
At point t2 the output current decreases again from i2 to a lower i3. As a consequence the on-time TON will be
reduced also. The output current i3 is so low, that the on-time TON3 would be smaller than the TON,min. The
regulator does not allow a on-time smaller than TON,min. Therefore we can say that the output current i3 is
under the imaginary current threshold for transition from PWM to PFM iPWM/PFM. With the pulse staying at ontime TON,min the output voltage VCC will rise. The regulator is still in PWM mode, but the output voltage rises.
At point t3 after a normal time period TPWM as adjusted by the frequency setting resistor RFREQ, a further pulse
of the duration TON,min is applied, the output voltage VCC keeps on rising. The regulator is still in PWM mode.
At point t4 the output voltage VCC touches (or exceeds) the voltage threshold for transition from PWM to PFM
VPWM/PFM. The regulator is now switching internally from PWM to PFM. In PFM mode the power consumption of
the internal blocks is reduced. The reference for the output voltage VCC is switched from VREF_PWM (which is
equal to VFB in PWM mode) to VREF_PFM (which is equal to VFB in PFM mode). The reference for VFB in PFM mode
is higher than the reference in PWM mode to avoid voltage dumps at the output voltage VCC due to sudden load
steps and to give the regulator more reaction time to switch back to PWM mode.
The regulator is now in PFM mode, the output voltage is VREF_PFM which is equal to VFB (or slightly higher) in PFM
mode.
The output voltage VCC is monitored and as soon as it touches the PFM reference voltage VREF_PFM a pulse of the
on-time TON,min is triggered. The time between two pulses is depending on the discharging of the output
capacitor COUT.
Data Sheet
11
Rev. 1.1
2018-03-07
TLF50281ELV50
2.2 MHz Step-Down Regulator 500 mA, 5 V, low quiescent current
Output current
Buck regulator
i1
i2
iPWM/PFM
i3
Switching signal
time
D1
D2
D3
TON2
TON1
TON,min
time
TPWM
Output voltage
TPWM
TPWM
Switch to PFM mode
VPWM/PFM
VREF_PFM
VREF_PWM
time
t1
Figure 4
t2
t3
t4
PWM to PFM transition (timing diagram)
Transition from PFM to PWM
Figure 5 shows the transition from Pulse Frequency Modulation to Pulse Width Modulation under the
assumption, that the input voltage VS will be constant, and only the output current ICC will vary. The diagram
shows the principle, in reality the signals might look slightly different. The diagram is without scale in respect
of time, voltage and current values.
Starting from left of the figure a certain output current, here named i3, is applied to the regulator output. i3
shall be below the imaginary current threshold for transition from PFM to PWM iPFM/PWM. The regulator is in
PFM mode, the output voltage is VREF_PFM, which is equal to VFB in PFM mode (or slightly higher).
Pulses of the duration TON,min are triggered whenever the output voltage VCC touches the PFM reference voltage
VREF_PFM.
At point t5 the output current increases from i3 to a higher i2, that shall be above the imaginary current
threshold for transition from PFM to PWM iPFM/PWM. Due to the higher output current more pulses of the
duration TON,min have to be triggered, the frequency of these pulses is monitored. The frequency of these
pulses increases until it is higher than the switching frequency fOSC set by the frequency setting resistor RFREQ.
The regulator is still in PFM mode.
At point t6 the frequency monitoring detects that the frequency of the PFM pulses is being higher than the
frequency threshold for transition from PFM to PWM fPFM/PWM. Therefore the regulator switches back to PWM
mode. This results in a certain duty cycle D2 with the on-time TON2 of the internal power stage. The time period
TPWM is as adjusted by the frequency setting resistor RFREQ.
Data Sheet
12
Rev. 1.1
2018-03-07
TLF50281ELV50
2.2 MHz Step-Down Regulator 500 mA, 5 V, low quiescent current
Output current
Buck regulator
i2
iPFM/PWM
i3
Switching signal
time
D2
TON,min
TON,min
TPWM
TON2
Output voltage
time
Switch to PWM mode
VPWM/PFM
VREF_PFM
VREF_PWM
time
t5
Figure 5
t6
PFM to PWM transition (timing diagram)
Frequency variation during PWM/PFM transition
Figure 6 shows the transition from Pulse Frequency Modulation to Pulse Width Modulation (and vice versa) in
relation to output current and switching frequency. The diagram shows the principle, in reality the signals
might be slightly different. The diagram is without scale in respect of frequency and current values.
The transition from PWM to PFM is shown in a grey line. Starting from right the switching frequency fPWM is
constant as set by the frequency setting resistor RFREQ. The output current ICC is decreasing.
As soon as the output current ICC is below the imaginary current threshold for transition from PWM to PFM
iPWM/PFM, the regulator will be switched from PWM to PFM mode depending on the output voltage VCC. With the
output current ICC decreasing, the switching frequency will also decrease, as the pulses are triggered by
monitoring the output voltage VCCat capacitor COUT.
The transition from PFM to PWM is shown in a black line. Starting from left the switching frequency is
increasing with the increasing output current ICC.
As soon as the switching frequency is crossing the frequency threshold for transition from PFM to PWM fPFM/PWM
(which is above the switching frequency fOSC set by the frequency setting resistor RFREQ) the regulator will
switch from PFM to PWM.
Data Sheet
13
Rev. 1.1
2018-03-07
TLF50281ELV50
2.2 MHz Step-Down Regulator 500 mA, 5 V, low quiescent current
Switching Frequency (log.scale)
Buck regulator
PWM to PFM
PFM to PWM
fPFM/PWM
fPWM
iPWM/PFM
Figure 6
Data Sheet
iPFM/PWM
Output Current
(log.scale)
PWM PFM transitions
14
Rev. 1.1
2018-03-07
TLF50281ELV50
2.2 MHz Step-Down Regulator 500 mA, 5 V, low quiescent current
Buck regulator
5.2
Electrical characteristics buck regulator
Table 4
Electrical characteristics: buck regulator
VS = 6.0 V to 40 V, Tj = -40°C to 150°C, all voltages with respect to ground (unless otherwise specified)
Parameter
Symbol
Values
Unit
Min. Typ. Max.
Output voltage
VFB
4.90 5.00 5.10 V
Note or
Test Condition
Number
VEN = 5.0 V
7 V < VS < 12 V
100 mA < ICC < 610 mA
P_5.2.1
VEN = 5.0 V
10 V < VS < 35 V
ICC = 100 µA
P_5.2.2
PWM Mode
Output voltage
VFB
4.90 5.10 5.30 V
PFM Mode
Power stage on-resistance
Ron
–
Buck peak over current limit
IBUOC
0.85 –
1.5
2.3
Ω
Tested at 100 mA,
VS = 7.0 V
P_5.2.8
1.7
A
–
P_5.2.9
P_5.2.10
Current transition rise/fall time
tR
–
100
–
mA/ns
1)
Maximum duty cycle
Dmax
–
–
100
%
2)
P_5.2.11
ns
1)
P_5.2.12
–
ns
1)
Minimum switch on-time
TON,min
–
100
–
Minimum switch off- Time
TOFF,min
–
Soft start ramp
tstart
300 450
750
µs
VFB rising from 5% to
95% of VFB,nom
P_5.2.14
Input undervoltage shutdown
threshold
VS,off
3.75 –
–
V
VS decreasing
P_5.2.15
Input voltage startup threshold
VS,on
–
4.75 V
VS increasing
P_5.2.16
Input undervoltage shutdown
hysteresis
VS,hyst
130 300
–
mV
–
P_5.2.17
5.3
V
1)
P_5.2.18
–
1)
P_5.2.19
Voltage threshold for transition from VPWM/PFM –
PWM to PFM
Frequency ratio for transition from
PFM to PWM
fPFM/PWM/ –
fosc
200
–
–
1.20 –
PFM mode
P_5.2.13
1) Specified by design. Not subject to production test.
2) Consider Chapter 4.2 Functional range.
Data Sheet
15
Rev. 1.1
2018-03-07
TLF50281ELV50
2.2 MHz Step-Down Regulator 500 mA, 5 V, low quiescent current
Buck regulator
5.3
Performance graphs
Typical performance characteristics
Line regulation PWM mode
VS = 12 V; TJ = +25°C
5,100
5,075
5,075
5,050
5,050
5,025
5,025
650
550
450
4,900
350
4,900
650
4,925
550
4,925
450
4,950
350
4,950
250
4,975
150
4,975
250
5,000
150
5,000
50
VFB (V)
5,100
50
VFB (V)
Load regulation PWM mode
VS = 12 V; TJ = -43°C
Icc (mA)
Icc (mA)
Load regulation PWM mode
VS = 12 V; TJ = +150°C
–
5,100
5,075
5,050
VFB (V)
5,025
5,000
4,975
4,950
650
550
450
350
250
150
4,900
50
4,925
Icc (mA)
Data Sheet
16
Rev. 1.1
2018-03-07
TLF50281ELV50
2.2 MHz Step-Down Regulator 500 mA, 5 V, low quiescent current
Buck regulator
Line regulation PFM mode
ICC = 100 µA; TJ = +25°C
5,128
5,112
5,112
5,096
5,096
5,08
5,08
45
40
35
30
Power stage on resistance: black TJ = +25°C
light grey TJ = -43°C, dark grey TJ = +150°C
Line regulation PFM mode
ICC = 100 µA; TJ = +150°C
1,400
5,128
5,112
1,200
5,096
1,000
5,08
VS - Vswo (V)
5,064
5,048
0,800
0,600
VS (V)
0,7
0,6
0,5
0,4
0,3
0,2
45
40
35
30
25
20
0,000
15
5
10
0,200
5
5,016
0,1
0,400
5,032
0
VFB (V)
25
VS (V)
VS (V)
Data Sheet
20
45
5
40
5
35
5,016
30
5,016
25
5,032
20
5,032
15
5,048
10
5,048
15
5,064
10
5,064
5
VFB (V)
5,128
5
VFB (V)
Line regulation PFM mode
ICC = 100 µA; TJ = -43°C
Iswo(A)
17
Rev. 1.1
2018-03-07
TLF50281ELV50
2.2 MHz Step-Down Regulator 500 mA, 5 V, low quiescent current
Buck regulator
Efficiency for
VS = 13 V, fOSC = 1.65 MHz, LOUT = 4.7 µH
Efficiency for
VS = 13 V, fOSC = 1.65 MHz, LOUT = 10 µH
90,00%
90,00%
80,00%
80,00%
70,00%
70,00%
60,00%
60,00%
50,00%
50,00%
40,00%
40,00%
30,00%
30,00%
20,00%
20,00%
10,00%
0,00%
10,00%
0
100
200
300
400
ICC (mA)
500
0
600
Efficiency for
VS = 13 V, fOSC = 2.2 MHz, LOUT = 4.7 µH
100
200
300
400
ICC (mA)
500
600
Efficiency for
VS = 13 V, fOSC = 2.2 MHz, LOUT = 10 µH
90,00%
90,00%
80,00%
80,00%
70,00%
70,00%
60,00%
60,00%
50,00%
50,00%
40,00%
40,00%
30,00%
30,00%
20,00%
20,00%
10,00%
0,00%
10,00%
0
Data Sheet
100
200
300
400
ICC (mA)
500
0
600
18
100
200
300
ICC (mA)
400
500
600
Rev. 1.1
2018-03-07
TLF50281ELV50
2.2 MHz Step-Down Regulator 500 mA, 5 V, low quiescent current
Reset and watchdog
6
Reset and watchdog
6.1
Description reset function
Principle:
The reset function supervises the value of the regulator output voltage VCC. The result is monitored by the
status of pin RO. A high level at pin RO means that the output voltage VCC is above the desired reset threshold.
A low level at pin RO means that the output voltage VCC is below the desired reset threshold. The reset function
does not work, if the supply (VFB) voltage is below 1 V.
Adjustment of reset threshold:
The reset generator consists of an internal comparator with a reset threshold VRO,T. By adding an external
resistor divider between the output voltage VCC and ground (GND) and connecting the point between the
upper (R1) and lower (R2) resistor to pin RTADJ the desired reset threshold VRT (where the reset generator
indicates an undervoltage) might be adjusted.
If reset function is not used please connect pin RTADJ to VCC.
(6.1)
R1 + R2
Desired reset threshold = V RO, T ⎛ ---------------------⎞ = V RT
⎝ R2 ⎠
Operation mode (please refer to Figure 7):
The reset generator starts operating as soon as the regulator is activated by supplying the device with an input
(battery) voltage higher than the input voltage startup threshold VS,ON and a valid high signal VEN,hi at pin EN.
The pin RO is low at this time.
When the regulator starts to operate, VCC ramps up and passes the desired reset threshold. The reset delay
time tRD is the time duration between that point and pin RO turning to high level.
The reset reaction time tRR is the maximum duration or time, the output voltage VCC may dip below the desired
reset threshold, before a reset is indicated and pin RO is pulled to low level. This is implemented to avoid
wrong reset triggering by short glitches on the output voltage VCC. If the output voltage VCC dips below the
desired reset threshold VRT for more than tRR; tRR is also the time until pin RO is pulled below VRO,L.
A voltage dip at the output voltage VCC leads to a low level at pin RO under the following condition:
(6.2)
R1 + R2
V CC < V RO, T ⎛ ---------------------⎞ ( for t > t RR )
⎝ R2 ⎠
In case the pin RO is pulled to low level, it stays low for the time until the output voltage VCC is higher than the
desired reset threshold VRT plus the reset delay time tRD.
Data Sheet
19
Rev. 1.1
2018-03-07
TLF50281ELV50
2.2 MHz Step-Down Regulator 500 mA, 5 V, low quiescent current
Reset and watchdog
Reset output pin (please refer to Figure 7):
The reset output is an open collector structure. As soon as a reset condition occurs, the pin is pulled to ground.
A pull up resistor (R4) connected to VCC or another voltage source is necessary. If the supply (VFB) voltage is
below 1 V the open collector structure does no longer pull pin RO to ground. In this case pin RO goes up to the
pull-up voltage (if not supplied by voltage VCC).
The reset output pin RO might be connected in parallel to the watchdog output pin WO, if the application
requires that.
V
< tRR
(related to RTADJ)
VRT
tRR
tRR
VRO
tRD
t
tRD
VROH
VROL
t
Figure 7
Reset function and timing diagram
•
ROH:= Reset Output High Level, depending on voltage sourcing the pull-up resistor at pin RO.
•
ROL:= Reset Output Low Level, Reset signal valid.
The recommended maximum value for the sum of both resistors R1 and R2 of the external resistor divider is
1.2 MΩ.
Data Sheet
20
Rev. 1.1
2018-03-07
TLF50281ELV50
2.2 MHz Step-Down Regulator 500 mA, 5 V, low quiescent current
Reset and watchdog
6.2
Electrical characteristics reset function
Table 5
Electrical characteristics: reset
VS = 6.0 V to 40 V, Tj = -40°C to 150°C, all voltages with respect to ground (unless otherwise specified)
Parameter
Symbol
Values
Unit Note or Test Condition
Number
Min. Typ. Max.
Reset Output RO
Output voltage low
VRO,L
–
0.2
0.4
V
VCC ≥ 1 V; VRTADJ < 0.9 V,
IRO = 1 mA
P_6.2.1
Sink current limit
IR,S,MAX
1
–
–
mA
VCC = 5 V; VRTADJ < 0.9 V,
VRO = 0.4 V
P_6.2.2
Leakage current
IRO,L,MAX
–
–
1
µA
VRO = 5 V
P_6.2.3
Output undervoltage threshold
decreasing
VRO,T
0.96 1.00 1.04 V
–
P_6.2.4
Output undervoltage hysteresis
VRO,T,Hyst 50
–
150
mV
Output voltage
decreasing
P_6.2.5
Pin RTADJ input current
IRTADJ,MAX -1
0.1
1
µA
VRTADJ = 1.2 V
P_6.2.6
Delay time
tRD
6
8
10
ms
–
P_6.2.7
Reset reaction time
tRR
2
–
10
µs
Output voltage
decreasing
P_6.2.8
Data Sheet
21
Rev. 1.1
2018-03-07
TLF50281ELV50
2.2 MHz Step-Down Regulator 500 mA, 5 V, low quiescent current
Reset and watchdog
6.3
Description watchdog function
Principle:
The watchdog supervises the operation of the microprocessor. The result is monitored by the status of pin WO.
A high level at pin WO means, that so far no microprocessor failure did occur. A low level at pin WO means, that
a microprocessor failure did occur. The watchdog signal is only valid for input (battery) voltage higher than
VS,off. The pin WO is also pulled to low, if the reset signal is pulled to low.
Watchdog mode select WMSEL:
The watchdog offers two operation modes: Slow watchdog timing and fast watchdog timing. For slow
watchdog timing please connect pin WMSEL to output voltage VCC. For fast watchdog timing please connect
WMSEL to ground (GND). The watchdog mode select pin WMSEL has an integrated pull-down resistor
RWMSEL,INT.
It is possible to change the time base during operation by switching the level at pin WMSEL from high to low
or from low to high. The new timing is valid from the beginning of the new period (beginning of new trigger
window). From this time on, the frequency of the microprocessor signal at pin WI has to be adapted, please
refer to Figure 11 and Figure 12. If the watchdog function is not used, please connect pin WMSEL to ground
(GND) to avoid EMC related influence.
Watchdog input pin WI:
The watchdog input pin WI is connected to the microprocessor (only if watchdog is used). If watchdog is not
used, please connect to ground (GND).
Initialization:
The watchdog initializes as soon as the reset signal at pin RO turns to high level. With a delay time equal to tRD
after the rising edge of the reset signal, the so-called “Ignore Window” starts. The duration of the “Ignore
Window” (IW) depends on the selected mode of the watchdog operation, either slow watchdog timing or fast
watchdog timing. Within this “Ignore Window” the microprocessor must initialize; during the “Ignore
Window” any signal at watchdog input pin WI is ignored. The watchdog input pin WI has an integrated pulldown resistor RWI,INT.
Normal operation (please refer to Figure 9 and Figure 10):
After closing the “Ignore Window” the watchdog opens the first “Trigger Window” (duration: watchdog period
tWD,p minus the watchdog sampling time tsam). Both watchdog period tWD,p and watchdog sampling time tsam
are depending on the selected mode of the watchdog operation, either slow watchdog timing or fast
watchdog timing. Within the “Trigger Window” a valid trigger signal must be applied to the watchdog input
WI. A valid trigger signal is a falling edge from VWI,H to VWI,L. After receiving a valid trigger signal within the
“Trigger Window” the watchdog immediately terminates the “Trigger Window” and opens the next “Trigger
Window” after a time duration tsam.
A trigger signal should not be applied during the time duration tsam before the beginning of the “Trigger
Window”, because this will not be detected.
The watchdog period tWD,p determines the frequency of the watchdog signal at pin WI coming from the
microprocessor. The watchdog output WO stays high as long as the watchdog input WI is triggered correctly.
If no valid trigger signal is applied to the pin WI during the “Trigger Window”, either a missing trigger signal or
an invalid trigger signal (please refer to explanation below), the watchdog output pin WO will be pulled to
ground with the falling edge of the “Trigger Window”. The watchdog pin WO stays at low level for the reset
Data Sheet
22
Rev. 1.1
2018-03-07
TLF50281ELV50
2.2 MHz Step-Down Regulator 500 mA, 5 V, low quiescent current
Reset and watchdog
delay time tRD. Then the watchdog output pin WO turns back to high level again. With the rising edge of the
watchdog signal a new “Ignore Window” is opened.
The watchdog signal WO does not influence the reset signal RO, but the reset signal RO influences the
watchdog signal WO.
If a reset condition occurs, the watchdog output pin WO is pulled to ground together with the reset output pin
RO. The watchdog output pin stays at low level as long as the reset output pin RO is pulled to ground plus the
reset delay time tRD; tRD is not depending on the selected mode of the watchdog operation. Then the watchdog
output pin WO turns back to high level again. With the rising edge of the watchdog signal a new “Ignore
Window” is opened.
Valid trigger signal (please refer to Figure 8):
Watchdog input WI is periodically sampled with a period of tsam. The watchdog sampling time tsam depends on
the selected mode of the watchdog operation, either slow watchdog timing or fast watchdog timing. A valid
trigger signal is a falling edge from VWI,H to VWI,L. To improve immunity against noise or glitches on the
watchdog input, at least two high samples followed by two low samples are required for a valid trigger signal.
For example, if the first three samples (two high one low) of the trigger pulse at pin WI are inside the watchdog
period tWD,p and only the fourth sample (the second low sample) is taken in the following period tWD,p, then the
watchdog output WO will be pulled to low. The frequency of the triggering signal at watchdog input pin WI
must be determined, so that valid triggering is ensured under all operating conditions.
Trigger Window 1
Trigger Window 2
Watchdog
Output (WO)
WI
Invalid
WI
Valid
Watchdog Decoder Sample Point
Figure 8
Valid triggering
Watchdog output pin WO:
The watchdog output is an open collector structure. As soon as the watchdog detects a microprocessor
failure, the pin is pulled to ground. A pull up resistor (R3) connected to VCC or another voltage source is
necessary. If the input (battery) voltage is below the input undervoltage shutdown threshold VS,off the pin RO
is pulled to ground (GND) and consequently pin WO is also pulled to ground (GND). As soon as the internal
supply of the chip drops down, the open collector structure is no longer able to pull pin WO to ground
therefore pin WO goes up to the pull-up voltage (if not supplied by voltage VCC).
The watchdog output pin WO might be connected in parallel to the reset output pin RO, if application requires
this.
Data Sheet
23
Rev. 1.1
2018-03-07
TLF50281ELV50
2.2 MHz Step-Down Regulator 500 mA, 5 V, low quiescent current
Reset and watchdog
VS
t
V CC
V RT,LOW
t
V RO
Power
Fail
t RD
t RD
t RR
t
t RD
t RD
V WMSEL
V WMSEL,H
V WMSEL,L
t
t sam
Trigger
Window
Ignore
Wnd
Ignore
Wnd
1. Correct Trigger 2. Correct Trigger
VWO
t
Missing
Trigger
Signal
causing
Watchdog
Signal
Figure 9
t
t WD,p
t < t WD,p
Don’t care WDI
during IW
V WI
Correct
Trigger
Correct
Trigger
Correct
Trigger
Reset Signal
causing
Watchdog Signal
t RD
t
Watchdog timing diagram, slow watchdog timing
VS
t
V CC
V RT,LOW
t
V RO
Power
Fail
t RD
t RD
t RR
t
t RD
t RD
V WMSEL
V WMSEL,H
V WMSEL,L
t
t < t WD,p
t sam
Trigger
Window
IW
IW
t
V WI
VWO
Don’t care WDI
during IW
t WD,p
1.Correct
Trigger
2.Correct
Trigger
3.Correct
Trigger
4.Correct
Trigger
causing
Watchdog
Signal
Figure 10
Data Sheet
t
Missing
Trigger
Signal
Correct
Trigger
Correct
Trigger
Correct
Trigger
Correct
Trigger
Correct
Trigger
Correct
Trigger
Reset Signal
causing
Watchdog Signal
t RD
t
Watchdog timing diagram, fast watchdog timing
24
Rev. 1.1
2018-03-07
TLF50281ELV50
2.2 MHz Step-Down Regulator 500 mA, 5 V, low quiescent current
Reset and watchdog
VS
t
V CC
V RT,LOW
t
V RO
t RD
t
t RD
V WMSEL
V WMSEL,H
V WMSEL,L
t
t < t WD,p(FAST)
t < tWD,p(SLOW)
Trigger
Window
IW
t
Don’t care WDI
during IW
V WI
t
Valid
Trigger
VWO
Valid
Trigger
Valid
Trigger
Valid
Trigger
Valid
Trigger
Valid
Trigger
Valid
Trigger
Valid
Trigger
t
Figure 11
Watchdog timing diagram, transition from slow to fast watchdog timing
VS
t
V CC
V RT,LOW
t
V RO
t RD
t
t RD
V WMSEL
V WMSEL,H
V WMSEL,L
t
t < t WD,p(FAST)
t < tWD,p(SLOW)
Trigger
Window
IW
t
V WI
Don’t care WDI
during IW
t
VWO
Valid
Trigger
Valid
Trigger
Valid
Trigger
Valid
Trigger
Valid
Trigger
Valid
Trigger
Valid
Trigger
Valid
Trigger
Valid
Trigger
Valid
Trigger
Valid
Trigger
t
Figure 12
Data Sheet
Watchdog timing diagram, transition from fast to slow watchdog timing
25
Rev. 1.1
2018-03-07
TLF50281ELV50
2.2 MHz Step-Down Regulator 500 mA, 5 V, low quiescent current
Reset and watchdog
6.4
Electrical characteristics watchdog function
Table 6
Electrical characteristics: watchdog
VS = 6.0 V to 40 V, Tj = -40°C to 150°C, all voltages with respect to ground (unless otherwise specified)
Parameter
Symbol
Values
Unit Note or Test Condition
Number
Min. Typ. Max.
Watchdog Mode Select WMSEL
Watchdog mode select, high
VWMSEL,H
4.00 –
–
V
–
P_6.4.1
Watchdog mode select, low
VWMSEL,L
–
–
0.80 V
–
P_6.4.2
Watchdog mode select input
current
IWMSEL
–
3
4
µA
VWMSEL = 5 V
P_6.4.3
Watchdog mode select, internal
resistor to GND
RWMSEL,INT 1.25 1.67 –
MΩ
–
P_6.4.4
High level input voltage
VWI,H
4.00 –
–
V
–
P_6.4.5
Low level input voltage
VWI,L
–
–
0.80 V
–
P_6.4.6
High level input current
IWI,H
–
3
4
µA
VWI = 5V
P_6.4.7
Low level input current
IWI,L
–
0.5
1
µA
VWI = 0.4 V; Tj < 105°C
P_6.4.8
Watchdog sampling time
tsam
0.40 0.50 0.60 ms
fast watchdog timing
P_6.4.9
0.80 1.00 1.20 ms
slow watchdog timing
25.6 32.0 38.4 ms
fast watchdog timing
51.2 64.0 76.8 ms
slow watchdog timing
25.6 32
38.4 ms
fast watchdog timing
51.2 64
76.8 ms
slow watchdog timing
Watchdog Input WI
Ignore window time
Watchdog period
tIW
tWD,p
Watchdog input, internal resistor to RWI,INT
GND
P_6.4.10
P_6.4.11
1.25 1.67 –
MΩ
–
P_6.4.12
Watchdog Output WO
Output voltage low
VWO,L
–
0.2
0.4
V
VOUT = 5 V; IWO = 1 mA
P_6.4.13
Sink current limit
IWO,L,MAX
1
–
–
mA
VOUT = 5 V; VWO = 0.4 V
P_6.4.14
Leakage current
IWO,H,MAX
–
–
1
µA
VWO = 5 V
P_6.4.15
Data Sheet
26
Rev. 1.1
2018-03-07
TLF50281ELV50
2.2 MHz Step-Down Regulator 500 mA, 5 V, low quiescent current
Enable and thermal shutdown
7
Enable and thermal shutdown
7.1
Description
A valid high level at pin EN (VEN,hi) turns the regulator on, a valid low level at pin EN (VEN,lo) turns the regulator
off. In off state the current consumption of the device is less than 2 µA. An integrated pull down resistor at pin
EN (REN,INT) ensures, that the device is switched off, if pin EN is left open.
The integrated thermal shutdown function turns off the power switch in case of overtemperature. The typical
junction shutdown temperature is 175°C, with a min. of 155°C. After cooling down, the IC will automatically
restart with a soft start into normal operation. The thermal shutdown is an integrated protection function
designed to prevent IC destruction when operating under fault conditions. It should not be used for normal
operation.
7.2
Electrical characteristics Enable, bias and thermal shutdown
Table 7
Electrical characteristics: Enable, bias and thermal shutdown
VS = 6.0 V to 40 V, Tj = -40°C to 150°C, all voltages with respect to ground (unless otherwise specified)
Parameter
Symbol
Values
Unit Note or Test Condition
Number
Min. Typ. Max.
Enable EN
Current consumption, shut down
mode
Iq,OFF
Current consumption of VCC
Iq,ON,V_CC –
–
0.1
2
µA
VEN = 0 V;
Tj < 105°C; VS = 16 V
P_7.2.1
–
60
µA
VEN = 5.0 V; VS = 16 V;
VCC = 5.4 V;
Tj < 105°C;
P_7.2.2
VEN = 5.0 V; VS = 16 V;
VCC = 5.4 V;
Tj < 105°C;
P_7.2.3
PFM mode
Current consumption of VS
Iq,ON,V_S –
15
20
µA
PFM mode
Enable high signal valid
VEN,hi
3.0
–
–
V
–
P_7.2.4
Enable low signal valid
VEN,lo
–
–
0.8
V
–
P_7.2.5
Enable hysteresis
VEN,HY
50
200
400
mV
–
P_7.2.6
Enable high input current
IEN,hi
–
–
3
µA
VEN = 16 V
P_7.2.7
Enable low input current
IEN,lo
–
0.1
1
µA
VEN = 0.5 V
P_7.2.8
Enable internal resistor to GND
REN,INT
7
12
20
MΩ
VEN = 3 V
P_7.2.9
195
°C
1)
P_7.2.14
–
K
Internal overtemperature protection
Overtemperature shutdown
Tj,sd
Overtemperature shutdown
hysteresis
Tj,sd_hyst -
155 175
15
P_7.2.15
1) Specified by design. Not subject to production test.
Data Sheet
27
Rev. 1.1
2018-03-07
TLF50281ELV50
2.2 MHz Step-Down Regulator 500 mA, 5 V, low quiescent current
Oscillator
8
Oscillator
8.1
Description
The oscillator supplies the device with a constant frequency. The power switch will be switched on and off
with a constant frequency fOSC. The time period TPWM is derived from this frequency and some safety functions
are synchronized to this frequency.
The oscillator frequency can be set by connecting an external resistor RFREQ between pin FREQ and GND using
the following table (selected values, for more precise setting please refer to Figure 13).
Frequency setting resistor
Frequency adjusting resistor
RFREQ
39
43
56
82
100
kΩ
P_8.1.1
Oscillator frequency
fosc
2400
2250
1800
1330
1100
kHz
P_8.1.2
2,5
Switching Frequency [MHz]
2,35
2,2
2,05
1,9
1,75
1,6
1,45
1,3
1,15
1
30
35
40
45
50
55
60
65
70
75
80
85
90
95
100
105
Resistor at Freq pin [kΩ]
Figure 13
Switching frequency fOSC versus frequency setting resistor RFREQ.
The turn-on frequency can optionally be set externally via the SYNC pin. In this case the synchronization of the
PWM-on signal refers to the falling edge of the SYNC-pin input signal. In case the synchronization to an
external clock signal is not needed, the SYNC pin should be connected to ground. The frequency setting
resistor RFREQ is also necessary for SYNC option and must be dimensioned according to the desired
synchronization frequency (the ratio between synchronization and internal frequency has to be less than or
equal to 1).
The synchronization function is not available in PFM mode.
Data Sheet
28
Rev. 1.1
2018-03-07
TLF50281ELV50
2.2 MHz Step-Down Regulator 500 mA, 5 V, low quiescent current
Oscillator
8.2
Electrical characteristics buck regulator
Table 8
Electrical characteristics: buck regulator
VS = 6.0 V to 40 V, Tj = -40°C to 150°C, all voltages with respect to ground (unless otherwise specified)
Parameter
Symbol
Values
Unit Note or
Number
Test
Condition
Min. Typ. Max.
fosc
2025 2250 2475 kHz VSYNC = 0 V;
RFREQ = 43 kΩ
P_8.2.1
fsync
1500 –
2200 kHz –
P_8.2.2
P_8.2.3
Frequency setting FREQ
Oscillator frequency spread
Synchronization SYNC
Synchronization capture range
SYNC signal high level valid
VSYNC,H
2.9
–
–
V
1)
SYNC signal low level valid
VSYNC,L
–
–
0.8
V
1)
P_8.2.4
SYNC input internal pull-down
RSYNC,INT
0.15 0.25 0.40 MΩ
VSYNC = 5 V
P_8.2.5
SYNC signal minimum high time
tSYNC,H, min 50
–
–
ns
–
P_8.2.6
SYNC signal minimum low time
tSYNC,L,min 50
–
–
ns
–
P_8.2.7
1) Synchronization of PWM-on signal to falling edge.
Data Sheet
29
Rev. 1.1
2018-03-07
TLF50281ELV50
2.2 MHz Step-Down Regulator 500 mA, 5 V, low quiescent current
Application information
9
Application information
Note:
The following information is given as a hint for the implementation of the device only and shall
not be regarded as a description or warranty of a certain functionality, condition or quality of the
device.
LIN
DIN
VS
CIN1
CIN2
LIN, CIN1 and CIN3 recommended for
suppression of EME,
DIN depending on application
CIN3
VS
TLF50281EL
Over
Temperature
Shutdown
EN
Enable
LOUT
Buck
Converter
SWO
VCC
FREQ
VCC
Oscillator
INT.
SUPPLY
SYNC
R5
COUT
FB
Bandgap
Reference
R3
DCATCH
Soft Start
Ramp
Generator
From
μP
WI
To μP
WO
R1
R4
RTADJ
Reset
Generator
Watchdog
To μP
RO
R2
WMSEL
GND
GND N.C.
Figure 14
Application diagram
Note:
This is a very simplified example of an application circuit. The function must be verified in the real
application.
Part-No.
CIN2
CIN3
COUT
DCATCH
LOUT
R1
R2
R3
R4
R5
Figure 15
Data Sheet
Value
47μF/50V
100nF/50V
10μF/25V
1A/100V
10μH
330 kΩ
100 kΩ
100 kΩ
100 kΩ
43 kΩ
Type
electrolytic
ceramic
ceramic
10BQ100 Schottky
MSS1278T
0.25 W
0.25 W
0.25 W
0.25 W
0.25 W
Manufacturer
AVX
AVX
AVX
International Rectifier
Coilcraft
Panasonic
Panasonic
Panasonic
Panasonic
Panasonic
Remark
For improving EME
1 A current capability
4.7 μH also possible
VRT set to 4.3 V
VRT set to 4.3 V
fOSC set to 2.2 MHz
Bill of material for application diagram
30
Rev. 1.1
2018-03-07
TLF50281ELV50
2.2 MHz Step-Down Regulator 500 mA, 5 V, low quiescent current
Application information
9.1
General layout recommendations
Introduction:
A switch mode step down converter is a potential source of electromagnetic disturbances which may affect
the environment as well as the device itself and cause sporadic malfunction up to damages depending on the
amount of noise.
In principal we may consider the following basic effects:
•
radiated magnetic fields caused by circular currents, occurring mostly with the switching frequency and
their harmonics;
•
radiated electric fields, often caused by (voltage) oscillations;
•
conducted disturbances (voltage spikes or oscillations) on the lines, mostly input and output lines.
Radiated magnetic fields:
Radiated magnetic fields are caused by circular currents occurring in so called “current windows”. These
circular currents are alternating currents which are driven by the switching transistor. The alternating current
in these windows are driving magnetic fields. The amount of magnetic emissions is mainly depending on the
amplitude of the alternating current and the size of the so-called “window” (this is the area, which is defined
by the circular current paths.
We can divide into two windows:
•
the input current “window” (path consisting of CIN2, CIN3, LOUT and COUT): Only the alternate content of the
input current IS is considered;
•
the output current “window” (path consisting of DCATCH, LOUT and COUT): Output current ripple ∆I.
The area of these “windows” has to be kept as small as possible, with the relating elements placed next to each
others as close as possible. It is highly recommended to use a ground plane as a single layer which covers the
complete regulator area with all components shown in the application diagram. All connections to ground
shall be as short as possible.
Radiated electric fields:
Radiated electric fields are caused by voltage oscillations occurring by stray inductances and stray
capacitances at the connection between internal power stage (pin SWO), freewheeling diode DCATCH, and
output capacitor COUT. They are also of course influenced by the commutation of the current from the internal
power stage to the freewheeling diode DCATCH. Their frequencies might be above 100 MHz. Therefore, it is
recommended to use a fast Schottky diode and to keep the connections in this area as low inductive as
possible. This can be achieved by using short and broad connections and by arranging the related parts as
close as possible. Following the recommendation of using a ground layer these low inductive connections will
form together with the ground layer small capacitances which are desirable to damp the slope of these
oscillations. The oscillations use connections or wires as antennas, this effect can also be minimized by the
short and broad connections.
Conducted disturbances:
Conducted disturbances are voltage spikes or voltage oscillations, occurring permanently or by occasion
mostly on the input or output connections. Comparable to the radiated electric fields they are caused by
voltage stage, freewheeling diode DCATCH, and output capacitor COUT.
Their frequencies might be above 100 MHz. They are super positioned to the input and output voltage and
might therefore disturb other components of the application.
The countermeasures against conducted disturbances are similar to the radiated electric fields:
Data Sheet
31
Rev. 1.1
2018-03-07
TLF50281ELV50
2.2 MHz Step-Down Regulator 500 mA, 5 V, low quiescent current
Application information
•
it is recommended to use short and thick connections between the single parts of the converter;
•
all parts shall be mounted close together;
•
additional filter capacitors (ceramic, with low ESR i.e CIN3 in the application diagram) in parallel to the
output and input capacitor and as close as possible to the switching parts. Input and load current must be
forced to pass these devices, do not connect them via thin lines. Recommended values from 10 nF to
220 nF;
•
for the input filter a so called π – Filter for maximum suppression might be necessary, which requires
additional capacitors on the input.
9.2
Further application information
•
Please contact us for information regarding the FMEA pin
•
Existing Application Notes with more detailed information about the possibilities of this device
•
For further information you may contact http://www.infineon.com/
Data Sheet
32
Rev. 1.1
2018-03-07
TLF50281ELV50
2.2 MHz Step-Down Regulator 500 mA, 5 V, low quiescent current
Package outlines
10
Package outlines
0.15 M C A-B D 14x
0.64 ±0.25
1
8
1
7
0.2
M
D 8x
Bottom View
3 ±0.2
A
14
6 ±0.2
D
Exposed
Diepad
B
0.1 C A-B 2x
14
7
8
2.65 ±0.2
0.25 ±0.05 2)
0.08 C
8˚ MAX.
C
0.65
0.1 C D
0.19 +0.06
1.7 MAX.
Stand Off
(1.45)
0 ... 0.1
0.35 x 45˚
3.9 ±0.11)
4.9 ±0.11)
Index Marking
1) Does not include plastic or metal protrusion of 0.15 max. per side
2) Does not include dambar protrusion
PG-SSOP-14-1,-2,-3-PO V02
Figure 16
Package outline PG-SSOP-14
Green Product (RoHS compliant)
To meet the world-wide customer requirements for environmentally friendly products and to be compliant
with government regulations the device is available as a green product. Green products are RoHS-Compliant
(i.e Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).
For further information on alternative packages, please visit our website:
http://www.infineon.com/packages.
Data Sheet
33
Dimensions in mm
Rev. 1.1
2018-03-07
TLF50281ELV50
2.2 MHz Step-Down Regulator 500 mA, 5 V, low quiescent current
Revision history
11
Revision history
Table 9
Revision history
Revision
Date
Changes
Rev 1.1
2018-03-06
P_8.2.6 Min value changed from 25 ns to 50 ns.
P_8.2.7 Min value changed from 25 ns to 50 ns.
Editorial changes.
Rev 1.01
2013-04-30
Editorial change: Pin FREQ added to chapter General Product Characteristics.
Efficiency graphs, Line Regulation graphs changed in chapter Buck Regulator. Table
Frequency setting resistor updated in chapter Oscillator. Bill of material updated in
chapter Application Information. Pin 12 N.C. on chapter Pin Configuration.
Electrical Characteristics change: table updated in chapter Oscillator.
Rev 1.0
2011-10-24
Initial data sheet.
Data Sheet
34
Rev. 1.1
2018-03-07
Trademarks
All referenced product or service names and trademarks are the property of their respective owners.
Edition 2018-03-07
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2018 Infineon Technologies AG.
All Rights Reserved.
Do you have a question about any
aspect of this document?
Email: erratum@infineon.com
Document reference
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hereby disclaims any and all warranties and liabilities
of any kind, including without limitation warranties of
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