TLF51801ELV
10 A synchronous DC/DC Step-Down Controller
Data sheet
Rev. 1.0.1, 2013-04-15
Automotive Power
10 A synchronous DC/DC Step-Down Controller
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TLF51801ELV
Overview
10 A synchronous step down Controller
Current limitation adjustable with Shunt resistor or Rdson
Adjustable output voltage
± 2% output voltage tolerance
External power transistors
Integrated bootstrap diode
PWM regulation
Very Low Dropout Operation: max Duty Cycle higher than 99%
Input voltage range from 4.75V to 45V
Adjustable switching frequency from 100 to 700 kHz
Synchronization input
Very low shutdown current consumption (99
%
–
1.20
Dmax x VS
V
–
-40
150
°C
–
Note: Within the functional range the IC operates as described in the circuit description. The electrical
characteristics are specified within the conditions given in the related electrical characteristics table.
4.3
Pos.
4.3.1
4.3.2
Thermal Resistance
Parameter
Junction to Case
Symbol
1)
Junction to Ambient
4.3.3
4.3.4
1) 2)
RthJC
RthJA
RthJA
RthJA
Limit Values
Unit
Conditions
Min.
Typ.
Max.
–
10
–
K/W
–
–
47
–
K/W
2s2p
–
54
–
K/W
1s0p + 600 mm2
–
64
–
K/W
1s0p + 300 mm2
1) Not subject to production test, specified by design.
2) Specified RthJA value is according to JEDEC 2s2p (JESD 51-7) + (JESD 51-5) and JEDEC 1s0p (JESD 51-3) + heatsink
area at natural convection on FR4 board;
Data sheet
7
Rev. 1.0.1, 2013-04-15
TLF51801ELV
Regulator
5
Regulator
5.1
Description
The TLF51801ELV is a synchronous step down controller for output currents up to 10 Amps. The power stage
consists of two external MOSFETs with logic level gate signal. The switching frequency can be adjusted between
100 and 700 kHz by connecting an external resistor between pin SYNC/FREQ and GND (FREQ-mode). By
connecting this pin to a frequency source the TLF51801ELV might be synchronized to a frequency between 350
and 700 kHz (SYNC-mode).
A valid high signal at pin EN will start the regulator. Then it will ramp up with a soft start ramp, which is derived
from the switching frequency (i.e.: the soft start ramp will last around 1 msec at a switching frequency of 500 kHz).
The regulator is working in voltage mode, there is no feedforward function included and it operates in continuous
conduction mode only.
An external compensation network connected to pin COMP is necessary to compensate the switching ripple on
the feedback line. The compensation network must be adapted to the application.
The regulator can withstand a short circuit at the output. The current limitation can be implemented measuring the
drop across the Rdson of the external high-side MOSFET (Rdson-configuration), or by shunt resistor located in
series with the drain of high-side MOSFET (Shunt-configuration).
The output voltage is monitored using pin FB. If the output voltage exceeds the overvoltage threshold (10% higher
than the regulated output voltage), the low-side external MOSFET is turned on in order to discharge the output
capacitor and lower the output voltage to the nominal value.
SENSELOW
BTS
UV
SENSEHIGH
BLANK
OC
UG
CLOCK
LS
COMP
Force
Min Duty
PWM
EA
COMP
+
UG
DRIVER
CROSS CONDUCTION
SAFETY LOGIC
BUO
L
O
G
IC
Skipping
Mode
FB
PHS
DETECT
VREF
1.2V
+
-
LG
V_LS
SAWTOOTH GEN
UV
POR
IVCC
LG
DRIVER
PGND
BG
SOFTSTART LOGIC
BG
Figure 3
Data sheet
TSD
OV
OVERVOLTAGESHUTDOWN
THERMALSHUTDOWN
Block Diagram Buck Regulator
8
Rev. 1.0.1, 2013-04-15
TLF51801ELV
Regulator
5.2
The Soft start
x0.6
Vfb
+
UV
-
UV
CK
SoSt_25%End
Vbg
EN
POR IVCC
TSD
SoSt_100%End
Logic
Stair
start
Force
min
Toff
To_LG
Vref1V2
CK
Figure 4
Soft start block diagram
An integrated Soft start function (of duration 512 clock cycles, where a clock cycle is derived from the switching
frequency) ensures that the inrush current will be limited and prevents from output voltage overshoots.
When the regulator starts from OFF state (EN pin forced from low to high), an additional pre-charging function is
triggered before Soft start: for a time slot of 64 clock cycles, low-side MOSFET is switched ON and OFF at fixed
frequency of 1.5 MHz and 50% duty cycle, in order to charge in advance the bootstrap capacitor.
If an under voltage appears during Soft start, it is recognized only after 25% of the Soft start stair, this is realized
by the signal SoSt_25%End. In case 1) the UV is permanent fault (i.e. the BTS cap is not charged or shorted, or
the output cap is shorted). In case 2) the UV failure is removed before the 25% of the Soft start procedure is
reached (i.e. the output cap is too large and the system is not able to charge it fast enough). In case 1), a
permanent UV, the soft start begins again the procedure after a delay of 512 clock cycles.
In case of pre-charged output condition, the system recognizes it and keeps the external switches in high
impedance in order not to discharge the output capacitance.
sta rt
1 .2V
D e la y
D e la y
V re f1 V 2
S o S t_ 2 5% E n d
UV
F ig u re 1)
sta rt
1 .2V
1.2 V
D e la y
V re f1 V 2
S o S t_ 2 5% E n d
UV
i.e o u tp u t
sh o rt
Figure 5
Data sheet
F ig u re 2)
Soft start timing
9
Rev. 1.0.1, 2013-04-15
TLF51801ELV
Regulator
5.3
Operation Mode
The PWM pulses are voltage controlled. The error amplifier and the PWM comparator are creating the PWM
pulses using the oscillator saw-tooth signal and the feedback voltage. The pulse-width modulation is done so that
the feedback voltage is similar to the reference voltage (1.2 V). To achieve a stable output voltage even under very
low or very high duty cycle conditions a pulse skipping mode is implemented. When the minimum off time for the
up-side gate is reached (boundary between dark grey area and light grey area in Figure 6), the TLF51801ELV
operates in pulse skipping mode for high duty cycle. This operation mode is typically used with low supply voltages
for very low dropout operation. If the minimum on time for the up-side gate is reached (boundary between dark
grey area and light grey area in Figure 6) the TLF51801ELV operates in pulse skipping mode for low duty cycle.
Figure 6
Data sheet
Operation Mode
10
Rev. 1.0.1, 2013-04-15
TLF51801ELV
Regulator
5.4
Bootstrap concept
The high-side MOSFET driver is supplied by the bootstrap concept. The capacitor at pin BTS and BUO must be
switched to GND to be charged by the internal LDO. A monitoring circuit controls the charge of the bootstrap
capacitor. If the charge is sufficient the driver will trigger the external high-side MOSFET. If a recharge is
necessary, the capacitor will be loaded using the integrated bootstrap diode by switching pin BUO to ground
forcing a proper PWM signal.
For very high duty-cycle and high input capacitance of the MOSFET, it may be necessary to consider use of an
external diode placed in parallel with the internal bootstrap diode to speed up the recharge of the bootstrap
capacitor. In addition, the small voltage drop across the external diode improves the overdrive of the gate of the
high-side MOSFET.
BTS
UV
VS
CBTS
UG
LS
UG
DRIVER
Linear Regulator
PWM
CROSS
CONDUCTION
SAFETY LOGIC
BUO
EN
PHS
DETECT
LG
V_LS
IVCC
LG
DRIVER
PGND
Parts in grey are optional
Figure 7
Data sheet
Bootstrap concept
11
Rev. 1.0.1, 2013-04-15
TLF51801ELV
Regulator
5.5
Current Limitation
5.5.1
Rdson-configuration
To optimize the efficiency, the regulator is measuring the voltage (which is the current through the MOSFET
multiplied by the Rdson) over the high-side switch, if it should be too high the pulse will be cut off. By varying the
sense resistor between the pin sensehigh and the drain of the high-side MOSFET the current limit can be adjusted.
Senselow is connected to the source of the MOSFET.
P o w e r c u rre n t
flo w
E x te rn a l h ig h s id e M O S
VS
BUO
95µA
R_SENSE
S E N S E H IG H
SEN SE LO W
OVERCURRENT
CO M PARATO R
(O V C )
IOC_lim,ref
OVERCURRENT
L O G IC S IG N A L
BLANK
Figure 8
Rdson-configuration for current limitation
The figure above shows the concept of the Rdson configuration for current limitation. The characteristics of the
external high-side MOSFET must be known, especially its thermal behavior. The current limitation might be
calculated with the following equation:
I limit = I OC
Data sheet
_ lim, ref
⋅
R _ SENSE
Rdson _ EXT _ MOS
12
Rev. 1.0.1, 2013-04-15
TLF51801ELV
Regulator
5.5.2
Shunt-configuration
The regulator is offering a second possibility to do a more accurate current measurement by shunt resistor located
in series with the drain of the high-side MOSFET. The shunt resistor will be placed in the input current path and
be connected to the overcurrent comparator with pin senselow and through a sense resistor to pin sensehigh. By
varying the sense resistor the current limit can be adjusted.
P o w e r c u rre n t
flo w
E x te rn a l h ig h s id e M O S
VS
BUO
R_S HU N T
95µA
R_SENSE
S E N S E H IG H
SENSELO W
OVERCURRENT
COMPARATOR
(O V C )
IOC_lim,ref
OVERCURRENT
L O G IC S IG N A L
BLANK
Figure 9
Shunt-configuration for current limitation
The Shunt-configuration works similar to the Rdson-configuration, it uses also pins Sensehigh and Senselow. The
current limitation might be calculated with the following equation:
I
Data sheet
limit
=
I
OC
_ lim,
⋅
ref
13
R _ SENSE
R _ SHUNT
Rev. 1.0.1, 2013-04-15
TLF51801ELV
Regulator
5.6
Electrical Characteristics
Electrical Characteristics:
VS = 6.0 V to 40 V, Tj = -40°C to +150°C, all voltages with respect to ground (unless otherwise specified)
Pos.
Parameter
Symbol
Limit Values
Min.
5.6.1
Output voltage
VFB
Typ.
Unit
Conditions
V
VEN = 12V;
Max.
1.176 1.200 1.224
ICC < 10A
5.6.2
Output overvoltage threshold
VFB,OV
1.05 x 1.1 x
1.15 x V
VFB
VFB
VFB
VFB increasing;
VCOMP = 3V;
Monitor LG low to high
5.6.3
Output overvoltage threshold
hysteresis
VFB,OV,hyst 0.02 x
VFB
IFB
-1
gmEA
0.8
REA,OUT
1.0
VFB
VFB
-0.1
0
µA
1.2
1.6
mS
–
–
MΩ
–
1.6
V
5.6.4
FB input current
5.6.5
Error amplifier, gain
5.6.6
Error amplifier, output resistance
5.6.7
Error amplifier, ramp amplitude,
FREQ-mode
VComp,peak 1.0
Error amplifier, ramp amplitude,
SYNC-mode
VComp,peak 0.6
5.6.8
0.05 x 0.08 x V
–
VFB = 1.2V
VFB = 1.2V
VFB = 1.2V;
VCOMP = 1.2V
VFB = 1.2V;
FREQ-mode;
fFREQ = 100 -700kHz;
Monitor LG
to peak,FREQ
–
2.6
V
VFB = 1.2V;
SYNC-mode;
fSYNC = 350 -700kHz;
Monitor LG
to peak,SYNC
5.6.9
Error amplifier output, source and IComp,max
sink current
150
280
450
μA
Source current:
VFB = 0.8V, VCOMP= 2.5V;
Sink current:
VFB = 2.4V, VCOMP= 2.5V
5.6.10
Comp pin, minimum voltage
VComp,min
0.8
–
–
V
VCOMP increasing;
Monitor UG
Bootstrap under voltage lockout
threshold for UG turn-off
VBTS,off
5.6.12
Bootstrap under voltage lockout,
hysteresis
VBTS,hyst
–
300
–
mV
–
5.6.13
Bootstrap capacitor discharge
current
IBTS_BUO
–
150
–
µA
VBTS_BUO = 4.5V
5.6.14
Bootstrap diode forward voltage
–
0.8
–
V
IDBTS = 20mA
5.6.15
Minimum on time Upper Gate
–
100
–
ns
1)
5.6.16
Minimum off time Upper Gate
–
100
–
ns
1)
5.6.17
Soft start ramp
VDBTS,fwd
TUGON,min
TUGOFF,min
tstart
–
512 x
1/f
–
µs
5.6.18
Input under voltage shutdown
threshold
VS,off
3.7
–
–
V
f = fFREQ, FREQ-mode;
f = fSYNC, SYNC-mode
VS decreasing
5.6.11
Data sheet
VBUO
–
–
V
14
VBTS_BUO voltage
decreasing
+ 3.0
Rev. 1.0.1, 2013-04-15
TLF51801ELV
Regulator
Electrical Characteristics:
VS = 6.0 V to 40 V, Tj = -40°C to +150°C, all voltages with respect to ground (unless otherwise specified)
Pos.
Parameter
Symbol
Limit Values
Unit
Conditions
Min.
Typ.
Max.
–
–
4.75
V
VS increasing
–
300
–
mV
–
Upper Gate Driver Peak Sourcing IUG,SRC
Current
–
-380
–
mA
VUG = 3.5V;
Upper Gate Driver Peak Sinking
Current
IUG,SNK
–
5.6.23
Upper Gate Driver Output Rise
Time
tR,UG
–
30
60
ns
5.6.24
Upper Gate Driver Output Fall
Time
tF,UG
–
20
40
ns
5.6.25
Upper Gate Driver Output Voltage VUG
–
4.4
5.2
V
CL,UG = 3.3nF;
VUG = 1V to 4V
CL,UG = 3.3nF;
VUG = 1V to 4V
CL,UG = 3.3nF
Lower Gate Driver Peak Sourcing ILG,SRC
Current
–
-380
–
mA
VLG = 3.5V;
Lower Gate Driver Peak Sinking
Current
ILG,SNK
–
5.6.28
Lower Gate Driver Output Rise
Time
tR,LG
–
30
60
ns
5.6.29
Lower Gate Driver Output Fall
Time
tF,LG
–
20
40
ns
5.6.30
Lower Gate Driver Output Voltage VLG
5.05
5.40
5.75
V
5.6.31
Overcurrent limitation
89
95
101
μA
5.6.19
Input voltage startup threshold
5.6.20
Input under voltage shutdown
hysteresis
VS,on
VS,hyst
Gate Driver for upper Switch
5.6.21
5.6.22
1)
550
–
mA
VUG = 1.5V;
1)
Gate Driver for lower Switch
5.6.26
5.6.27
IOC_lim,ref
1)
550
–
mA
VLG = 1.5V;
1)
CL,LG = 3.3nF;
VLG = 1V to 4V
CL,LG = 3.3nF;
VLG = 1V to 4V
CL,LG = 3.3nF;
VS ≥ 7V
VCOMP = 3V
sensehigh-senselow
decreasing;
monitor max current on
sensehigh
5.6.32
Overcurrent comparator offset
voltage
VOCComp,
-15
Offset
–
+15
mV
VFB = 1V;
VCOMP = 4V;
sensehigh-senselow
increasing
1) Not subject to production test, specified by design.
Data sheet
15
Rev. 1.0.1, 2013-04-15
TLF51801ELV
Module Oscillator
6
Module Oscillator
6.1
Description
The oscillator supplies the device with a constant frequency. When the device is not operating in pulse skipping
mode, the external MOSFETs are switched on and off with the same constant frequency. Some safety functions
are synchronized also to this frequency.
The internal oscillator is used to determine the switching frequency of the buck regulator. The switching frequency
can be selected from 100 kHz to 700 kHz with an external resistor connected at pin SYNC/FREQ to GND. To set
the switching frequency with an external resistor the following formula can be applied
R FREQ =
1
(149 × 10 [ ])× ( f
−12
s
Ω
FREQ
[1s ])
(
)
− 2 . 0 × 10 3 [Ω ] [Ω ]
80
70
RFREQ (kΩ)
60
50
40
30
20
10
0
100
200
300
400
500
600
700
Switching Frequency fFREQ (kHz)
Figure 10
Resistor RFREQ versus Switching Frequency fFREQ
The turn-on frequency can optionally be set externally via the pin SYNC/FREQ. In this case the synchronization
of the PWM-on signal refers to the falling edge of the pin SYNC/FREQ input signal.
Data sheet
16
Rev. 1.0.1, 2013-04-15
TLF51801ELV
Module Oscillator
6.2
Electrical Characteristics Module Oscillator
Electrical Characteristics: Module Oscillator
VS = 6.0 V to 40 V, Tj = -40°C to +150°C, all voltages with respect to ground (unless otherwise specified)
Pos.
Parameter
Symbol
Limit Values
Unit
Conditions
Min.
Typ.
Max.
fFREQ
fFREQ
250
300
350
kHz
RFREQ = 20kΩ
100
–
700
kHz
17% internal
tolerance + external
resistor tolerance
IFREQ
–
–
800
µA
VFREQ = 0 V
–
700
kHz
1)
80
%
Oscillator:
6.2.1
Oscillator Frequency
6.2.2
Oscillator Frequency
Adjustment Range
6.2.3
FREQ Supply Current
Synchronization
6.2.4
Synchronization Frequency
Capture Range
fSYNC
350
6.2.5
Synchronization Signal Duty cycle
20
6.2.6
Synchronization Signal
High Logic Level Valid
DSYNC
VSYNC,H
3.0
–
–
V
2)
6.2.7
Synchronization Signal
Low Logic Level Valid
VSYNC,L
–
–
0.8
V
2)
1) Synchronization frequency out of the specified range leads to complete malfunction of the device
2) Synchronization of external UG ON signal to falling edge
Data sheet
17
Rev. 1.0.1, 2013-04-15
TLF51801ELV
Linear Regulator
7
Linear Regulator
7.1
Description
The internal linear voltage regulator supplies the low-side gate driver directly (typical voltage 5.4 V) and through
a diode the high-side gate driver. The current capability is up to 50 mA. An external output capacitor with low ESR
is required on pin IVCC for stability and buffering transient load currents. During normal operation the gate drivers
will draw transient currents from the linear regulator and its output capacitor. Proper sizing of the output capacitor
must be considered to supply sufficient peak current to the gate of the external MOSFETs. An integrated poweron reset circuit monitors the linear regulator output voltage and resets the device in case the output voltage falls
below the power-on reset threshold. The power-on reset helps protect the external MOSFETs from excessive
power dissipation by ensuring the gate drive voltage is sufficient to enhance the gate of an external logic level nchannel MOSFET. For IVCC voltage lower than 5V the proper charging of the bootstrap capacitor is not
guaranteed.
The internal linear voltage regulator is implemented to supply the gate drivers, therefore a large voltage ripple may
be present on this output due to the pulsed current sinked by internal drivers and bootstrap diode. This output
should not be used to supply loads than the internal ones.
VS
IVCC
1
3
Linear Regulator
EN
Figure 11
Data sheet
HS Gate
Driver
2
LS Gate
Driver
Linear Regulator Block Diagram and Simplified Application Circuit
18
Rev. 1.0.1, 2013-04-15
TLF51801ELV
Linear Regulator
7.2
Electrical Characteristics
Electrical Characteristics: Linear Regulator
VS = 6V to 40V; Tj = -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin; (unless
otherwise specified)
Pos.
Parameter
Symbol
Limit Values
Unit
Conditions
Min.
Typ.
Max.
5.4
5.75
V
7 V ≤ VS ≤ 40 V;
0.1 mA ≤ IIVCC ≤ 50 mA
110
mA
800
mV
VS = 13.5 V;
VIVCC = 5.1V
IIVCC = 50mA 1)
3
µF
2)
0.5
Ω
f = 10kHz
VIVCC decreasing;
VIVCC - VIVCC,RTH,d
VIVCC decreasing
VIVCC increasing
7.2.1
Output Voltage
VIVCC
5.05
7.2.2
Output Current Limitation
ILIM
51
7.2.3
7.2.6
VDR
Output Capacitor
CIVCC
0.47
Output Capacitor ESR
RIVCC,ESR
Undervoltage Reset Headroom VIVCC,HDRM 100
–
–
mV
7.2.7
Undervoltage Reset Threshold VIVCC,RTH,d
4.0
–
–
V
7.2.8
Undervoltage Reset Threshold VIVCC,RTH,i
–
–
4.5
V
7.2.4
7.2.5
Drop out Voltage
1) Measured when the output voltage VIVCC has dropped 100 mV from its nominal value.
2) Minimum value given is needed for regulator stability; application might need higher capacitance than the minimum.
Data sheet
19
Rev. 1.0.1, 2013-04-15
TLF51801ELV
Module Enable and Thermal Shutdown
8
Module Enable and Thermal Shutdown
8.1
Description
With the enable pin the device can be set in off-state reducing the current consumption to less than 2µA.
The enable function features an integrated pull down resistor which ensures that the IC is shut down and the
external MOSFETs are off in case the pin EN is left open.
The integrated thermal shutdown function turns the external MOSFETs off in case of overtemperature. The typical
junction shutdown temperature is 175°C, with a minimum of 160°C. After cooling down, the IC will automatically
restart with soft start. The thermal shutdown is an integrated protection function designed to prevent IC destruction
when operating under fault conditions.
8.2
Electrical Characteristics Module Enable, Bias and Thermal Shutdown
Electrical Characteristics: Enable, Bias and Thermal Shutdown
VS = 6.0 V to 40 V, Tj = -40°C to +150°C, all voltages with respect to ground (unless otherwise specified)
Pos.
Parameter
Symbol
Limit Values
Min.
Typ.
Max.
Unit
Conditions
8.2.1
Current Consumption,
shut down mode
Iq,OFF
–
0.1
2
µA
8.2.2
Current Consumption,
active mode
Iq,ON
–
3
10
mA
VEN = 0.8V;
Tj < 105°C; Vs = 16V
VEN = 5.0V;
IIVCC= 0mA;
VS = 16V
8.2.3
VEN,lo
Enable low signal valid
VEN,hi
Enable hysteresis
VEN,HY
Enable high input current
IEN,hi
Enable low input current
IEN,lo
Over temperature shutdown Tj,sd
Over temperature shutdown Tj,sd_hyst
3.0
–
–
V
–
–
–
0.8
V
–
200
300
400
mV
–
–
30
µA
–
0.1
1
µA
160
175
190
°C
1)
–
15
–
K
1)
8.2.4
8.2.5
8.2.6
8.2.7
8.2.8
8.2.9
Enable high signal valid
VEN = 16V
VEN = 0.5V
hysteresis
1) Not subject to production test, specified by design.
Data sheet
20
Rev. 1.0.1, 2013-04-15
TLF51801ELV
Application Information
9
Application Information
Note: The following information is given as a hint for the implementation of the device only and shall not be
regarded as a description or warranty of a certain functionality, condition or quality of the device.
9.1
Application Diagram
CIVCC
DBOOT
V_S
CIN1
CIN2
R sense
IVCC
CIN
*
sensehigh
VS
senselow
LDO
V_ls
EN
EN
BTS
Enable
CBTS
GND
Softstart
UG
Tem p .S D
SYNC/ FREQ
HIGH
Osc
Sync
L1
BUO
Step Down
COMP
V_CC
V_ls
Regulator
LOW
LG
D1
FB
COUT1
COUT2
PGND
TLF 51801ELV
GND
R1
RF
GND
CL
RFREQ
CCF
Parts in grey are optional
R2
CF
* Parts suggested for suppresion of EME
Figure 12
Application Diagram (Current limitation with Rdson-configuration)
Note: This is a very simplified example of an application circuit. The function must be verified in the real application
CIVCC
DBOOT
V_S
CIN1
CIN2
CIN
R sense
IVCC
sensehigh
R shunt
*
VS
senselow
LDO
V_ls
EN
EN
BTS
Enable
CBTS
GND
Softstart
UG
Temp .S D
SYNC / FREQ
HIGH
Osc
Sync
L1
BUO
Step Down
COMP
Regulator
V_CC
V_ls
LG
LOW
D1
FB
COUT1
COUT2
PGND
TLF 51801ELV
GND
RF
R1
GND
CL
RFREQ
CCF
CF
Parts in grey are optional
R2
* Parts suggested for suppresion of EME
Figure 13
Application Diagram (Current limitation with Shunt-configuration)
Note: This is a very simplified example of an application circuit. The function must be verified in the real application
Data sheet
21
Rev. 1.0.1, 2013-04-15
TLF51801ELV
Application Information
Ref
L1
LOW, HIGH
COUT1, COUT2
Value
5.6μH
N-ch, 60 V, 12 mΩ
100μF - 10mΩ ESR
Manufacturer
Coilcraft
Infineon
Rubycon
Part number
MSS1278T-562ML_
IPD50N06S4L-12
6SW100M
Type
Inductor
Transistor
Capacitor, Poly Al, 6.3V
Qty
1
2
2
CIN2
22μF
Kemet
C2220C226M5R2CTU
Capacitor, X7R, 50V
1
CIN1
RFREQ
470μF
20kΩ
Panasonic
Panasonic
EEEFK1H471AM
ERJ3EKF2002V
Capacitor, Al, 50V
Resistor, ±1%, 0.1W
1
1
R1
100kΩ
Panasonic
ERJ3EKF1003V
Resistor, ±1%, 0.1W
1
R2
27.3kΩ
Panasonic
ERJ3EKF2742V
Resistor, ±1%, 0.1W
1
RF
6.65kΩ
Panasonic
ERJ3EKF6651V
Resistor, ±1%, 0.1W
1
Rsense
1.1kΩ
Panasonic
ERJ3EKF1101V
Resistor, ±1%, 0.1W
1
Rshunt
10mΩ
Vishay Dale
WSL3637R0100FEB
Resistor, ±1%, 3W
1
CCF
12pF
Kemet
C0603C120J5GACTU
Capacitor, C0G
1
CL
120pF
Kemet
C0603C121J5GACTU
Capacitor, C0G
1
CF
15nF
Kemet
C0603C153K5RACTU
Capacitor, X7R, 50V
1
CIVCC
1μF
Kemet
C1206C105K4RACTU
Capacitor, X7R, 16V
1
CIN
1μF
Kemet
C1206C105K5RACTU
Capacitor, X7R, 50V
1
CBTS
270nF
Kemet
C1206C273K5RACTU
Capacitor, X7R, 50V
1
Figure 14
Data sheet
Bill of Material for Application Diagram
22
Rev. 1.0.1, 2013-04-15
TLF51801ELV
Performance Graphs
10
Performance Graphs
Typical Performance Characteristics
Efficiency and Power Losses
versus Load Current
Efficiency versus Load Current
6
100
97
T = 25°C; f = 300kHz
T = 25°C; f = 300kHz
VS = 12V; RDS,on-Config
96
5
90
95
4
70
3
PLOSS @ VS = 24V
93
VS = 24V; RDS,on-Config
92
2
60
VS = 12V; Shunt-Config
94
EFFICIENCY (%)
80
POWER LOSSES (W)
EFFICIENCY (%)
VS = 12V
VS = 24V
91
VS = 24V; Shunt-Config
PLOSS @ VS = 12V
90
1
50
89
0
40
0,1
1
LOAD CURRENT (A)
88
10
1
10
LOAD CURRENT (A)
Efficiency versus Load Current
VCC versus Temperature
98
5,70
f = 300kHz; VS = 12V
ICC = 5A; VS = 12V
97
T = -40°C
96
5,65
T = 25°C
94
VCC (V)
EFFICIENCY (%)
95
5,60
93
T = 150°C
92
5,55
91
90
5,50
89
1
-50
10
LOAD CURRENT (A)
Data sheet
23
-30
-10
10
30
50
70
TEMPERATURE (°C)
90
110
130
150
Rev. 1.0.1, 2013-04-15
TLF51801ELV
Performance Graphs
Typical Performance Characteristics
IVCC versus Temperature
IVCC Undervoltage versus Temperature
5,75
4,30
VS = 12V
5,65
4,25
5,55
IVCC UNDERVOTAGE (V)
4,20
IVCC (V)
5,45
IIVCC = 50mA
5,35
4,15
4,10
5,25
4,05
5,15
5,05
4,00
-50
-30
-10
10
30
50
70
TEMPERATURE (°C)
90
110
130
150
IVCC versus VS
-50
-30
-10
10
30
50
70
TEMPERATURE (°C)
90
110
130
150
Bootstrap Diode drop versus Temperature
5,75
1,1
T = 20°C
5,65
1,0
5,55
IBTS = 50mA
0,9
IVCC (V)
IVCC-BTS (V)
5,45
5,35
IBTS = 20mA
0,8
IBTS = 10mA
IIVCC = 50mA
0,7
5,25
0,6
5,15
0,5
5,05
0
5
Data sheet
10
15
20
25
VS (V)
30
35
40
45
-50
50
24
-25
0
25
50
75
TEMPERATURE (°C)
100
125
150
Rev. 1.0.1, 2013-04-15
TLF51801ELV
Performance Graphs
Typical Performance Characteristics
Load Regulation
VS = 12 V
Line Regulation
ICC = 5 A
5,70
5,70
VS = 12V
Temperature forced for the entire application
ICC = 5A
Temperature forced for the entire application
5,65
5,65
150°C
VCC (V)
VCC (V)
150°C
5,60
5,60
25°C
25°C
-40°C
5,55
5,55
-40°C
5,50
5,50
0
1
Data sheet
2
3
4
5
LOAD (A)
6
7
8
9
5
10
10
15
20
25
30
35
40
VS (V)
25
Rev. 1.0.1, 2013-04-15
TLF51801ELV
Performance Graphs
Load Step
VS = 12 V
VCC = 5.6 V
ICC = 5 A
ICC = 0 A
Line Step
ICC = 5 A
VCC = 5.6 V
VS = 24 V
VS = 12 V
Data sheet
26
Rev. 1.0.1, 2013-04-15
TLF51801ELV
Package Outlines
11
Package Outlines
0.19 +0.06
0.08 C
0.15 M C A-B D 14x
0.64 ±0.25
1
8
1
7
0.2
M
D 8x
Bottom View
3 ±0.2
A
14
6 ±0.2
D
Exposed
Diepad
B
0.1 C A-B 2x
14
7
8
2.65 ±0.2
0.25 ±0.05 2)
0.1 C D
8˚ MAX.
C
0.65
3.9 ±0.11)
1.7 MAX.
Stand Off
(1.45)
0 ... 0.1
0.35 x 45˚
4.9 ±0.11)
Index Marking
1) Does not include plastic or metal protrusion of 0.15 max. per side
2) Does not include dambar protrusion
PG-SSOP-14-1,-2,-3-PO V02
Figure 15
Package Drawing
Green Product (RoHS compliant)
To meet the world-wide customer requirements for environmentally friendly products and to be compliant with
government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e
Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).
For further package information, please visit our website:
http://www.infineon.com/packages.
Data sheet
26
Dimensions in mm
Rev. 1.0.1, 2013-04-15
TLF51801ELV
Revision History
12
Version
Revision History
Date
Changes
Rev 1.0.1 2013-04-15 Page 21: Editorial change
Rev 1.0
Data sheet
2013-02-25 Initial data sheet
27
Rev. 1.0.1, 2013-04-15
Edition 2013-04-15
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2013 Infineon Technologies AG
All Rights Reserved.
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties
and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights
of any third party.
Information
For further information on technology, delivery terms and conditions and prices, please contact the nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements, components may contain dangerous substances. For information on the types in
question, please contact the nearest Infineon Technologies Office.
Infineon Technologies components may be used in life-support devices or systems only with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
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