74F1071

74F1071 18-Bit Undershoot/Overshoot Clamp October 1994 Revised March 2005 74F1071 18-Bit Undershoot/Overshoot Clamp and ESD Protection Device General Description The 74F1071 is an 18-bit undershoot/overshoot clamp which is designed to limit bus voltages and also to protect more sensitive devices from electrical overstress due to electrostatic discharge (ESD). The inputs of the device aggressively clamp voltage excursions nominally at 0.5V below and 7V above ground. Features s 18-bit array structure in 20-pin package s FAST£ Bipolar voltage clamping action s Dual center pin grounds for min inductance s Robust design for ESD protection s Low input capacitance s Optimum voltage clamping for 5V CMOS/TTL applications Ordering Code: Order Number 74F1071SC 74F1071SCX_NL (Note 1) 74F1071MSA 74F1071MSAX_NL (Note 1) 74F1071MTC 74F1071MTCX_NL (Note 1) Package Number M20B M20B MSA20 MSA20 MTC20 MTC20 Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Pb-Free 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide Pb-Free 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Pb-Free 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Note 1: “_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only. Connection Diagram Note: Simplified Component Representation FAST£ is a registered trademark of Fairchild Semiconductor Corporation. © 2005 Fairchild Semiconductor Corporation DS011685 www.fairchildsemi.com 74F1071 Absolute Maximum Ratings(Note 2) Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias Input Voltage (Note 3) Input Current (Note 3) ESD (Note 4) Human Body Model (MIL-STD-883D method 3015.7) IEC 801-2 Machine Model (EIAJIC-121-1981) DC Latchup Source Current (JEDEC Method 17) Package Power Dissipation @70qC SOIC Package 800 mW 65qC to 150qC 65qC to 125qC 65qC to 150qC 0.5V to 6V 200 mA to 50 mA Recommended Operating Conditions Free Air Ambient Temperature Reverse Bias Voltage Thermal Resistance (TJA in Free Air) SOIC Package SSOP Package 100qC/W 110qC/W 0qC to 70qC 0V to 5.25 VDC r10 kV r6 kV r2 kV r500 mA Note 2: Absolute maximum ratings are DC values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 3: Voltage ratings may be exceeded if current ratings and junction temperature and power consumption ratings are not exceeded. Note 4: ESD Rating for Direct contact discharge using ESD Simulation Tester. Higher rating may be realized in the actual application. DC Electrical Characteristics Symbol IIH VZ VF ICT CIN Parameter Input HIGH Current Reverse Voltage Forward Voltage Adjacent Input Crosstalk Input Capacitance (small signal @ 1 MHz) 25 13 6.6 TA Min 25qC Typ 1.5 3 6.9 7.1 Max 10 20 7.2 7.5 TA 0qC to 70qC Max 50 100 Min Units Conditions VIN VIN IZ IZ IF IF 5.25V; Untested Input @ GND 5.5V; Untested Input @ GND 1 mA; Untested Inputs @ GND 50 mA; Untested Inputs @ GND PA V V % pF 5.9 7.7 8.0 0.3 0.5 0.6 1.1 0.9 1.5 3 0.3 0.5 0.9 1.5 18 mA; Untested Inputs @ 5V 200 mA; Untested Inputs @ 5V 0 VDC 5 VDC VBIAS VBIAS www.fairchildsemi.com 2 74F1071 DC Electrical Characteristics Typical Forward and Reverse V/I Characteristics Typical Reverse Conduction Characteristics Typical Forward Conduction Characteristics ESD Network Human Body Model IEC 801-2 CZ 100 pF 150 pF RZ 1500: 330: Simulated ESD Voltage Clamping Test Circuit 3 www.fairchildsemi.com 74F1071 DC Electrical Characteristics Unclamped + 1 KV ESD Voltage Waveform (IEC801-2 Network) (Continued) Clamped + 1 KV ESD Voltage Waveform (IEC801-2 Network) Unclamped - 1 KV ESD Voltage Waveform (IEC801-2 Network) Clamped - 1 KV ESD Voltage Waveform (IEC801-2 Network) Typical Application 74F1071 ESD Protection of ASIC on User Port www.fairchildsemi.com 4 74F1071 Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide Package Number MSA20 5 www.fairchildsemi.com 74F1071 18-Bit Undershoot/Overshoot Clamp Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 6 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com