74F1071MTC

74F1071 18-Bit Undershoot/Overshoot Clamp and ESD Protection Device Features General Description ■ 18-bit array structure in 20-pin package The 74F1071 is an 18-bit undershoot/overshoot clamp which is designed to limit bus voltages and also to protect more sensitive devices from electrical overstress due to electrostatic discharge (ESD). The inputs of the device aggressively clamp voltage excursions nominally at 0.5V below and 7V above ground. ■ FAST Bipolar voltage clamping action ■ Dual center pin grounds for min inductance ■ Robust design for ESD protection ■ Low input capacitance ■ Optimum voltage clamping for 5V CMOS/TTL applications Ordering Information Package Number Package Description M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 74F1071MSA MSA20 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide 74F1071MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Order Number 74F1071SC Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number. All packages are lead free per JEDEC: J-STD-020B standard. Connection Diagram Note: Simplified Component Representation ©1994 Fairchild Semiconductor Corporation 74F1071 Rev. 1.4.0 www.fairchildsemi.com 74F1071 — 18-Bit Undershoot/Overshoot Clamp and ESD Protection Device January 2008 Symbol TSTG Parameter Rating Storage Temperature –65°C to +150°C TA Ambient Temperature Under Bias –65°C to +125°C TJ Junction Temperature Under Bias –65°C to +150°C VI Input Voltage(1) –0.5V to +6V II Input Current(1) –200mA to +50mA ESD(2) Human Body Model (MIL-STD-883D method 3015.7) ±10kV IEC 801-2 ±6kV Machine Model (EIAJIC-121-1981) ±2kV DC Latchup Source Current (JEDEC Method 17) ±500mA Package Power Dissipation @ +70°C SOIC Package 800mW Notes: 1. Voltage ratings may be exceeded if current ratings and junction temperature and power consumption ratings are not exceeded. 2. ESD Rating for Direct contact discharge using ESD Simulation Tester. Higher rating may be realized in the actual application. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Symbol Parameter TA Free Air Ambient Temperature VZ Reverse Bias Voltage θJA Thermal Resistance (in Free Air) Rating 0°C to +70°C 0V to 5.25 VDC SOIC Package 100°C/W SSOP Package 110°C/W ©1994 Fairchild Semiconductor Corporation 74F1071 Rev. 1.4.0 www.fairchildsemi.com 2 74F1071 — 18-Bit Undershoot/Overshoot Clamp and ESD Protection Device Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. TA = +25°C Symbol IIH VZ Parameter Input HIGH Current Reverse Voltage Conditions Min. Typ. Max. VIN = 5.25V; Untested Input @ GND 1.5 VIN = 5.5V; Untested Input @ GND IZ = 1mA; Untested Inputs @ GND 6.6 IZ = 50mA; Untested Inputs @ GND VF Forward Voltage Min. Max. Units 10 50 µA 3 20 100 6.9 7.2 7.1 7.5 5.9 7.7 –0.3 –0.6 –0.9 –0.3 –0.9 IF = –200mA; Untested Inputs @ 5V –0.5 –1.1 –1.5 –0.5 –1.5 Adjacent Input Crosstalk CIN Input Capacitance VBIAS = 0 VDC (small signal @ 1MHz) V BIAS = 5 VDC 3 25 V 8.0 IF = –18mA; Untested Inputs @ 5V ICT ©1994 Fairchild Semiconductor Corporation 74F1071 Rev. 1.4.0 TA = 0°C to +70°C V % pF 13 www.fairchildsemi.com 3 74F1071 — 18-Bit Undershoot/Overshoot Clamp and ESD Protection Device DC Electrical Characteristics Typical Forward and Reverse V/I Characteristics Typical Reverse Conduction Characteristics ESD Network CZ RZ Human Body Model 100pF 1500Ω IEC 801-2 150pF 330Ω ©1994 Fairchild Semiconductor Corporation 74F1071 Rev. 1.4.0 Typical Forward Conduction Characteristics Simulated ESD Voltage Clamping Test Circuit www.fairchildsemi.com 4 74F1071 — 18-Bit Undershoot/Overshoot Clamp and ESD Protection Device DC Electrical Characteristics Unclamped +1kV ESD Voltage Waveform (IEC801-2 Network) Clamped +1kV ESD Voltage Waveform (IEC801-2 Network) Unclamped -1kV ESD Voltage Waveform (IEC801-2 Network) Clamped -1kV ESD Voltage Waveform (IEC801-2 Network) Typical Application 74F1071 ESD Protection of ASIC on User Port ©1994 Fairchild Semiconductor Corporation 74F1071 Rev. 1.4.0 www.fairchildsemi.com 5 74F1071 — 18-Bit Undershoot/Overshoot Clamp and ESD Protection Device DC Electrical Characteristics (Continued) 13.00 12.60 A 11.43 20 11 B 9.50 10.65 7.60 10.00 7.40 2.25 1 10 0.51 0.35 PIN ONE INDICATOR 0.25 M 0.65 1.27 1.27 C B A LAND PATTERN RECOMMENDATION 2.65 MAX SEE DETAIL A 0.33 0.20 C 0.75 0.25 X 45° SEATING PLANE NOTES: UNLESS OTHERWISE SPECIFIED (R0.10) GAGE PLANE (R0.10) 0.10 C 0.30 0.10 0.25 8° 0° A) THIS PACKAGE CONFORMS TO JEDEC MS-013, VARIATION AC, ISSUE E B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE MOLD FLASH OR BURRS. D) CONFORMS TO ASME Y14.5M-1994 1.27 0.40 SEATING PLANE E) LANDPATTERN STANDARD: SOIC127P1030X265-20L (1.40) DETAIL A F) DRAWING FILENAME: MKT-M20BREV3 SCALE: 2:1 Figure 1. 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ ©1994 Fairchild Semiconductor Corporation 74F1071 Rev. 1.4.0 www.fairchildsemi.com 6 74F1071 — 18-Bit Undershoot/Overshoot Clamp and ESD Protection Device Physical Dimensions 74F1071 — 18-Bit Undershoot/Overshoot Clamp and ESD Protection Device Physical Dimensions (Continued) Figure 2. 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ ©1994 Fairchild Semiconductor Corporation 74F1071 Rev. 1.4.0 www.fairchildsemi.com 7 74F1071 — 18-Bit Undershoot/Overshoot Clamp and ESD Protection Device Physical Dimensions (Continued) Figure 3. 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ ©1994 Fairchild Semiconductor Corporation 74F1071 Rev. 1.4.0 www.fairchildsemi.com 8 ACEx® Build it Now™ CorePLUS™ CROSSVOLT™ CTL™ Current Transfer Logic™ EcoSPARK® EZSWITCH™ * ™ PDP-SPM™ SyncFET™ ® Power220® ® Power247 The Power Franchise® POWEREDGE® Power-SPM™ PowerTrench® TinyBoost™ Programmable Active Droop™ TinyBuck™ ® QFET TinyLogic® QS™ TINYOPTO™ QT Optoelectronics™ TinyPower™ ® Quiet Series™ TinyPWM™ RapidConfigure™ TinyWire™ Fairchild® SMART START™ Fairchild Semiconductor® µSerDes™ ® SPM FACT Quiet Series™ UHC® STEALTH™ FACT® Ultra FRFET™ SuperFET™ FAST® UniFET™ SuperSOT™-3 FastvCore™ VCX™ ® ®* SuperSOT™-6 FlashWriter SuperSOT™-8 * EZSWITCH™ and FlashWriter® are trademarks of System General Corporation, used under license by Fairchild Semiconductor. FPS™ FRFET® Global Power ResourceSM Green FPS™ Green FPS™ e-Series™ GTO™ i-Lo™ IntelliMAX™ ISOPLANAR™ MegaBuck™ MICROCOUPLER™ MicroFET™ MicroPak™ MillerDrive™ Motion-SPM™ OPTOLOGIC® OPTOPLANAR® DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. A critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Formative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production This datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve the design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild Semiconductor. The datasheet is printed for reference information only. Rev. I32 ©1994 Fairchild Semiconductor Corporation 74F1071 Rev. 1.4.0 www.fairchildsemi.com 9 74F1071 — 18-Bit Undershoot/Overshoot Clamp and ESD Protection Device TRADEMARKS The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries, and is not intended to be an exhaustive list of all such trademarks.