74LCXH32245G

74LCXH32245 Low Voltage 32-Bit Bidirectional Transceiver with 5V Tolerant Inputs and Outputs with Bushold April 2002 Revised August 2003 74LCXH32245 Low Voltage 32-Bit Bidirectional Transceiver with 5V Tolerant Inputs and Outputs with Bushold General Description The LCXH32245 contains thirty-two non-inverting bidirectional buffers with 3-STATE outputs and is intended for bus oriented applications. The device is designed for low voltage (2.5V or 3.3V) VCC applications with capability of interfacing to a 5V signal environment. The device is byte controlled. Each byte has separate control inputs which could be shorted together for full 32-bit operation. The T/R inputs determine the direction of data flow through the device. The OE inputs disable both the A and B ports by placing them in a high impedance state. The LCXH32245 data inputs include bushold, eliminating the need for external pull-up/down resistors to hold unused inputs. The LCXH32245 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining CMOS low power dissipation. Features s 5V tolerant inputs and outputs s 2.3V to 3.6V VCC specifications provided s 4.5 ns tPD max (VCC = 3.3V), 20 µA ICC max s Power-off high impedance inputs and outputs s Bushold on inputs eliminates the need for external pull-up/down resistors s Supports live insertion/withdrawal (Note 1) s ±24 mA output drive (VCC = 3.0V) s Uses patented noise/EMI reduction circuitry s Latch-up performance exceeds 500 mA s ESD performance: Human body model > 2000V Machine model > 200V s Packaged in plastic Fine-Pitch Ball Grid Array (FBGA) Note 1: To ensure the high-impedance state during power-up or down, OE should be tied to VCC through a pull-up resistor: the minimum value or the resistor is determined by the current-sourcing capability of the driver. Ordering Code: Order Number 74LCXH32245G (Note 2) (Note 3) Package Number BGA96A Package Description 96-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide Note 2: Ordering Code “G” indicates Trays. Note 3: D evices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbol © 2003 Fairchild Semiconductor Corporation DS500727 www.fairchildsemi.com 74LCXH32245 Connection Diagram Pin Descriptions Pin Names OEn T/Rn A0–A31 B0–B31 Description Output Enable Input (Active LOW) Transmit/Receive Input Side A Inputs/3-STATE Outputs Side B Inputs/3-STATE Outputs FBGA Pin Assignments 1 A B C D E F G (Top Thru View) H J K L M N P R T B1 B3 B5 B7 B9 B11 B13 B14 B17 B19 B21 B23 B25 B27 B29 B30 2 B0 B2 B4 B6 B8 B10 B12 B15 B16 B18 B20 B22 B24 B26 B28 B31 3 T/R1 GND VCC1 GND GND VCC1 GND T/R2 T/R3 GND VCC2 GND GND VCC2 GND T/R4 4 OE1 GND VCC1 GND GND VCC1 GND OE2 OE3 GND VCC2 GND GND VCC2 GND OE4 5 A0 A2 A4 A6 A8 A10 A12 A15 A16 A18 A20 A22 A24 A26 A28 A31 6 A1 A3 A5 A7 A9 A11 A13 A14 A17 A19 A21 A23 A25 A27 A29 A30 Truth Tables Inputs OE1 L L H Inputs OE2 L L H T/R2 L H X Outputs Bus B8–B15 Data to Bus A8–A15 Bus A8–A15 Data to Bus B8–B15 HIGH–Z State on A8–A15,B8–B15 T/R1 L H X Outputs Bus B0–B7 Data to Bus A0–A7 Bus A0–A7 Data to Bus B0–B7 HIGH–Z State on A0–A7,B0–B7 Inputs OE3 L L H Inputs OE4 L L H T/R4 L H X Outputs Bus B24–B31 Data to Bus A24–A31 Bus B24–A31 Data to Bus B24–B31 HIGH–Z State on A24–A31,B24–B31 T/R3 L H X Outputs Bus B16–B23 Data to Bus A16–A23 Bus A16–A23 Data to Bus B16–B23 HIGH–Z State on A16–A23,B16–B23 H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance www.fairchildsemi.com 2 74LCXH32245 Logic Diagrams Note: Please note that these diagrams are provided only for the understanding of logic operations and should not be used to estimate propagation delays. 3 www.fairchildsemi.com 74LCXH32245 Absolute Maximum Ratings(Note 4) Symbol VCC VI VO IIK IOK IO ICC IGND TSTG Parameter Supply Voltage T/R, OE I/O Ports DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Source/Sink Current DC Supply Current per Supply Pin DC Ground Current per Ground Pin Storage Temperature Value Conditions Units V V Output in 3-STATE Output in HIGH or LOW State (Note 5) VI < GND VO < GND VO > VCC V mA mA mA mA mA −0.5 to +7.0 −0.5 to +7.0 −0.5 to VCC + 0.5 −0.5 to +7.0 −0.5 to VCC + 0.5 −50 −50 +50 ±50 ±100 ±100 −65 to +150 °C Recommended Operating Conditions (Note 6) Symbol VCC VI VO IOH/IOL Supply Voltage Input Voltage Output Voltage Output Current HIGH or LOW State 3-STATE VCC = 3.0V − 3.6V VCC = 2.7V − 3.0V VCC = 2.3V − 2.7V TA Free-Air Operating Temperature Input Edge Rate, VIN = 0.8V–2.0V, VCC = 3.0V Parameter Operating Data Retention Min 2.0 1.5 0 0 0 Max 3.6 3.6 VCC VCC 5.5 Units V V V ±24 ±12 ±8 −40 0 85 10 mA °C ns/V ∆t/∆V Note 4: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. Note 5: IO Absolute Maximum Rating must be observed. Note 6: Floating or unused control inputs must be HIGH or LOW. DC Electrical Characteristics Symbol VIH VIL VOH Parameter HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Voltage IOH = −100 µA IOH = −8 mA IOH = −12 mA IOH = −18 mA IOH = −24 mA VOL LOW Level Output Voltage IOL = 100 µA IOL = 8 mA IOL = 12 mA IOL = 16 mA IOL = 24 mA Conditions VCC (V) 2.3 − 2.7 2.7 − 3.6 2.3 − 2.7 2.7 − 3.6 2.3 − 3.6 2.3 2.7 3.0 3.0 2.3 − 3.6 2.3 2.7 3.0 3.0 VCC − 0.2 1.8 2.2 2.4 2.2 0.2 0.6 0.4 0.4 0.55 V V TA = −40°C to +85°C Min 1.7 2.0 0.7 0.8 Max Units V V www.fairchildsemi.com 4 74LCXH32245 DC Electrical Characteristics Symbol II II(HOLD) Parameter Input Leakage Current Bushold Input Minimum Drive Hold Current (Continued) VCC (V) 2.3 − 3.6 2.3 3.0 2.7 3.6 2.3 − 3.6 0 2.3–3.6 2.3–3.6 2.3–3.6 45 -45 75 −75 300 −300 450 −450 ±5.0 10 20 ±20 500 µA µA µA µA µA µA TA = −40°C to +85°C Min Max ±5.0 Conditions 0 ≤ VI ≤ 5.5V VIN = 0.7V VIN = 1.7V VIN = 0.8V VIN = 2.0V Units II(OD) Bushold Input Over-Drive Current to Change State (Note 7) (Note 8) (Note 7) (Note 8) IOZ IOFF ICC ∆ICC 3-STATE I/O Leakage Power-Off Leakage Current Quiescent Supply Current Increase in ICC per Input 0 ≤ VO ≤ 5.5V VI = V IH or VIL VI or VO = 5.5V VI = V CC or GND 3.6V ≤ VI, VO ≤ 5.5V (Note 9) VIH = VCC −0.6V Note 7: An external driver must source at least the specified current to switch from LOW-to-HIGH. Note 8: An external driver must sink at least the specified current to switch from HIGH-to-LOW. Note 9: Outputs disabled or 3-STATE only. AC Electrical Characteristics TA = −40°C to +85°C, RL = 500Ω Symbol Parameter VCC = 3.3V ± 0.3V CL = 50 pF Min tPHL tPLH tPZL tPZH tPLZ tPHZ Output Disable Time Propagation Delay An to Bn or Bn to An Output Enable Time 1.0 1.0 1.0 1.0 1.0 1.0 Max 4.5 4.5 6.5 6.5 6.4 6.4 VCC = 2.7V CL = 50 pF Min 1.0 1.0 1.0 1.0 1.0 1.0 Max 5.2 5.2 7.2 7.2 6.9 6.9 VCC = 2.5V ± 0.2V CL = 30 pF Min 1.0 1.0 1.0 1.0 1.0 1.0 Max 5.4 5.4 8.5 8.5 7.7 7.7 ns ns ns Units Dynamic Switching Characteristics Symbol VOLP VOLV Parameter Quiet Output Dynamic Peak VOL Quiet Output Dynamic Valley VOL Conditions CL = 50 pF, VIH = 3.3V, VIL = 0V CL = 30 pF, VIH = 2.5V, VIL = 0V CL = 50 pF, VIH = 3.3V, VIL = 0V CL = 30 pF, VIH = 2.5V, VIL = 0V VCC (V) 3.3 2.5 3.3 2.5 TA = 25°C Typical 0.8 0.6 −0.8 −0.6 Units V V Capacitance Symbol CIN CI/O CPD Input Capacitance Input/Output Capacitance Power Dissipation Capacitance Parameter Conditions VCC = Open, VI = 0V or VCC VCC = 3.3V, VI = 0V or VCC VCC = 3.3V, VI = 0V or VCC, f = 10 MHz Typical 7 8 20 Units pF pF pF 5 www.fairchildsemi.com 74LCXH32245 AC LOADING and WAVEFORMS Generic for LCX Family FIGURE 1. AC Test Circuit (CL includes probe and jig capacitance) Test tPLH, tPHL tPZL, tPLZ tPZH , tPHZ Switch Open 6V at VCC = 3.3 ± 0.3V, and 2.7V VCC x 2 at VCC = 2.5 ± 0.2V GND Waveform for Inverting and Non-Inverting Functions 3-STATE Output High Enable and Disable Times for Logic Propagation Delay. Pulse Width and trec Waveforms Setup Time, Hold Time and Recovery Time for Logic 3-STATE Output Low Enable and Disable Times for Logic FIGURE 2. Waveforms (Input Characteristics; f =1MHz, tr = tf = 3ns) Symbol Vmi Vmo Vx Vy VCC 3.3V ± 0.3V 1.5V 1.5V VOL + 0.3V VOH − 0.3V 2.7V 1.5V 1.5V VOL + 0.3V VOH − 0.3V trise and tfall 2.5V ± 0.2V VCC/2 VCC/2 VOL + 0.15V VOH − 0.15V www.fairchildsemi.com 6 74LCXH32245 Schematic Diagram Generic for LCX Family 7 www.fairchildsemi.com 74LCXH32245 Low Voltage 32-Bit Bidirectional Transceiver with 5V Tolerant Inputs and Outputs with Bushold Physical Dimensions inches (millimeters) unless otherwise noted 96-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide Package Number BGA96A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 8 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com