74LVXZ161284MEA

74LVXZ161284 Low Voltage IEEE 161284 Translating Transceiver with Power-Up Protection May 2002 Revised May 2002 74LVXZ161284 Low Voltage IEEE 161284 Translating Transceiver with Power-Up Protection General Description The LVXZ161284 contains eight bidirectional data buffers and eleven control/status buffers to implement a full IEEE 1284 compliant interface. The device supports the IEEE 1284 standard and is intended to be used in an Extended Capabilities Port mode (ECP). The pinout allows for easy connection from the Peripheral (A-side) to the Host (cable side). Outputs on the cable side can be configured to be either open drain or high drive (± 14 mA) and are connected to a separate power supply pin (VCC-Cable) that allows these outputs to be driven by a higher supply voltage than the A-side. The pull-up and pull-down series termination resistance of these outputs on the cable side is optimized to drive an external cable. In addition, the C inputs and the B and Y outputs on the cable side contain internal pull-up resistors connected to the VCC-Cable supply to provide proper input termination and pull-ups for open drain output mode. Outputs on the Peripheral side are standard low-drive CMOS outputs designed to interface with 3V logic. The DIR input controls data flow on the A1–A8/B1–B8 transceiver pins. This device also has an added power-up protection feature which forces the Y outputs (Y9 - Y13) to a high state after power-on until one of the associated inputs (A9 - A13) goes HIGH. When an associated input (A9 - A13) goes HIGH, all Y outputs (Y9 - Y13) are activated. Features I Supports IEEE 1284 Level 1 and Level 2 signaling standards for bidirectional parallel communications between personal computers and printing peripherals I Translation capability allows outputs on the cable side to interface with 5V signals I All inputs have hysteresis to provide noise margin I B and Y output resistance optimized to drive external cable I B and Y outputs in high impedance mode during power down I C inputs and B, Y outputs on cable side have internal 1.4 kΩ pull-up resistors I Flow-through pin configuration allows easy interface between the “Peripheral and Host” I Replaces the function of two (2) 74ACT1284 devices I Power-up protection prevents errors when the printer is powered on but no valid signal is at the input pins (A9 - A13). Ordering Code Order Number 74LVXZ161284MEA 74LVXZ161284MEX 74LVXZ161284MTD 74LVXZ161284MTX Package Number MS48A MS48A MTD48 MTD48 Package Description 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide [RAIL] 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide [TAPE and REEL] 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide [RAIL] 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide [TAPE and REEL] © 2002 Fairchild Semiconductor Corporation DS500729 www.fairchildsemi.com 74LVXZ161284 Logic Symbol Connection Diagram Pin Descriptions Pin Names HD DIR A1–A8 B1–B8 A9–A13 Y9–Y13 A14–A17 C14–C17 PLHIN PLH HLHIN HLH Description High Drive Enable Input (Active HIGH) Direction Control Input Inputs or Outputs Inputs or Outputs Inputs Outputs Outputs Inputs Peripheral Logic HIGH Input Peripheral Logic HIGH Output Host Logic HIGH Input Host Logic HIGH Output Truth Table Inputs DIR L HD L B1–B8 Data to A1–A8, and A9–A13 Data to Y9–Y13 (Note 1) C14–C17 Data to A14–A17 PLH Open Drain Mode L H B1–B8 Data to A1–A8, and A9–A13 Data to Y9–Y13 C14–C17 Data to A14–A17 H L A1–A8 Data to B1–B8 (Note 2) A9–A13 Data to Y9–Y13 (Note 1) C14–C17 Data to A14–A17 PLH Open Drain Mode H H A1–A8 Data to B1–B8 A9–A13 Data to Y9–Y13 C14–C17 Data to A14–A17 Note 1: Y9–Y13 Open Drain Outputs with 1.4 kΩ pullups Note 2: B1–B8 Open Drain Outputs with 1.4 kΩ pullups Outputs www.fairchildsemi.com 2 74LVXZ161284 Logic Diagrams Input Detection Circuit FIGURE 1. Input Detection Circuit Timing 3 www.fairchildsemi.com 74LVXZ161284 Absolute Maximum Ratings(Note 3) Supply Voltage VCC VCC—Cable VCC—Cable Must Be ≥ VCC Input Voltage (VI)—(Note 4) A1–A13, PLHIN, DIR, HD B1–B8, C14–C17, HLHIN B1–B8, C14–C17, HLHIN Output Voltage (VO) A1–A8, A14–A17, HLH B1–B8, Y9–Y13, PLH B1–B8, Y9–Y13, PLH DC Output Current (IO) A1–A8, HLH B1–B8, Y9–Y13 PLH (Output LOW) PLH (Output HIGH) Input Diode Current (IIK)—(Note 4) DIR, HD, A9–A13, PLH, HLH, C14–C17 Output Diode Current (IOK) A1–A8, A14–A17, HLH B1–B8, Y9–Y13, PLH DC Continuous VCC or Ground Current Storage Temperature ESD Human Body Model Machine Model Charged Device Model 4000V 200V 2000V Recommended Operating Conditions Supply Voltage VCC VCC—Cable DC Input Voltage (VI) 3.0V to 3.6V 3.0V to 5.5V 0V to VCC 0V to 5.5V −0.5V to +4.6V −0.5V to +7.0V −0.5V to VCC + 0.5V −0.5V to +5.5V (DC) −2.0V to +7.0V* *40 ns Transient Open Drain Voltage (VO) Operating Temperature (TA) −40°C to +85°C −0.5V to VCC +0.5V −0.5V to +5.5V (DC) −2.0V to +7.0V* *40 ns Transient ±25 mA ±50 mA 84 mA −50 mA −20 mA ±50 mA −50 mA ±200 mA −65°C to +150°C Note 3: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Fairchild does not recommend operation outside the databook specifications. Note 4: Either voltage limit or current limit is sufficient to protect inputs. DC Electrical Characteristics Symbol VIK VIH Input Clamp Diode Voltage Minimum HIGH Level Input Voltage VIL Maximum LOW Level Input Voltage ∆VT Minimum Input Hysteresis VOH Minimum HIGH Level Output Voltage Bn, Yn Bn, Yn PLH An, Bn, PLHIN, DIR, HD Cn HLHIN An, Bn, PLHIN, DIR, HD Cn HLHIN An, Bn, PLHIN, DIR, HD Cn HLHIN An, HLH 3.0–3.6 3.0–3.6 3.0–3.6 3.0–3.6 3.0–3.6 3.0–3.6 3.3 3.3 3.3 3.0 3.0 3.0 3.0 3.15 3.0–5.5 3.0–5.5 3.0–5.5 3.0–5.5 3.0–5.5 3.0–5.5 5.0 5.0 5.0 3.0 3.0 3.0 4.5 3.15 2.0 2.3 2.6 0.8 0.8 1.6 0.4 0.8 0.2 2.8 2.4 2.0 2.23 3.1 2.0 2.3 2.6 0.8 0.8 1.6 0.4 0.8 0.2 2.8 2.4 2.0 2.23 3.1 V V VT+ – VT− VT+ – VT− VT+ – VT− IOH = −50 µA IOH = −4 mA IOH = −14 mA IOH = −14 mA IOH = −500 µA V V Parameter VCC (V) 3.0 VCC—Cable (V) 3.0 TA = 0°C to +70°C −1.2 TA = −40°C to +85°C −1.2 Units V Conditions Ii = −18 mA Guaranteed Limits www.fairchildsemi.com 4 74LVXZ161284 DC Electrical Characteristics Symbol VOL Maximum LOW Level Output Voltage Bn, Yn Bn, Yn PLH PLH RD Maximum Output Impedance Minimum Output Impedance RP Maximum Pull-Up Resistance Minimum Pull-Up Resistance IIH Maximum Input Current in HIGH State IIL Maximum Input Current in LOW State IOZH Maximum Output Disable Current (HIGH) IOZL Maximum Output Disable Current (LOW) IOZPU IOZPD IOFF IOFF IOFF—ICC Maximum Power-Up Disable Current Disable Current Power Down Output Leakage Power Down Input Leakage Power Down Leakage to VCC IOFF—ICC2 Power Down Leakage to VCC—Cable ICC Maximum Supply Current B1 - B8, Y9 - Y13, C14 - C17 B1 -B8, Y9 - Y13 C14 - C17 A9 - A13, PLHIN, HD, DIR, HLHIN C14 - C17 C14 -C17 A9 - A13, PLHIN, HD, DIR, HLHIN C14 - C17 C14 - C17 A1 - A 8 B1 - B8 B1 - B8 A1 - A8 B1 - B8 B1 - B8 Y9 - Y13 B1 - B8 B1 - B8 B1 - B8, Y9 - Y13, PLH C14–C17, HLHIN B1 - B8, Y9 - Y13 B1 - B8, Y9 -Y13 Parameter An, HLH (Continued) TA = 0°C to +70°C 0.2 0.4 0.8 0.77 0.85 0.8 60 55 30 35 1650 1650 1150 1150 1.0 50.0 100 −1.0 −3.5 −5.0 20 50 100 −20 −3.5 −5.0 350 −5 350 −5 100 100 250 250 45 70 TA = −40°C to +85°C 0.2 0.4 0.8 0.77 0.95 0.9 60 55 30 35 1650 1650 1150 1150 1.0 50.0 100 −1.0 −3.5 −5.0 20 50 100 −20 −3.5 −5.0 350 −5 350 −5 100 100 250 250 45 70 µA mA µA mA µA mA µA µA µA µA mA mA VO = 0.0V VO = 5.5V VO = 0.0V VO = 5.5V VO = 0.0V VO = 5.5V VI = 5.5V (Note 6) (Note 6) VI = VCC or GND VI = VCC or GND µA µA mA µA Ω Ω VI = 3.6V VI = 3.6V VI = 5.5V VI = 0.0V VI = 0.0V VO = 3.6V VO = 3.6V VO = 5.5V Ω (Note 5)(Note 7) V Units Conditions IOL = 50 µA IOL = 4 mA IOL = 14 mA IOL = 14 mA IOL = 84 mA IOL = 84 mA (Note 5)(Note 7) VCC (V) 3.0 3.0 3.0 3.0 3.0 3.0 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 0 to 1.5 (Note 8) 0 to 1.5 (Note 8) 0.0 0.0 0.0 0.0 3.6 3.6 VCC—Cable (V) 3.0 3.0 3.0 4.5 3.0 4.5 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.6 3.6 5.5 3.6 3.6 5.5 3.6 3.6 5.5 3.6 3.6 5.5 0 to 1.5 (Note 8) 0 to 1.5 (Note 8) 0.0 0.0 0.0 0.0 3.6 5.5 Guaranteed Limits Maximum Power-Down Y9 - Y13 Note 5: Output impedance is measured with the output active LOW and active HIGH (HD = HIGH). Note 6: Power-down leakage to VCC or VCC—Cable is tested by simultaneously forcing all pins on the cable-side (B1–B8, Y9–Y13, PLH, C14–C17 and HLHIN) to 5.5V and measuring the resulting ICC or ICC—Cable. Note 7: This parameter is guaranteed but not tested, characterized only. Note 8: C onnect all VCC pins and VCC-Cable pins when forcing voltage applied, DIR = HD = 0V. 5 www.fairchildsemi.com 74LVXZ161284 AC Electrical Characteristics TA = 0°C to +70°C Symbol Parameter VCC = 3.0V–3.6V VCC—Cable = 3.0V–5.5V Min tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tSKEW tPHL tPLH tPHL tPLH tPHZ tPLZ tPZH tPZL tPHZ tPLZ tpEN tpDIS tpEN–tpDIS tSLEW tPLH tPHL tr, tf tRISE and tFALL B1–B8 (Note 9), Y9–Y13 (Note 9) Note 9: Open Drain Note 10: tSKEW is measured for common edge output transitions and compares the measured propagation delay for a given path type: (i) A1–A8 to B1–B8, A9–A13 to Y9–Y13 (ii) B1–B8 to A1–A8 (iii) C14–C17 to A14–A17 Note 11: This parameter is guaranteed but not tested, characterized only. TA = −40°C to +85°C VCC = 3.0V–3.6V VCC—Cable = 3.0V–5.5V Min 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 Max 44.0 44.0 44.0 44.0 44.0 44.0 44.0 44.0 12.0 44.0 44.0 44.0 44.0 18.0 18.0 50.0 50.0 50.0 50.0 28.0 28.0 28.0 28.0 12.0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Figure 2 Figure 3 Figure 4 Figure 4 Figure 2 Figure 3 Figure 4 Figure 4 (Note 10) Figure 2 Figure 3 Figure 4 Figure 4 Figure 8 Figure 9 Figure 10 Figure 3 Figure 3 Units Figure Number Max 40.0 40.0 40.0 40.0 40.0 40.0 40.0 40.0 10.0 40.0 40.0 40.0 40.0 15.0 15.0 50.0 50.0 50.0 50.0 25.0 25.0 25.0 25.0 10.0 A1–A8 to B1–B8 A1–A8 to B1–B8 B1–B8 to A1–A8 B1–B8 to A1–A8 A9–A13 to Y9–Y13 A9–A13 to Y9–Y13 C14–C17 to A14–A17 C14–C17 to A14–A17 LH-LH or HL-HL PLHIN to PLH PLHIN to PLH HLHIN to HLH HLHIN to HLH Output Disable Time DIR to A1–A8 Output Enable Time DIR to A1–A8 Output Disable Time DIR to B1–B8 Output Enable Time HD to B1–B8, Y9–Y13 Output Disable Time HD to B1–B8, Y9–Y13 Output EnableOutput Disable Output Slew Rate B1–B8, Y9–Y13 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 0.05 0.05 0.40 0.40 120 120 0.05 0.05 0.40 0.40 120 120 V/ns Figure 6 Figure 5 Figure 7 (Note 11) ns Capacitance Symbol CIN CI/O (Note 12) Parameter Input Capacitance I/O Pin Capacitance Typ 3 5 Units pF pF VCC = 3.3V Conditions VCC = 0.0V (HD, DIR, A9–A13, C14–C17, PLHIN and HLHIN) Note 12: CI/O is measured at frequency = 1 MHz, per MIL-STD-883B, Method 3012 www.fairchildsemi.com 6 74LVXZ161284 AC Loading and Waveforms Pulse Generator for all pulses: Rate ≤1.0 MHz; ZO ≤ 50Ω; tf ≤ 2.5 ns, tr ≤ 2.5 ns. FIGURE 2. Port A to B and A to Y Propagation Delay Waveforms FIGURE 3. Port A to B and A to Y Output Waveforms FIGURE 4. Port B to A, C to A and HLHin to HLH Propagation Delay Waveforms 7 www.fairchildsemi.com 74LVXZ161284 AC Loading and Waveforms (Continued) FIGURE 5. Port A to B and A to Y HL Slew Test Load and Waveforms FIGURE 6. Port A to B and A to Y LH Slew Test Load and Waveforms www.fairchildsemi.com 8 74LVXZ161284 AC Loading and Waveforms (Continued) tr = Output Rise Time, Open Drain tf = Output Fall Time, Open Drain FIGURE 7. Ports A to B and A to Y Rise and Fall Test Load and Waveforms for Open Drain Outputs FIGURE 8. tPHZ and tPLZ Test Load and Waveforms, DIR to A1–A8 9 www.fairchildsemi.com 74LVXZ161284 AC Loading and Waveforms (Continued) FIGURE 9. tPZH and tPZL Test Load and Waveforms, DIR to A1–A8 FIGURE 10. tPHZ and tPLZ Test Load and Waveforms DIR to B1–B8 www.fairchildsemi.com 10 74LVXZ161284 Physical Dimensions inches (millimeters) unless otherwise noted 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide Package Number MS48A 11 www.fairchildsemi.com