74VCX16722

74VCX16722 Low Voltage 22-Bit Register with 3.6V Tolerant Inputs and Outputs February 1999 Revised January 2005 74VCX16722 Low Voltage 22-Bit Register with 3.6V Tolerant Inputs and Outputs General Description The VCX16722 low voltage 22-bit register contains twentytwo non-inverting D-type flip-flops with 3-STATE outputs and is intended for bus oriented applications. The design has been optimized for use with JEDEC compliant 200 pin DIMM modules. The 74VCX16722 is designed for low voltage (1.65V to 3.6V) VCC applications with I/O capability up to 3.6V. The 74VCX16722 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining low CMOS power dissipation. Features s 1.65V–3.6V VCC supply operation s 3.6V tolerant inputs and outputs s tPD (CLK to O n) 3.6ns max for 3.0V to 3.6V VCC 4.6ns max for 2.3V to 2.7V VCC 9.2ns max for 1.65V to 1.95V VCC s Power-down high impedance inputs and outputs s Supports live insertion/withdrawal (Note 1) s Meets JEDEC registered module specifications s Static Drive (IOH/IOL) ±24mA @ 3.0V ±18mA @ 2.3V ±6mA @ 1.65V s Latchup performance exceeds 300 mA s ESD performance: Human body model > 2000V Machine model >200V Note 1: To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pull-up resistor; the minimum value of the resistor is determined by the current sourcing capability of the driver. Ordering Code: Order Number 74VCX16722MTD Package Number MTD64 Package Description 64-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. © 2005 Fairchild Semiconductor Corporation DS500192 www.fairchildsemi.com 74VCX16722 Connection Diagram Pin Descriptions Pin Names OE CE CLK D0- D21 O0 - O21 Description Output Enable Input (Active LOW) Clock Enable Input (Active Low) Clock Input Data Inputs 3-STATE Outputs Truth Table CLK X X CE X H L L L OE H L L L L Dn X X L H X On Z On L H On ↑ ↑ L or H H = Logic HIGH L = Logic LOW X = Don’t Care, but not floating Z = High Impedance On = Previous On before LOW-to-HIGH Clock Transition ↑ = LOW-to-HIGH Clock Transition Functional Description The VCX16722 contains twenty-two D-type flip-flops with 3-STATE standard outputs. The twenty-two flip-flops will store the state of their individual D-type inputs that meet the setup and hold time requirements on the LOW-HIGH Clock (CLK) transition, when the Clock-Enable (CE) is LOW. The 3-STATE standard outputs are controlled by the Output-Enable (OE). When OE is HIGH, the standard outputs are in high impedance mode but this does not interfere with entering new data into the flip-flops. Logic Diagram www.fairchildsemi.com 2 74VCX16722 Absolute Maximum Ratings(Note 2) Supply Voltage (VCC) DC Input Voltage (VI) Output Voltage (VO) Outputs 3-STATE Outputs Active (Note 3) DC Input Diode Current (IIK) VI < 0V DC Output Diode Current (IOK) VO < 0 V VO > VCC DC Output Source/Sink Current (IOH/IOL) DC VCC or Ground Current per Supply Pin (ICC or Ground) Storage Temperature Range (TSTG) −0.5V to +4.6V −0.5V to +4.6V −0.5V to +4.6V −0.5V to VCC + 0.5V −50 mA −50 mA +50 mA ±50 mA ±100 mA −65°C to +150°C Recommended Operating Conditions (Note 4) Power Supply Operating Data Retention Only Input Voltage Output Voltage (VO) Output in Active States Output in 3-STATE Output Current in IOH/IOL VCC = 3.0V to 3.6V VCC = 2.3V to 2.7V VCC = 1.65V to 2.3V Free Air Operating Temperature (TA) Minimum Input Edge Rate (∆t/∆V) VIN = 0.8V to 2.0V, VCC = 3.0V 10 ns/V Note 2: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The Recommended Operating Conditions tables will define the conditions for actual device operation. Note 3: IO Absolute Maximum Rating must be observed. Note 4: Floating or unused pin (inputs or I/O's) must be held HIGH or LOW. 1.65V to 3.6V 1.2V to 3.6V −0.3V to 3.6V 0V to VCC 0V to 3.6V ±24 mA ±18 mA ±6 mA −40°C to +85°C DC Electrical Characteristics (2.7V < VCC ≤ 3.6V) Symbol VIH VIL VOH Parameter HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Voltage IOH = −100 µA IOH = −12 mA IOH = −18 mA IOH = −24 mA VOL LOW Level Output Voltage IOL = 100 µA IOL = 12 mA IOL = 18 mA IOL = 24 mA II IOZ IOFF ICC ∆ICC Input Leakage Current 3-STATE Output Leakage Power Off Leakage Current Quiescent Supply Current Increase in ICC per Input 0V ≤ VI ≤ 3.6V 0V ≤ VO ≤ 3.6V VI = V IH or VIL 0V ≤ (VI, VO) ≤ 3.6V VI = V CC or GND VCC ≤ (VI, VO) ≤ 3.6V (Note 5) VIH = VCC − 0.6V Note 5: Outputs disabled or 3-STATE only. Conditions VCC (V) 2.7–3.6 2.7–3.6 2.7–3.6 2.7 3.0 3.0 2.7–3.6 2.7 3.0 3.0 2.7–3.6 2.7–3.6 0 2.7–3.6 2.7–3.6 Min 2.0 Max Units V 0.8 VCC − 0.2 2.2 2.4 2.2 0.2 0.4 0.4 0.55 ±5.0 ±10 10 20 ±20 750 V V V µA µA µA µA µA 3 www.fairchildsemi.com 74VCX16722 DC Electrical Characteristics (2.3V ≤ VCC ≤ 2.7V) Symbol VIH VIL VOH Parameter HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Voltage IOH = −100 µA IOH = −6 mA IOH = −12 mA IOH = −18 mA VOL LOW Level Output Voltage IOL = 100 µA IOL = 12mA IOL = 18 mA II IOZ IOFF ICC Input Leakage Current 3-STATE Output Leakage Power Off Leakage Current Quiescent Supply Current 0 ≤ VI ≤ 3.6V 0 ≤ VO ≤ 3.6V VI = VIH or VIL 0 ≤ (VI, V O) ≤ 3.6V VI = VCC or GND VCC ≤ (VI, VO) ≤ 3.6V (Note 6) Note 6: Outputs disabled or 3-STATE only. Conditions VCC (V) 2.3–2.7 2.3–2.7 2.3–2.7 2.3 2.3 2.3 2.3–2.7 2.3 2.3 2.3–2.7 2.3–2.7 0 2.3–2.7 Min 1.6 Max Units V 0.7 VCC − 0.2 2.0 1.8 1.7 0.2 0.4 0.6 ±5.0 ±10 10 20 ±20 V V V µA µA µA µA DC Electrical Characteristics (1.65V ≤ VCC < 2.3V) Symbol VIH VIL VOH VOL II IOZ IOFF ICC Parameter HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Voltage LOW Level Output Voltage Input Leakage Current 3-STATE Output Leakage Power Off Leakage Current Quiescent Supply Current IOH = −100 µA IOH = −6 mA IOL = 100 µA IOL = 6mA 0 ≤ VI ≤ 3.6V 0 ≤ VO ≤ 3.6V VI = VIH or VIL 0 ≤ (VI, V O) ≤ 3.6V VI = VCC or GND VCC ≤ (VI, VO) ≤ 3.6V (Note 7) Note 7: Outputs disabled or 3-STATE only. Conditions VCC (V) 1.65 - 2.3 1.65 - 2.3 1.65 - 2.3 1.65 1.65 - 2.3 1.65 1.65 - 2.3 1.65 - 2.3 0 1.65 - 2.3 Min 0.65 × VCC Max Units V 0.35 × VCC VCC − 0.2 1.25 0.2 0.3 ±5.0 ±10 10 20 ±20 V V V µA µA µA µA www.fairchildsemi.com 4 74VCX16722 AC Electrical Characteristics (Note 8) TA = −40°C to +85°C, CL = 30 pF, RL = 500Ω Symbol Parameter VCC = 3.3V ± 0.3V Min fMAX tPHL, tPLH tPZL, tPZH tPLZ, tPHZ tS tH tW tOSHL tOSLH Maximum Clock Frequency Propagation Delay Clock to Bus Output Enable Time Output Disable Time Setup Time Hold Time Pulse Width Output to Output Skew (Note 9) 250 1.3 0.6 0.6 2.0 0.0 1.5 0.5 3.6 3.5 3.2 Max VCC = 2.5 ± 0.2V Min 200 1.5 0.8 0.8 2.0 0.0 1.5 0.5 4.6 4.5 4.2 Max VCC = 1.8 ± 0.15V Min 100 2.0 1.5 1.5 3.0 0.5 4.0 0.75 9.2 9.0 7.6 Max MHz ns ns ns ns ns ns ns Units Note 8: For CL= 50 pF, add approximately 300 ps to the AC maximum specification. Note 9: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). AC Electrical Characteristics Over Load (Note 10) TA = −0°C to +70°C, RL = 500Ω VCC = 3.3V ± 0.3V Symbol Parameter Min tPHL, tPLH tPZL, tPZH tPLZ, tPHZ tS tH tW Propagation Delay Clock to Bus Output Enable Time Output Disable Time Setup Time Hold Time Pulse Width 1.1 0.7 0.7 2.0 0.0 1.5 CL = 0 pF Max 2.5 2.4 2.1 Min 1.9 1.0 1.0 2.0 0.0 1.5 CL = 50 pF Max 3.9 3.8 3.5 ns ns ns ns ns ns Units Note 10: This parameter is guaranteed by characterization but not tested. Dynamic Switching Characteristics Symbol VOLP Parameter Quiet Output Dynamic Peak VOL Conditions CL = 30 pF, VIH = VCC, VIL = 0V VCC (V) 1.8 2.5 3.3 VOLV Quiet Output Dynamic Valley VOL CL = 30 pF, VIH = VCC, VIL = 0V 1.8 2.5 3.3 VOHV Quiet Output Dynamic Valley VOH CL = 30 pF, VIH = VCC, VIL = 0V 1.8 2.5 3.3 TA = +25°C Typical 0.25 0.6 0.8 −0.25 −0.6 −0.8 1.5 1.9 2.2 V V V Units 5 www.fairchildsemi.com 74VCX16722 Capacitance Symbol CIN CI/O CPD Parameter Input Capacitance Input/Output Capacitance Power Dissipation Capacitance Conditions VI = 0V or VCC, VCC = 1.8V, 2.5V, or 3.3V, VI = 0V, or VCC, VCC = 1.8V, 2.5V or 3.3V VI = 0V or VCC, f = 10 MHz, VCC = 1.8V, 2.5V or 3.3V TA = +25°C Typical 3.5 5.5 13 Units pF pF pF IOUT - VOUT Characteristics IOH versus VOH FIGURE 1. Characteristics for Output - Pull Up Driver IOL versus VOL FIGURE 2. Characteristics for Output - Pull Down Driver www.fairchildsemi.com 6 74VCX16722 AC Loading and Waveforms FIGURE 3. AC Test Circuit TEST tPLH, tPHL tPZL, tPLZ tPZH, tPHZ SWITCH Open 6V at VCC = 3.3 ± 0.3V; VCC x 2 at VCC = 2.5 ± 0.2V; 1.8V to ± 0.15V GND FIGURE 4. Waveform for Inverting and Non-inverting Functions tr = tf ≤ 2.0ns, 10% to 90% FIGURE 5. 3-STATE Output High Enable and Disable Times for Low Voltage Logic tr = tf ≤ 2.0ns, 10% to 90% FIGURE 6. 3-STATE Output Low Enable and Disable Times for Low Voltage Logic tr = tf ≤ 2.0ns, 10% to 90% Symbol Vmi Vmo Vx Vy VCC 3.3V ± 0.3V 1.5V 1.5V VOL + 0.3V VOH − 0.3V 2.5V ± 0.2V VCC/2 VCC/2 VOL + 0.15V VOH − 0.15V 1.8 ± 0.15V VCC/2 VCC/2 VOL + 0.15V VOH − 0.15V 7 www.fairchildsemi.com 74VCX16722 Low Voltage 22-Bit Register with 3.6V Tolerant Inputs and Outputs Physical Dimensions inches (millimeters) unless otherwise noted 64-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD64 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 8 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com