AN-6077

www.fairchildsemi.com AN-6077 SG6742 — Highly Integrated Green-Mode PWM Controller Abstract This application note describes a detailed design strategy for a high-efficiency, compact flyback converter. Design considerations, mathematical equations, and guidelines for a Printed-Circuit-Board (PCB) layout are presented. Introduction The highly integrated SG6742 series of PWM controllers provides several features to enhance the performance of flyback converters. To minimize standby power consumption, a proprietary green-mode function provides off-time modulation to linearly decrease the switching frequency at light-load conditions. To avoid acoustic-noise problems, the minimum PWM frequency is set above 22KHz. This green-mode function enables the power supply to meet international power conservation requirements. With the internal highvoltage startup circuitry, the power loss due to bleeding resistors is also eliminated. To further reduce power consumption, SG6742 is manufactured using the BiCMOS process, which allows an operating current of only 2.7mA. Built-in synchronized slope compensation achieves stable peak-current-mode control. The proprietary external line compensation ensures a constant output-power limit over a wide AC input voltage range, from 90VAC to 264VAC. SG6742 provides many protection functions. In addition to cycle-by-cycle current limiting, the internal open-loop protection circuit ensures safety should an open-loop or output short-circuit failure occur. OVP (VDD) SG6742ML SG6742MR SG6742HL SG6742HR Latch Latch Latch Latch Features High-Voltage Startup Low Operating Current: 2.7mA Linearly Decreasing PWM Frequency to 22KHz Frequency Hopping to Reduce EMI Emission Fixed PWM Frequency: ML and MR are 65KHz. HL and HR are 100KHz. Peak-Current-Mode Control Cycle-by-Cycle Current Limiting Leading-Edge Blanking (LEB) Synchronized Slope Compensation Internal Open-Loop Protection Gate Output Maximum Voltage Clamp: 18V VDD Under-Voltage Lockout (UVLO) VDD Over-Voltage Protection (OVP) Programmable Over-Temperature Protection (OTP) Internal Latch Circuit (OVP, OTP) Internal Sense Short-Circuit Protection Built-In Soft-Start Function ML and MR are 5ms. HL and HR are 6ms. Constant Power Limit (Full AC Input Range) Internal OTP Sensor with Hysteresis OLP (FB) Latch Auto Restart Latch Auto Restart OTP (RT) Latch Latch Latch Latch SCP (SENSE) Auto Restart Auto Restart Auto Restart Auto Restart Frequency 65KHz 65KHz 100KHz 100KHz SOP-8 GND 1 2 3 4 8 7 6 5 GATE VDD SENSE RT Applications General-purpose, switch-mode power supplies and flyback power converters, including: Power Adapters Open-Frame Switch-Mode Power Supply (SMPS) FB NC HV Figure 1. Pin Configuration (Top View) © 2008 Fairchild Semiconductor Corporation Rev. 1.0.2 • 12/1/08 www.fairchildsemi.com 1 AN-6077 APPLICATION NOTE Typical Application Figure 2. Typical Application Block Diagram SG6742ML/HL SG6742MR/HR Figure 3. Functional Block Diagram © 2008 Fairchild Semiconductor Corporation Rev. 1.0.2 • 12/1/08 www.fairchildsemi.com 2 AN-6077 APPLICATION NOTE Internal Block Operation Startup Circuitry When the power is turned on, the internal current source (typically 2mA) charges the hold-up capacitor C1 through a startup resistor RHV. During the startup sequence, the VBULK provides a startup current of about 2.3mA and charges the VDD capacitor C1. RHV and D2 are series connections and can be directly connected by VAC to the HV pin. As the VDD pin reaches the start threshold voltage VDD-ON, the SG6742 activates and signals the MOSFET. The highvoltage source current is switched off and the supply current is drawn from the auxiliary winding of the main transformer, as shown in Figure 4. VAC D2 RHV tD_ ON HV SG6742 GND VDD I HV VDD-ON Under-Voltage Lockout (UVLO) The SG6742 has a voltage detector on the VDD pin to ensure that the chip has enough power to drive the MOSFET. Figure 6 shows a hysteresis of the turn-on and turn-off threshold levels and an open-loop-release voltage. IDD 2.7mA 70µA 10µA 7.5V 9.5V 15.5V VDD Figure 6. UVLO Specification D1 C1 The turn-on and turn-off thresholds are internally fixed at 15.5V and 9.5V. During startup, the VDD capacitor must be charged to 15.5V to enable the IC. The capacitor continues to supply the VDD until the energy can be delivered from the auxiliary winding of the main transformer. The VDD must not drop below 9.5V during startup. If the secondary output short circuits or the feedback loop is open, the FB pin voltage rises rapidly toward the open-loop voltage, VFB-OPEN. If the FB voltage remains above VFB-OLP and lasts for tD-OLP, the SG6742 stops emitting output pulses and enters latched-up mode until VDD drops below 5V. To further limit the input power under a short-circuit or openloop condition, a special two-step UVLO mechanism prolongs the discharge time of the VDD capacitor. Figure 7 shows the traditional UVLO method, along with the special two-step UVLO method. In the two-step UVLO mechanism, an internal sinking current, IDD-OLP, pulls the VDD voltage toward the VDD-OLP. This sinking current is disabled after the VDD drops below VDD-OLP; after which, the VDD voltage is again charged towards VDD-ON. With the two-step UVLO mechanism, the average input power during a short-circuit or open-loop condition is greatly reduced. As a result, overheating does not occur. 15.5V VDD 9.5V General UVLO Gate Figure 4. Startup Circuit for Power Transfer When the supply current is drawn from the transformer, it draws a leakage current of about 1µA from the HV pin. The maximum power dissipation of the RHV is: PRHV = IHV −LC( Typ.) × RHV 2 (1) where IHV-LC is the supply current drawn from HV pin. PRHV = 1μA 2 × 100KΩ ≅ 0.1μW (2) Soft-Start For many applications, it is necessary to minimize the inrush current during the startup period. The built-in 5ms/6ms softstart circuit significantly reduces the startup current spike and output-voltage overshoot. Figure 5. Soft-Start Circuit 15.5V VDD 9.5V 7.5V Two-Step UVLO Gate Figure 7. © 2008 Fairchild Semiconductor Corporation Rev. 1.0.2 • 12/1/08 3 UVLO Effect www.fairchildsemi.com AN-6077 APPLICATION NOTE FB Input The SG6742 is designed for peak-current-mode control. A current-to-voltage conversion is accomplished externally with current-sense resistor RS. Under normal operation, the FB level controls the peak inductor current: IPEAK = VFB − 0.6 4 × RS Built-In Slope Compensation A flyback converter can be operated in either Discontinuous-Current Mode (DCM) or Continuous-Current Mode (CCM). There are many advantages when operating the converter in CCM. With the same output power, a converter in CCM exhibits a smaller peak inductor current than one in DCM. Therefore, a small-sized transformer and a low-rated MOSFET can be applied. On the secondary side of the transformer, the RMS output current of DCM can be twice that of CCM. Larger wire gauge and output capacitors with larger ripple-current ratings are required. DCM operation also results in a higher output voltage spike. A large LC filter is added. Therefore, a flyback converter in CCM achieves better performance with lower component cost. Despite the above advantages of CCM operation, there is one concern—stability. In CCM operation, the output power is proportional to the average inductor current, while the peak current remains controlled. This causes sub-harmonic oscillation when the PWM duty cycle exceeds 50%. Adding slope compensation (reducing the current-loop gain) is an effective way to prevent oscillation. The SG6742 introduces a synchronized positive-going ramp (VSLOPE) in every switching cycle to stabilize the current loop. Therefore, SG6742 helps design a cost-effective, highly efficient, compact, flyback power supply that operates in CCM without additional external components. The positive ramp added is: (3) where VFB is the voltage on the FB pin and 4 is an internal divider ratio. When VFB is less than 0.6V, the SG6742 terminates the output pulses. Figure 8. Feedback Circuit Figure 8 is a typical feedback circuit consisting mainly of a shunt regulator and an opto-coupler. R1 and R2 form a voltage divider for the output-voltage regulation. R3 and C1 are adjusted for control-loop compensation. A small-value RC filter (e.g. RFB= 47Ω, CFB= 1nF) placed on the FB pin to the GND can further increase the stability. The maximum sourcing current of the FB pin is 1.5mA. The phototransistor must be capable of sinking this current to pull the FB level down at no load. The value of the biasing resistor Rb is determined as follows: VOUT − VD − VZ ⋅ K ≥ 1.5mA Rb VSLOPE = VSL • D where VSL = 0.33V and D = duty cycle. 5.2V (5) S 3R FB R SG6742 VSLOPE Q R GATE PWM comp SENSE (4) where: VD is the drop voltage of photodiode, approximately 1.2V; VZ is the minimum operating voltage, 2.5V of the shunt regulator; and K is the current transfer rate (CTR) of the opto-coupler. For an output voltage VOUT=5V, with CTR=100%, the maximum value of Rb is 860Ω. Figure 9. Synchronized Slope Compensation © 2008 Fairchild Semiconductor Corporation Rev. 1.0.2 • 12/1/08 www.fairchildsemi.com 4 AN-6077 APPLICATION NOTE Constant Output-Power Limit The maximum output power of a flyback converter can generally be determined from the current-sense resistor RS. When the load increases, the peak inductor current increases accordingly. When the output current arrives at the protection value, the Output-Current-Protection (OCP) comparator dominates the current-control loop. OCP occurs when the current-sense voltage reaches the threshold value. The output GATE driver is turned off after a small propagation delay tPD. The delay time results in unequal power-limit levels under universal input. A sawtooth power limiter (saw limiter) is designed to solve the unequal power limit problem. As shown in Figure 10, the saw limiter is designed as a positive ramp signal (Vlimit_ramp) and is fed into the inverting input of the OCP comparator. This results in a lower current limit at high-line inputs than at low-line inputs. However, with the fixed propagation delay tPD, the peak primary current would be the same for various line-input voltages. Therefore, the maximum output power can remain a constant value within a wide input voltage range without adding any external circuitry. SG6742 GATE Blanking Circuit SENSE RS Figure 11. Circuit for Brownout Sense-Pin Short-Circuit Protection The SG6742 provides safety protection for power supply production. When the sense resistor is shorted by soldering during production, the pulse-by-pulse current limiting loses efficiency for the purpose of providing over-power protection for the unit. The unit may be damaged when the loading is larger than the original maximum load. To protect against a short circuit across the current-sense resistor, the controller is designed to immediately shut down if a continuously low voltage (around 0.15V/150µs) on the Sense pin is detected. Actual Power Limit Point High-Line Sense Voltage Low-Line Sense Voltage VSTHFL VSTHVA Open-Loop Protection (OLP) 0 ton1 tPD ton2 Figure 10. Constant Power-Limit Compensation Leading-Edge Blanking (LEB) A voltage signal proportional to the MOSFET current develops on the current-sense resistor RS. Each time the MOSFET is turned on, a spike induced by the diode reverse recovery and the output capacitances of the MOSFET and diode, appears on the sensed signal. A leading-edge blanking time of about 140ns is introduced to avoid premature termination of the MOSFET by the spike. Therefore, only a small-value RC filter (e.g. 100Ω + 470pF) is required between the SENSE pin and RS. Still, a noninductive resistor for the RS is recommended. The SG6742 contains the open loop protection function. If the output load is higher than the maximum output current, the output voltage will drop and the feedback error amplifier will be saturated. Once the FB voltage trips the OLP threshold 4.8V and keeps longer than 56ms, the protection will be activated to turns off the gate output to stop the switching of power circuit. As shown in Figure 12, the FB voltage is compared with 4.8V reference voltage. If the FB voltage is higher than 4.8V, the OLP timer starts counting. If the OLP condition persists for 56ms, the timer generates the OLP signal and acts as auto restart for SG6742MR/HR, latch off for SG6742ML/HL. Moreover, this protection will be reset after IC’s UVLO. FB OLP 56ms Timer 4.8V Figure 12. Open-Loop Protection Circuit © 2008 Fairchild Semiconductor Corporation Rev. 1.0.2 • 12/1/08 www.fairchildsemi.com 5 AN-6077 APPLICATION NOTE Output Driver / Soft Driving The output stage is a fast totem-pole gate driver capable of directly driving an external MOSFET. An internal Zener diode clamps the driver voltage under 18V to protect the MOSFET against over-voltage. By integrating special circuits to control the slew rate of switch-on rising time, the external resistor RG may not be necessary to reduce switching noise, improving Electromagnetic Interference (EMI) performance. V DD Thermal Protection A constant current IRT (IRT = 100µA) is provided from the RT pin. For over-temperature protection, an NTC thermistor RT in series with a resistor Ra can be connected between the RT pin and ground. When VRT, the voltage level of the RT pin, is less than 1.05V; PWM output is latched off after a debounce time of tD-OTP1, which is added to prevent false triggering. If VRT is less than 0.7V, PWM output latches off after a very short debounce time of tD-OTP2. If the thermal protection is not used, connect a small capacitor (around 0.47nF is recommended) from the RT pin to the GND pin to prevent noise interference. This RT capacitor cannot be larger than 1nF or the thermal protection is triggered before a successful startup of output voltage. ON/OFF D river 18V GATE RG Over-Temperature Protection (OTP) The built-in temperature-sensing circuit shuts down PWM output once the junction temperature exceeds 135°C. While PWM output is shut down, VDD gradually drops to the UVLO voltage (around 7.5V). Then VDD charges up to the startup threshold voltage of 15.5V through the startup resistor until PWM output is restarted. This hiccup-mode protection occurs repeatedly as long as the temperature remains above 130°C. The temperature hysteresis window for the OTP circuit is 25°C. SG6742 Figure 13. Gate Driver © 2008 Fairchild Semiconductor Corporation Rev. 1.0.2 • 12/1/08 www.fairchildsemi.com 6 AN-6077 APPLICATION NOTE Printed Circuit Board Layout Current, voltage, and switching frequency make PCB layout and design very important. Good PCB layout minimizes excessive EMI and prevents the power supply from being disrupted during surge/ESD tests. The following are some general guidelines: For better EMI performance and to reduce line frequency ripples, the output of the bridge rectifier should be connected to capacitor Cbulk first, then to switching circuits. The high-frequency current loop is found in the loop Cbulk – Transformer – MOSFET – RS – Cbulk in Figure 14. The area enclosed by this current loop should be as small as possible. Keep the traces (especially 4→1) short, direct, and wide. High-voltage drain traces related to the MOSFET and RCD snubber should be kept far from control circuits to prevent unnecessary interference. If a heatsink is used for the MOSFET, grounding the heatsink is recommended. As indicated by 3 in Figure 14, the control circuits’ ground should be connected first, then to other circuitry. As indicated by 2 in Figure 14, the area enclosed by the transformer auxiliary winding, D1, and C1 should also be kept small. Place C1 close to the SG6742 for good decoupling. Two suggestions with pros and cons for ground connections are recommended. GND3→2→4→1: Possible method for circumventing the sense signals and common impedance interference. GND3→2→1→4: Potentially better for ESD testing where a ground is not available for the power supply. The charges for ESD discharge path go from secondary through the transformer stray capacitance to the GND2 first. Then, the charges go from GND2 to GND1 and back to the mains. It should be noted that control circuits should not be placed on the discharge path. Point discharge for common choke can decrease high-frequency impedance and help increase ESD immunity. Should a Y-cap between primary and secondary be required, the Y-cap should be connected to the positive terminal of the Cbulk (VDC). If this Y-cap is connected to the primary GND, it should be connected to the negative terminal of the Cbulk (GND1) directly. Point discharge of the Y-cap also helps with ESD. However, according to safety requirements, the creepage between the two pointed ends should be at least 5mm. VDC Cbulk Common mode choke RHV D1 C1 1 Ra RT RT HV VDD 2 Rg SG6742 GATE Rf SENSE FB RFB CFB GND Cf RS Y-cap 4 5 3 Figure 14. Layout Considerations © 2008 Fairchild Semiconductor Corporation Rev. 1.0.2 • 12/1/08 www.fairchildsemi.com 7 AN-6077 APPLICATION NOTE Related Datasheets SG6742ML/MR — Highly Integrated Green-Mode PWM Controller SG6742HL/HR — Highly Integrated Green-Mode PWM Controller DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. © 2008 Fairchild Semiconductor Corporation Rev. 1.0.2 • 12/1/08 www.fairchildsemi.com 8