AN-6747

www.fairchildsemi.com AN-6747 Applying FAN6747 to Control a Flyback Power Supply with Peak Current Output 1. Introduction Highly integrated PWM controller, FAN6747, is optimized for applications with motor load, such as printers and scanners, that inherently impose some kind of overload condition on the power supply during acceleration mode. FAN6747 provides a two-level OCP function that allows the SMPS to stably deliver peak power during the motor acceleration without causing premature shutdown, while protecting the SMPS from overload condition. Green-mode and burst-mode functions with a low operating current maximize the light-load efficiency so that the power supply can meet stringent standby power regulations. The frequency-hopping function reduces electro-magnetic interference (EMI) of a power supply by spreading the energy over a wider frequency range. The constant power limit function minimizes the component stress in abnormal condition and helps optimize the power stage. Protection functions such as OCP, OLP, OVP, and OTP are fully integrated into FAN6747, which improves the SMPS reliability without increasing system cost. This application note presents design considerations to apply FAN6747 to a flyback power supply with peak load current profile. It covers designing the transformer, selecting the components, and closing the feedback loop. Figure 1 shows a typical application circuit using FAN6747. Figure 1. Typical Application © 2010 Fairchild Semiconductor Corporation Rev. 1.0.1 • 9/16/10 www.fairchildsemi.com AN-6747 APPLICATION NOTE 2. Design Considerations Flyback converters have two operation modes; continuous conduction mode (CCM) and discontinuous conduction mode (DCM). CCM and DCM each have advantages and disadvantages. In general, DCM provides better switching conditions for the rectifier diodes, since the diodes are operating at zero current just before becoming reverse biased and the reverse recovery loss is minimized. The transformer size can be reduced using DCM because the average energy storage is low compared to CCM. However, DCM causes high RMS current, which increases the conduction loss of the MOSFET severely for low line condition. Thus, especially for applications with peak load profile, such as printer and scanner; it is typical to design the converter such that the converter operates in CCM for low line and peak load condition to maximize efficiency. In this section, a design procedure is presented using the schematic of Figure 1 as a reference. An offline SMPS with 20W/32V nominal output power and 70W/32V peak output power has been selected as a design example. [STEP-1] Define the System Specifications Designing a power supply with peak load current profile, the following specifications should be determined first: Line voltage range (VLINEMIN and VLINEMAX) Line frequency (fL) Nominal output power (PNO) Peak output power (PPO) and its duration (tPO) Estimated efficiencies for nominal load (ηN) and peak load (ηP). The power conversion efficiency must be estimated to calculate the input powers for each condition. Typically, the efficiency at peak load condition is lower than that of nominal load since most of the components of power supply are selected for nominal load condition. If no reference data is available, set ηN = 0.7~0.75 and ηP = 0.65~0.7 for low-voltage output applications and ηN = 0.8~0.85 and ηP = 0.75~0.8 for high-voltage output applications. With the estimated efficiency, the input power for peak load condition is given by: PINP = PPO ηP (Design Example) The specifications of the target system are: VLINEMIN =90VRMS, VLINEMAX=264VRMS Line frequency (fL) = 60Hz Nominal output power (PNO) = 20W (32V/0.625A) Peak output power (PPO) = 70W (32V/2.187A) Peak load duration (tPO) < 100ms Estimated efficiency: ηN = 0.87 and ηP = 0.83 PINP = PPO 70 = = 84 W ηP 0.83 PNO 20 = = 23 W ηN 0.87 PINN = FAN6747 can be used for this application because the peak load duration is less than the OCP delay time of 220ms. [STEP-2] Determine the Input Capacitor (CIN) and the Input Voltage Range It is typical to select the input capacitor as 1.5~2μF per watt of peak input power for universal input range (85-265VRMS) and 0.7~0.8μF per watt of peak input power for European input range (195V-265VRMS). With the input capacitor chosen, the minimum input capacitor voltage at peak load condition is obtained as: VINPMIN = 2 • VLINE MIN ( ) 2 − PINP • (1 − D CH ) CIN • fL ( 3) The minimum input capacitor voltage at nominal load condition is obtained as: VINNMIN = 2 • VLINE MIN ( ) 2 − PINN • (1 − D CH ) CIN • fL ( 4) where DCH is the input capacitor charging duty ratio defined as shown in Figure 2, which is typically about 0.2. The maximum input capacitor voltage is given as: VINMAX = 2 VLINEMAX ( 5) (1) The input power for nominal load condition is given by: PINN = PNO ηN (2) Figure 2. Input Capacitor Voltage Waveform © 2010 Fairchild Semiconductor Corporation Rev. 1.0.1 • 9/16/10 www.fairchildsemi.com 2 AN-6747 APPLICATION NOTE (Design Example) By choosing a 120μF capacitor for the input capacitor, the minimum input voltages for peak and nominal load are obtained, respectively, as: VINPMIN = 2 • VLINE MIN = 2 • (90 )2 − ( ) 2 − PINP • (1 − D CH ) CIN • fL = 83 V 84 • (1 − 0.2) 120 × 10 − 6 • 60 VINNMIN = 2 • VLINE MIN = 2 • (90)2 − ( ) 2 − PINN • (1 − D CH ) CIN • fL −6 As can be seen in Equation (7), the voltage stress across the MOSFET can be reduced by reducing VRO; however, this increases the voltage stresses on the rectifier diodes in the secondary side. Therefore, VRO should be determined by a trade-off between the voltage stresses of MOSFET and diode. Because the actual drain voltage rises above the nominal MOSFET voltage due to the leakage inductance of the transformer, as shown in Figure 3, it is typical to set VRO around 70~100V so that VDSNOM is 430~450V for 600V MOSFET (73~78% of MOSFET voltage rating). (Design Example) By determining VRO as 100V: 23 • (1 − 0.2) 120 × 10 • 60 = 117 V DMAX = VRO VRO + VINP MIN = 100 = 0.55 100 + 83 The maximum input voltage is obtained as: VINMAX = 2 • VLINEMAX = 2 • 264 = 373V VDSNOM = VINMAX + VRO = 373 + 100 = 473V [STEP-3] Determine the Reflected Output Voltage (VRO) When the MOSFET is turned off, the input voltage (VIN), together with the output voltage reflected to the primary, (VRO) are imposed across the MOSFET, as shown in Figure 3. With a given VRO, the maximum duty cycle (DMAX) and the maximum nominal MOSFET voltage (VDSNOM) are obtained as: DMAX = VRO VRO + VINP MIN [STEP-4] Determine the Transformer Primary-Side Inductance (LM) The transformer primary-side inductance is determined for the minimum input voltage and peak load condition. With the DMAX from step 3, the primary-side inductance (LM) of the transformer is obtained as: LM = (V INP • D MAX 2PINP fSW K RF MIN ) 2 ( 8) ( 6) ( 7) where fSW is the switching frequency and KRF is the ripple factor at peak load and minimum input voltage condition, as shown in Figure 4. The ripple factor is closely related to the transformer size and the RMS value of the MOSFET current. Even though the conduction loss in the MOSFET can be reduced by reducing the ripple factor, too small a ripple factor forces an increase in transformer size. From a practical point of view, it is reasonable to set KRF = 0.3~0.6 for the universal input range and KRF = 0.4~0.8 for the European input range. Once LM is calculated by determining KRF from Equation (8), the peak current and RMS current of the MOSFET for minimum input voltage and peak load condition are obtained as: IDS PK = IEDC + ΔI 2 VDSNOM = VINMAX + VRO ( 9) (10) (11) (12) I DS RMS = 2 ⎡ ⎛ ΔI ⎞ ⎤ D 2 ⎢3(I EDC ) + ⎜ ⎟ ⎥ MAX ⎝2⎠⎥ 3 ⎢ ⎣ ⎦ where and IEDC = VINP PINP MIN • DMAX ΔI = VINP MINDMAX L M fSW Figure 3. Output Voltage Reflected to the Primary www.fairchildsemi.com 3 © 2010 Fairchild Semiconductor Corporation Rev. 1.0.1 • 9/16/10 AN-6747 APPLICATION NOTE K RF ΔI ΔI = 2 I EDC The peak drain current at minimum input voltage and peak load condition was obtained from Equation (9) in step 4. The peak drain current at minimum input voltage and nominal load condition is given as: CCM: I DS PK Figure 4. MOSFET Current and Ripple Factor (KRF) IDS.NPK = PINN • VINMIN + VRO VINNMIN • VRO ( )+ VINNMIN • VRO 2L M fSW • VINNMIN + VRO ( ) (13) DCM: IDS.NPK = 2 • PINN fSW • L M (Design Example) Determining the ripple factor as 0.375: (14) LM = (V INP • DMAX 2PINP fSW K RF MIN ) 2 = (83 • 0.55)2 2 • 84 • 65 × 10 3 • 0.375 = 508μH Whether the converter operates in CCM or DCM at minimum input voltage and nominal load condition is determined by: CCM: 2PINNL M f SW • IEDC = ΔI = V INP PINP MIN •DMAX = 84 = 1.84A 83 • 0.55 (V MIN MIN MIN INN + VRO • VRO + VRO )>1 (15) VINN VINPMINDMAX 83 • 0.55 = = 1.38 A L M fSW 508 × 10 − 6 • 65 × 10 3 ΔI = 1.84 + 0.69 = 2.53 2 DCM: 2PINNL M f SW • (V INN IDS PK = IEDC + VINNMIN • VRO )1m). When the wire is short with a small number of turns, a current density of 8~14A/mm2 is also acceptable. These current densities are based on the peak load condition and therefore almost twice conventional power supply design. Avoid using wire with a diameter larger than 1mm to avoid severe eddy current losses and to make winding easier. For high current output, use parallel windings with multiple strands of thinner wire to minimize skin effect. (Design Example) The RMS current of the primary- 1 − DMAX DMAX 1 − 0 . 55 = 3 . 84 A 0 . 55 10A and 200V diode is selected, assuming a very small heat-sink is used for the diode. [STEP-10] Feedback Circuit Configuration The FAN6747 employs peak-current-mode control, as shown in Figure 8. A current-to-voltage conversion is accomplished externally with current-sense resistor RCS. Under normal operation, the FB level controls the peak inductor current as: IDS • R CS + VSLOPE = IDS • R CS + 0.35 • D = VFB − 0.6 (27) 4 side winding is obtained from step 4 as 1.4A. The RMS current of the secondary-side winding is calculated as: ISECRMS = n • IDSRMS 1 − DMAX DMAX = 3 . 03 • 1 . 4 1 − 0 . 55 = 3 . 84 A 0 . 55 where VFB is the voltage of FB pin, VSLOPE is synchronized positive-going ramp, and D is duty cycle ratio. 0.45mm (8A/mm2) and 0.55mm (12A/mm2) diameter wires are selected for primary and secondary windings, respectively. [STEP-9] Choose the Rectifier Diode in the Secondary-Side Based on Voltage and Current Ratings The maximum reverse voltage and the RMS current of the rectifier diode are obtained as: VDO = VO + VINMAX n (23) 1 − DMAX DMAX IDORMS = n • IDSRMS (24) Figure 8. Peak Current Mode Circuit The typical voltage and current margins for the rectifier diode are: VRRM > 1.3 • VDO (25) (26) IF > 1.5 • IDO RMS where VRRM is the maximum reverse voltage and IF is the current rating of the diode. Figure 9 is a typical feedback circuit mainly consisting of a shunt regulator and a photo-coupler. R1 and R2 form a voltage divider for output voltage regulation. RF and CF are adjusted for control-loop compensation. A small-value RC filter (e.g. RFB= 100Ω, CFB= 1nF) placed from the FB pin to GND can increase stability substantially. The maximum source current of the FB pin is about 325μA. The phototransistor must be capable of sinking this current to pull the FB level down at no load. The value of the biasing resistor, RBIAS, is determined as: www.fairchildsemi.com 6 © 2010 Fairchild Semiconductor Corporation Rev. 1.0.1 • 9/16/10 AN-6747 APPLICATION NOTE VO − VOPD − VKA • CTR > 325 × 10 − 6 R BIAS (28) where VOPD is the drop voltage of photodiode, about 1.2V; VKA is the minimum cathode to anode voltage of shunt regulator (2.5V); and CTR is the current transfer rate of the opto-coupler. 5.2V iD vFB 3R R CF RF R2 R BIAS vO A two-stage hold-up capacitor configuration (CDD1 and CDD2) is typically used to increase the hold-up time while minimizing startup time. Initially, the FAN6747 HV startup circuit is enabled before it begins normal switching operation. Therefore, the current supplied by the HV pin can charge capacitor CDD1 while supplying the startup current to FAN6747. When VDD reaches the turn-on voltage of 16.5V (VDD-ON), FAN6747 begins switching operation and the HV startup circuit is disabled. Then the current required by FAN6747 is supplied from the auxiliary winding of transformer. It is typical to use a 150~250kΩ resistor for the HV pin to improve the immunity against line surge. C FB RDB R1 Figure 9. Feedback Circuit The feedback compensation network transfer function of Figure 9 is obtained as: ˆ ν FB ω 1 + s / ω ZC =− I• ˆ νO s 1 + s / ω PC (29) where ωI = RB 1 1 ; ω ZC = ;ω = (RF + R1 )CO PC RB CFB R1R DB CF RB is the internal feedback bias resistor; and R1, RD, RF, CF, and CFB are shown in Figure 9. (Design Example) Assuming CTR is 100%; VO − VOPD − VKA • CTR > 325 × 10 − 6 R BIAS Figure 10. Startup Circuit R BIAS < VO − VOPD − VKA 325 × 10 − 6 = 32 − 1.2 − 2.5 325 × 10 − 6 = 87kΩ 5.1kΩ resistor is selected for RDB. The voltage divider resistors for VO sensing are selected as 120kΩ and 10kΩ. [STEP-11] Design the Startup Circuit Figure 10 shows the typical startup circuit for FAN6747. HV pin has an internal high-voltage startup circuit that is disabled when VDD reaches its turn-on threshold. Since HV pin is also used to obtain line voltage information for brownout protection and power limit line compensation, it is typical to connect the HV pin to the AC line through a resistor and diode. © 2010 Fairchild Semiconductor Corporation Rev. 1.0.1 • 9/16/10 Leading-Edge Blanking (LEB) Each time the power MOSFET is switched on, a turn-on spike occurs across the sense resistor, caused by primaryside capacitance and secondary-side rectifier reverse recovery. To avoid premature termination of the switching pulse, a leading-edge blanking time is built in. During this blanking period (270ns), the PWM comparator is disabled and cannot switch off the gate driver. Thus, an RC filter with a small RC time constant is enough for current sensing (e.g. 100Ω + 470pF). A non-inductive resistor is recommended for RCS. www.fairchildsemi.com 7 AN-6747 APPLICATION NOTE NTC thermister decreases and RT pin voltage drops. When the voltage of the RT pin is less than 1.05V but over 0.7V, the PWM turns off after 16ms (tD_OTP-LATCH). When RT pin voltage is less than 0.7V, OTP is triggered after the 185μs (tD_OTP2-LATCH) debounce time. If the RT pin is not connected to the NTC resistor for overtemperature protection, a 100KW resistor to ground to prevent noise interference is recommended. This pin is limited by the internal clamping circuit. Figure 11. Current Sensing Figure 12. Thermal Protection Circuit Thermal Protection Figure 12 shows the internal blocks for thermal protection. A constant current, IRT, of 100μA is provided from the RT pin. For over-temperature protection, an NTC thermistor in series with a resistor can be connected between the RT and GND pins. As temperature increases, the impedance of © 2010 Fairchild Semiconductor Corporation Rev. 1.0.1 • 9/16/10 www.fairchildsemi.com 8 AN-6747 APPLICATION NOTE Printed Circuit Board (PCB) Layout PCB layout is a very important design issue for highfrequency switching current/voltage application. Good PCB layout minimizes excessive EMI and helps the power supply survive during surge / ESD tests. Guidelines: To get better EMI performance and reduce line frequency ripples, the output of the bridge rectifier should be connected to capacitor C1 first, then to the switching circuits. The high-frequency current loop is in C1 – transformer – MOSFET – RS – C1. The area enclosed by this current loop should be as small as possible. Keep the traces (especially 4 → 1) short, direct, and wide. High-voltage traces related to the drain of MOSFET and RCD snubber should be kept far way from control circuits to prevent unnecessary interference. If a heatsink is used for the MOSFET, connect this heatsink to ground. As indicated by 3, the ground of control circuits should be connected first, then to other circuitry. As indicated by 2, the area enclosed by transformer auxiliary winding, D1, C2, D2, and C3 should also be kept small. Place C3 close to the FAN6747 for good decoupling. Two suggestions with different advantages disadvantages for ground connections are offered: and GND3 → 2 → 4 → 1: This could avoid common impedance interference for sense signal. GND3 → 2 → 1 → 4: This could be better for ESD testing where the earth ground is not available on the power supply. Regarding the ESD discharge path, the charges go from secondary through the transformer stray capacitance to GND2 first. The charges then go from GND2 to GND1 and back to the mains. Control circuits should not be placed on the discharge path. Point discharge for common choke can decrease highfrequency impedance and increase ESD immunity. Should a Y-cap between primary and secondary be required, connect this Y-cap to the positive terminal of C1. If this Y-cap is connected to the primary GND, it should be connected to the negative terminal of C1 (GND1) directly. Point discharge of this Y-cap also helps for ESD. However, the creepage between these two pointed ends should be large enough to satisfy the requirements of applicable standards. Figure 13. © 2010 Fairchild Semiconductor Corporation Rev. 1.0.1 • 9/16/10 Layout Considerations www.fairchildsemi.com 9 AN-6747 APPLICATION NOTE Design Summary Figure 14 shows the final schematic of the 20W (70W peak) power supply of the design example. Figure 14. Final Schematic of Design Example © 2010 Fairchild Semiconductor Corporation Rev. 1.0.1 • 9/16/10 www.fairchildsemi.com 10 AN-6747 APPLICATION NOTE Transformer Specification 4 N3 3 N1 N2 5 1 N4 9 2 JP3(fly line) 1 5 10 6 Bottom View Figure 15. Transformer Specification Winding Specification Pin N1 5 3 Insulation Tape Shielding Lead to Pin 4 Insulation Tape N2 JP3 9 Insulation Tape Shielding Lead to Pin 4 Insulation Tape N3 3 4 Insulation Tape N4 1 2 Insulation Tape Diameter / Thickness 0.45mm Turns 30 3 65 3 20 3 65 3 30 6 9 3 0.55mm 0.45mm 0.2mm Core: EF25/13/11 (Ae=78 mm2) Bobbin: EF25/13/11 Inductance: 508μH © 2010 Fairchild Semiconductor Corporation Rev. 1.0.1 • 9/16/10 www.fairchildsemi.com 11 AN-6747 APPLICATION NOTE Related Datasheets FAN6747 — Highly Integrated Green-Mode PWM Controller for Peak Power Management DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. © 2010 Fairchild Semiconductor Corporation Rev. 1.0.1 • 9/16/10 www.fairchildsemi.com 12