AN-6921

www.fairchildsemi.com AN-6921 Integrated Critical Mode PFC / Quasi-Resonant Current Mode PWM Controller FAN6921 1. Introduction This application note presents practical step-by-step design considerations for power supply system employing Fairchild’s FAN6921 PFC/PWM combination controller, which combines a Boundary Conduction Mode (BCM) Power Factor Correction (PFC) controller and QuasiResonant (QR) PWM controller. Figure 1 shows the typical application circuit, where the BCM PFC converter is in the front end and the Quasi-Resonant flyback converter is in the back end. FAN6921 achieves high efficiency with relatively low cost for 75~200W applications where BCM and QR operation with a single switch show best performance. BCM boost PFC converter can achieve better efficiency with lower cost than continuous conduction mode (CCM) boost PFC converter. These benefits result from the elimination of the reverse-recovery losses of the boost diode and zero-voltage switching (ZVS) or near ZVS (also called valley switching) of boost switch. The QR flyback converter for the DC/DC conversion achieves higher efficiency than the conventional hard-switching converter with valley switching. Moreover, FAN6921 has variable PFC output voltage function that can improve the overall efficiency by reducing the conduction loss of PFC converter and switching loss of DC/DC converter stage at low-line condition. Figure 1. Typical Application Circuit © 2010 Fairchild Semiconductor Corporation Rev. 1.0.1 • 8/24/10 www.fairchildsemi.com AN-6921 APPLICATION NOTE 2. Operation Principle of BCM Boost PFC Converter The most widely used operation modes for the boost converter are continuous conduction mode (CCM) and boundary conduction mode (BCM). These refer to the current flowing through the energy storage inductor of the boost converter, as depicted in Figure 2. As the names indicate, the inductor current in CCM is continuous; while in BCM, the new switching period is initiated when the inductor current returns to zero, which is at the boundary of continuous conduction and discontinuous conduction operations. Even though the BCM operation has higher RMS current in the inductor and switching devices, it allows better switching condition for the MOSFET and the diode. As shown in Figure 2, the diode reverse recovery is eliminated and a fast silicon carbide (SiC) diode is not needed. MOSFET is also turned on with zero current, which reduces the switching loss. BCM operation an ideal candidate for power factor correction. A by-product of the BCM is that the boost converter runs with variable switching frequency that depends primarily on the selected output voltage, the instantaneous value of the input voltage, the boost inductor value, and the output power delivered to the load. The operating frequency changes as the input current follows the sinusoidal input voltage waveform, as shown in Figure 3. The lowest frequency occurs at the peak of sinusoidal line voltage. Figure 3. Operation Waveforms of BCM PFC The voltage-second balance equation for the inductor is: VIN (t ) ⋅ tON = (VO.PFC − VIN (t )) ⋅ tOFF where VIN(t) is the rectified line voltage. (1 ) The switching frequency of BCM boost PFC converter is obtained as: f SW = = 1 1 VO. PFC − VIN (t ) = ⋅ tON + tOFF tON VOUT ⋅ VO. PFC − VIN , PK ⋅ | sin(2π f LINE t ) | VO. PFC 1 tON (2 ) where VIN,PK is the amplitude of the line voltage and fLINE is the line frequency. Figure 2. CCM vs. BCM Control The fundamental idea of BCM PFC is that the inductor current starts from zero in each switching period, as shown in Figure 3. When the power transistor of the boost converter is turned on for a fixed time, the peak inductor current is proportional to the input voltage. Since the current waveform is triangular, the average value in each switching period is also proportional to the input voltage. In the case of a sinusoidal input voltage, the input current of the converter follows the input voltage waveform with a very high accuracy and draws a sinusoidal input current from the source. This behavior makes the boost converter in © 2010 Fairchild Semiconductor Corporation Rev. 1.0.1 • 8/24/10 2 Figure 4 shows how the MOSFET on time and switching frequency change as output power decreases. When the load decreases, as shown in the right side of Figure 4, the peak inductor current diminishes with reduced MOSFET on time and the switching frequency increases. www.fairchildsemi.com AN-6921 APPLICATION NOTE 3. Operation Principle of QuasiResonant Flyback Converter QR flyback converter topology can be derived from a conventional square wave, pulse-width modulated (PWM), flyback converter without adding additional components. Figure 6 and Figure 7 show the simplified circuit diagram of a quasi-resonant flyback converter and its typical waveforms. The basic operation principles are: During the MOSFET on time (tON), input voltage (VIN) is applied across the primary-side inductor (Lm). MOSFET current (IDS) increases linearly from zero to the peak value (Ipk). During this time, the energy is drawn from the input and stored in the inductor. When the MOSFET is turned off, the energy stored in the inductor forces the rectifier diode (D) to turn on. During the diode ON time (tD), the output voltage (Vo) is applied across the secondary-side inductor and the diode current (ID) decreases linearly from the peak value to zero. At the end of tD, all the energy stored in the inductor has been delivered to the output. During this period, the output voltage is reflected to the primary side as Vo× Np/Ns. Then, the sum of input voltage (VIN) and the reflected output voltage (Vo× Np/Ns) is imposed across the MOSFET. When the diode current reaches zero, the drain-tosource voltage (VDS) begins to oscillate by the resonance between the primary-side inductor (Lm) and the MOSFET output capacitor (Coss) with an amplitude of Vo× Np/Ns on the offset of VIN, as depicted in Figure 7. Quasi-resonant switching is achieved by turning on the MOSFET when VDS reaches its minimum value. This reduces the MOSFET turn-on switching loss caused by the capacitance loading between the drain and source of the MOSFET. Figure 4. Frequency Variation of BCM PFC Since the design of line filter and inductor for a BCM PFC converter with variable switching frequency should be done at minimum frequency condition, it is worthwhile to examine how the minimum frequency of BCM PFC converter changes with operating conditions. Figure 5 shows the minimum switching frequency, which occurs at the peak of line voltage, as a function of the RMS line voltage for different output voltage settings. For universal line application, the minimum switching frequency occurs at high line (265VAC) as long as the output voltage is lower than about 405V. Figure 5. Minimum Switching Frequency vs. RMS Line Voltage (L = 780µH, POUT = 100W) Figure 6. Schematic of QR Flyback Converter © 2010 Fairchild Semiconductor Corporation Rev. 1.0.1 • 8/24/10 www.fairchildsemi.com 3 AN-6921 APPLICATION NOTE IDS (MOSFET Drain-to-Source Current) Ipk The MOSFET conduction time with a given line voltage at a nominal output power is given as: tON = ID (Diode Current) Ipk×Np/Ns 2 ⋅ PO . PFC ⋅ L η ⋅ VLINE 2 (4) where: η is the overall efficiency; L is the boost inductance; and POUT is the nominal output power. Using Equation 4, the minimum switching frequency of Equation 3 can be expressed as: VDS (MOSFET Drain-to-Source Voltage) VIN +Vo×Np/Ns Vo×Np/Ns f SW , MIN = η ⋅ VLINE 2 VO . PFC − 2VLINE 2 ⋅ POUT ⋅ L ⋅ VO . PFC (5) Vo×Np/Ns VIN VIN -Vo×Np/Ns tON tS tD Since the minimum frequency occurs at high line as long as the PFC output voltage is lower than 405V, as observed in Figure 5; once the output voltage and minimum switching frequency are set, the inductor value is given as: L= η ⋅ (VLINE .MAX ) 2 2 ⋅ POUT ⋅ f SW , MIN ⋅ Figure 7. Typical Waveforms of QR Flyback Converter VO. PFC − 2VLINE .MAX VO . PFC (6) 4. Design Considerations This design procedure uses the schematic in Figure 1 as a reference. A 90W PFC application with universal input range is selected as a design example. The design specifications are: Line Voltage Range: 90~264VAC (60Hz) Output of DC/DC Converter: 19V/4.7A (90W) PFC Output Voltage for High Line: 400V (VO.PFC.H) PFC Output Voltage for Low Line: 260V (VO.PFC.L) Minimum PFC Switching Frequency: > 50kHz Brownout Protection Line Voltage: 70VAC Output Over-Voltage Protection Trip Point: 22.5V Overall Efficiency: 90% (PFC Stage: 95%, DC/DC Stage: 95%) where VLINE,MAX is the maximum line voltage. As the minimum frequency decreases, the switching loss is reduced, while the inductor size and line filter size increase. Thus, the minimum switching frequency should be determined by the trade-off between efficiency and the size of magnetic components. The minimum switching frequency must be above 20kHz to prevent audible noise. Once the inductance value is decided, the maximum peak inductor current at the nominal output power is obtained at low-line condition as: I L. PK = 2 2 ⋅ POUT η ⋅ VLINE , MIN (7) where VLINE,MIN is the minimum line voltage. Since the maximum on time is internally limited at 20µs, it should be smaller than 20µs as: Part A. PFC Section [STEP-A1] Boost Inductor Design tON MAX = The boost inductor value is determined by the output power and the minimum switching frequency. From Equation 2, the minimum frequency with a given line voltage and MOSFET on time is obtained as: 2 ⋅ POUT ⋅ L < 20 μ s η ⋅ VLINE . MIN 2 (8) The number of turns of boost inductor should be determined considering the core saturation. The minimum number is given as: f SW , MIN = 1 VO.PFC − 2VLINE ⋅ tON VO. PFC (3) N BOOST ≥ I L, PK ⋅ L Ae ⋅ ΔB (9) where: VLINE is RMS line voltage; tON is the MOSFET conduction time; and VO.PFC is the PFC output voltage. © 2010 Fairchild Semiconductor Corporation Rev. 1.0.1 • 8/24/10 where is Ae is the cross-sectional area of core and ΔB is the maximum flux swing of the core in Tesla. ΔB should be set below the saturation flux density. www.fairchildsemi.com 4 AN-6921 APPLICATION NOTE (Design Example) Since the output voltage is 400V for high line and 260V for low line, the minimum frequency occurs at high-line (264VAC) and full-load condition. Assuming the overall efficiency is 90% and selecting the minimum frequency as 58kHz, the inductor value is obtained as: η ⋅ VLINE , MAX 2 VO. PFC . H − 2VLINE , MAX L= ⋅ VO . PFC . H 2 ⋅ POUT ⋅ f SW , MIN = 0.9 ⋅ 264 2 400 − 2 ⋅ 264 ⋅ = 400 μ H 400 2 ⋅ 90 ⋅ 58 × 103 The maximum peak inductor current at nominal output power is calculated as: I L, PK = 2 2 ⋅ POUT η ⋅VLINE , MIN = 2 2 ⋅ 90 = 3.14 A 0.9 ⋅ 90 Figure 8. Internal Block for ZCD tON MAX 2 ⋅ POUT ⋅ L 2 ⋅ 90 ⋅ 400 × 10−6 = = η ⋅ VLINE .MIN 2 0.9 ⋅ 90 2 = 9.87 μ s < 20 μ s Assuming RM10 core (PC40, Ae=98mm2) is used and setting ΔB as 0.23T, the primary winding should be: N BOOST ≥ I L , PK ⋅ L Ae ⋅ ΔB = 3.14 ⋅ 400 × 10−6 = 55.7 turns 98 × 10−6 ⋅ 0.23 N ZCD (VO.PFC − VIN ) N BOOST N ZCD VIN N BOOST Thus, the number of turns (NBOOST) of boost inductor is determined as 60. [STEP-A2] Auxiliary Winding Design Figure 9 shows the internal block for zero-current detection (ZCD) for the PFC. FAN6921 indirectly detects the inductor zero current instant using an auxiliary winding of the boost inductor. The auxiliary winding should be designed such that the voltage of the ZCD pin rises above 2.1V when the boost switch is turned off to trigger internal comparator as: N ZCD (VO.PFC .H − 2VLINE . MAX ) > 2.1V N BOOST Figure 9. (10) ZCD Waveforms (Design Example) The number of turns for the auxiliary where VO.PFC.H is the PFC output voltage for high line condition. The ZCD pin has upper voltage clamping and lower voltage clamping at 10V and 0.65V, respectively. When the ZCD pin voltage is clamped at 0.65V, the maximum sourcing current is 1.5mA and, therefore, the resistor RZCD should be properly designed to limit the current of the ZCD pin below 1.5mA in the worst case as: RZCD > VIN N ⋅ AUX = 1.5mA N BOOST 2VLINE .MAX N AUX ⋅ 1.5mA N BOOST (11) ZCD winding is obtained as: N ZCD > 2.1N BOOST (VO. PFC . H − 2VLINE . MAX ) = 4.7turns With a margin, NAUX is determined as 8 turns. Then RZCD is selected from: RZCD > 2VLINE .MAX N ZCD 2 ⋅ 265 8 ⋅ = ⋅ = 33k Ω N BOOST 1.5 × 10−3 60 1.5mA as 68kΩ. © 2010 Fairchild Semiconductor Corporation Rev. 1.0.1 • 8/24/10 www.fairchildsemi.com 5 AN-6921 APPLICATION NOTE [STEP-A3] Design VIN and VO.PFC Sense Circuit FAN6921 senses the line voltage using the averaging circuit shown in Figure 10, where the VIN pin is connected to the AC line through a voltage divider and low-pass filter capacitor. When VIN pin voltage drops below 1V, the COMP pin is clamped at 1.6V to limit the energy delivered to output. Then VO.PFC decreases with the INV pin voltage. When INV pin voltage drops below 1.2V, brownout protection is triggered, stopping gate drive signals of PFC and DC/DC. This protection is reset when VDD drops below the turn-off threshold (UVLO threshold). When VDD rises to the turn-on voltage after dropping below the turn-off threshold, FAN6921 resumes normal operation (if VVIN is higher than 1.3V). The brownout protection level can be determined as: VLINE. BO = RVIN 1 + RVIN 2 RVIN 2 22 ⋅ π (12) Figure 10. VIN Sensing Internal Block (13) (Design Example) Setting the brownout protection trip point as 69VAC: The minimum line voltage for PFC startup is given as: VLINE .STR = 1.3 ⋅ VLINE .BO FAN6921 has a variable output voltage function that reduces the PFC output voltage at low-line condition. When the voltage of the VIN pin is higher than 2.45V, the internal switch QR is turned on and the lower resistor RPFC2 of the voltage divider is in parallel with RPFC3. Then, the PFC output voltage for high line is given as: VO. PFC . H = 2.5 ⋅ ( RPFC1 + 1) RPFC 2 // RPFC 3 (14) RVIN 1 + RVIN 2 22 = VLINE . BO ⋅ = 62 π RVIN 2 Determining RVIN2 as 154kΩ, RVIN1 is determined as 9.4MΩ. The line voltage to start up the PFC is obtained as: VLINE. STR = 1.3 ⋅ VLINE . BO = 90VAC To regulate the PFC output voltage at high line as 400V: When the voltage of the VIN pin is lower than 2.1V, the lower resistor RPFC2 of the voltage divider is not in parallel with RPFC3. Then, the PFC output voltage for low line is given as: VO.PFC . L = 2.5 ⋅ ( RPFC1 + 1) RPFC 2 (15) VO.PFC = 2.5 ⋅ ( RPFC1 + 1) = 400 RPFC 2 // RPFC 3 By selecting RPFC1=9.4MΩ: The ratio between the nominal PFC output voltage and reduced PFC output voltage is approximated as: VO. PFC . H R ≅ PFC 2 + 1 VO.PFCL RPFC 3 (16) RPFC 2 // RPFC 3 = 9.4M Ω = 59.1k Ω 400 − 1) ( 2.5 To regulate the PFC output voltage at low line as 260V: VO.PFC . H 400 RPFC 2 = ≅ +1 VO. PFC . L 260 RPFC 3 By selecting RPFC2=165kΩ: RPFC 3 = ( 400 − 1) RPFC 2 = 89k Ω 260 So RPFC1, RPFC2, and RPFC3 are selected from the off-the-shelf components as 9.4MΩ, 91kΩ , and 165kΩ , respectively. © 2010 Fairchild Semiconductor Corporation Rev. 1.0.1 • 8/24/10 www.fairchildsemi.com 6 AN-6921 APPLICATION NOTE [STEP-A4] Current Sensing Resistor for PFC FAN6921 has pulse-by-pulse current limit function. It is typical to set the pulse-by-current limit level at 20~30% higher than the maximum inductor current: [STEP-A6] Design Compensation Network RCS1 = 0.85 I L. PK (1 + K MARGIN ) (17) where KMARGIN is the margin factor and 0.85V is the pulseby-pulse current limit threshold. (Design Example) Choosing the margin factor as 35%, the sensing resistor is selected as: The feedback loop bandwidth must be lower than 20Hz for the PFC application. If the bandwidth is higher than 20Hz, the control loop may try to reduce the 120Hz ripple of the output voltage and the line current is distorted, decreasing power factor. A capacitor is connected between COMP and GND to attenuate the line frequency ripple voltage by 40dB. If a capacitor is connected between the output of the error amplifier and the GND, the error amplifier works as an integrator and the error amplifier compensation capacitor can be calculated by: CCOMP > 100 ⋅ g M 2.5 ⋅ 2π ⋅ 2 f LINE VO.PFC.H (19) RCS1 = 0.85 0.85 = = 0.2Ω I L. PK (1 + K MARGIN ) 3.14(1 + 0.35) To improve the power factor, CCOMP must be higher than the calculated value. However, if the value is too high, the output voltage control loop may become slow. (Design Example) CCOMP > = 100 ⋅ g M 2.5 ⋅ 2π ⋅ 2 f LINE VO.PFC . H [STEP-A5] Output Capacitor Selection For a given minimum PFC output voltage during the holdup time, the PFC output capacitor is obtained as: CO.PFC 2 POUT ⋅ tHOLD > VO.PFC .L 2 − VO.PFC , HLD 2 (18) 100 ⋅125 ×10−6 2.5 ⋅ = 103nF 2π ⋅ 2 ⋅ 60 400 where: POUT is total nominal output power; tHOLD is the required holdup time; and VO.PFC,HLD is the allowable minimum output voltage during the hold-up time. For PFC output capacitor, it is typical to use 0.5~1µF per 1W output power for 400V PFC output. Meanwhile, it is reasonable to use about 1µF per 1W output power for variable output PFC due to the larger voltage drop during the hold-up time than 400V output. (Design Example) Assuming the minimum allowable PFC output voltage during the hold-up time is 160V, the capacitor should be: CO.PFC > 2 POUT ⋅ t HOLD VO.PFC .H 2 − VO. PFC .HLD 2 = 2 ⋅ 90 ⋅ 20 × 10−3 2582 − 1602 = 88μ F 470nF is selected for better power factor. A 100μF capacitor is selected for the output capacitor. The minimum PFC output voltage during the hold-up time is: VO.PFC .HOLD = VOUT 2 − = 2582 − 2 POUT ⋅ t HOLD COUT = 175V 2 ⋅ 90 ⋅ 20 × 10−3 100 × 10 −6 © 2010 Fairchild Semiconductor Corporation Rev. 1.0.1 • 8/24/10 www.fairchildsemi.com 7 AN-6921 APPLICATION NOTE Part B. DC/DC Section [STEP-B1] Determine the Reflected Output Voltage (VRO) Figure 11 shows the typical operation waveforms of a quasiresonant flyback converter. When the MOSFET is turned off, the input voltage (PFC output voltage), together with the output voltage reflected to the primary (VRO), is imposed on the MOSFET. When the MOSFET is turned on, the sum of input voltage reflected to the secondary side and the output voltage is applied across the diode. Thus, the maximum nominal voltage across the MOSFET (Vdsnom) and diode are given as: (Design Example) Assuming 650V MOSFET and 100V MOSFET are used for primary side and secondary side, respectively, with 18% voltage margin: 0.82 ⋅ 650V > VDS nom = VO. PFC + VRO ∴VRO < 0.82 ⋅ 650 − VO.PFC = 133V 0.82 ⋅ 100 > VD nom = VO + ∴ VRO > VD nom = VO . PFC (VO + VF ) VRO VDS nom = VO . PFC . H + n(VO + VF ) = VO . PFC . H + VRO where: (20) VO . PFC (VO + VF ) = 121V 0.82 ⋅ 100 − VO VRO is determined as 130V. VRO n= VO + VF VD nom = VO + VO . PFC . H V = VO + O . PFC . H (VO + VF ) n VRO (21) By increasing VRO (i.e. the turns ratio, n), the capacitive switching loss and conduction loss of the MOSFET are reduced. This also reduces the voltage stress of the secondary-side rectifier diode. However, this increases the voltage stress on the MOSFET. Therefore, VRO should be determined by a trade-off between the voltage stresses of the MOSFET and diode. It is typical to set VRO such that VDSnorm and VDnom are 75~85% of their voltage ratings. [STEP-B2] Transformer Design Figure 12 shows the typical switching timing of a quasiresonant converter. The sum of MOSFET conduction time (tON), diode conduction time (tD), and drain voltage falling time (tF) is the switching period (tS). To determine the primary-side inductance (Lm), the following parameters should be determined first. Minimum Switching Frequency (fS.QRmin) The minimum switching frequency occurs at the minimum input voltage and full-load condition, which should be higher than 20kHz to avoid audible noise. By increasing fS.QRmin, the transformer size can be reduced. However, this results in increased switching losses. Determine fS.QRmin by a trade-off between switching losses and transformer size. Typically fS.QRmin is set to around 50kHz. Falling Time of the MOSFET Drain Voltage (tF) As shown in Figure 12, the MOSFET drain voltage fall time is half of the resonant period of the MOSFET’s effective output capacitance and primary-side inductance. The typical value for tF is 0.6~1.2µs. Non-Conduction Time of the MOSFET (tOFF) FAN6921 has a minimum non-conduction time of MOSFET (8µs), during which turning on of MOSFET is prohibited. To maximize the efficiency, it is necessary to turn on the MOSFET at the first valley of MOSFET drain-to-source voltage at heavy-load condition. Therefore, the MOSFET non-conduction time at heavy load condition should be larger than 8µs. After determining fS.QRmin and tF, the maximum duty cycle is calculated as: Dmax = VRO ⋅ (1 − f S .QR min ⋅ t F ) VRO + VO.PFC .L (22) Then, the primary-side inductance is obtained as: Lm = ηQR ⋅ (VO. PFC .L ⋅ Dmax ) 2 2 ⋅ f S .QR min POUT (23) Figure 11. Typical Waveforms of QR Flyback Converter © 2010 Fairchild Semiconductor Corporation Rev. 1.0.1 • 8/24/10 www.fairchildsemi.com 8 AN-6921 APPLICATION NOTE Once Lm is determined, the maximum peak current and RMS current of the MOSFET in normal operation are obtained as: Once the minimum number of turns for the primary side is determined, calculate the proper integer for NS so that the resulting NP is larger than Npmin as: I DS PK = VO.PFC .L ⋅ Dmax Lm f S .QR min Dmax 3 (24) N P = n ⋅ N S > N P min (29) The number of turns of the auxiliary winding for VDD is given as: (25) I DS RMS = I DS PK N AUX = The MOSFET non-conduction time at heavy load and low line is obtained as: VDD nom + VFA ⋅ NS (VO + VF ) (30) tOFF .L = (1 − Dmax ) f S .QR min where VDDnom is the nominal VDD voltage, which is typically 18V and VFA is forward voltage drop of VDD diode. Once the number of turns of the primary winding is determined, the maximum flux density when the drain current reaches its pulse-by-pulse current limit level should be checked to guarantee the transformer is not saturated during transient or fault condition. The maximum flux density (Bmax) when drain current reaches ILIM is given as: (26) The MOSFET non-conduction time at heavy load and high line is obtained as: tOFF .H = tOFF .L ⋅ VO.PFC . L VO.PFC . H + VRO ⋅ VO. PFC .H VO.PFC .L + VRO (27) To guarantee the first valley switching at high line and heavy-load condition, tOFF.H should be larger than 8µs. Bmax = Lm I LIM < Bsat Ae N P (31) Bmax should be smaller than the saturation flux density. If there is no reference data, use Bsat =0.35~0.40T. (Design Example) Setting the minimum frequency is 52kHz and the falling time is 0.8µs: Dmax = = VRO ⋅ (1 − f S .QR min ⋅ tF ) VRO + VO.PFC .L 130 ⋅ (1 − 52 ×103 ⋅ 0.8 ×10−6 ) = 0.319 130 + 260 Lm = = Figure 12. Switching Timing of QR Flyback Converter ηQR ⋅ (VO.PFC .L ⋅ Dmax ) 2 2 ⋅ f S .QR min PO 0.95 ⋅ (260 ⋅ 0.319)2 = 700μ H 2 ⋅ 52 ×103 ⋅ 90 When designing the transformer, the maximum flux density swing in normal operation (B) as well as the maximum flux density in transient (Bmax) should be considered. The maximum flux density swing in normal operation is related to the hysteresis loss in the core, while the maximum flux density in transient is related to the core saturation. The minimum number of turns for the transformer primary side to avoid the over temperature in the core is given by: I DS PK = tOFF .L = 260 ⋅ 0.319 = 2.28 A 700 ×10−6 ⋅ 52 ×103 (1 − Dmax ) 1 − 0.319 = = 13μ s f S .DD min 52 ×103 VO.PFC. L VO.PFC. H + VRO ⋅ VO.PFC.H VO.PFC .L + VRO 260 400 + 130 ⋅ = 11.48μ s > 8μ s 400 260 + 130 tOFF . H = tOFF . L ⋅ = 13μ s ⋅ NP min L I PK = m DS Ae ΔB (28) where B is the maximum flux density swing in Tesla. If there is no reference data, use B =0.25~0.30T. Assuming POT3319 (Ae=159mm2) core is used and the flux swing is 0.26T © 2010 Fairchild Semiconductor Corporation Rev. 1.0.1 • 8/24/10 www.fairchildsemi.com 9 AN-6921 APPLICATION NOTE N P min = Lm I DS PK 700 ×10−6 ⋅ 2.28 = = 38.6 159 ×10−6 ⋅ 0.26 Ae ΔB N P = n ⋅ N S = 6.84 ⋅ 5 = 34 < N P min = n ⋅ N S = 6.84 ⋅ 6 = 41 > N P min N AUX = VDD nom + VFA 18 + 1.2 ⋅ NS = ⋅6 = 6 (VO + VF ) 19 VO ⋅ NA NS Assuming the pulse-by-pulse current limit for low PFC output voltage is 125% of peak drain current at heavy load: − PFC _ VO ⋅ NA NP Bmax LI 700 ⋅ 2.28 ⋅1.25 = m LIM = = 0.31T 159 ⋅ 41 Ae N P VO ⋅ NA RA ⋅ N S RDET + RA [STEP-B3] Design the Valley Detection Circuit The valley of MOSFET voltage is detected by monitoring the current flowing out of DET pin. The typical application circuit is shown as Figure 13 and typical waveforms are shown in Figure 14. The DET pin has upper and lower voltage clamping at 5V and 0.7V, respectively. The valley detection circuit is blanked for 8µs after the MOSFET is turned off. When VAUX drops below zero, VDET is clamped at 0.7V and current flows out of the DET pin. MOSFET is turned on with 200ns time delay once the current flowing out of DET pin exceeds 30µA. To guarantee that valley detection circuit is triggered when DET pin is clamped at 0.7V, the current flowing through RDET2 should be larger than 30µA as: 0.7 > 30μ A RDET 2 (32) Figure 14. Waveforms of Valley Detection and VO OVP Detection The output voltage is indirectly monitored for over-voltage protection using the DET pin voltage while the MOSFET is turned off. Thus, the ratio of RDET1 and RDET2 should be determined as: 2 .5 = RDET 2 NA NA 1 VOVP = VOVP RDET 1 + RDET 2 N S K DET + 1 N S (33) where the ratio between RDET1 and RDET2 is obtained as: K DET = RDET 1 N A VOVP = ⋅ −1 RDET 2 N S 2.5 (34) For a quasi-resonant flyback converter, the peak drain current with a given output power decreases as input voltage increases. Thus, constant power limit cannot be achieved by just using pulse-by-pulse current limit with constant threshold. FAN6921 has high/low line over power compensation that reduces the pulse-by-pulse current limit level as input voltage increases. FAN6921 senses the input voltage using the current flowing out of the DET pin while the MOSFET is turned on. The pulse-by-pulse current limit level vs. DET current is depicted in Figure 16. The DET pin current for low line and high line PFC output voltages are given as: VO. PFC . L I DET .L = NA +0.7 NP NA +0.7 NP RDET 1 VO.PFC .H + 0.7 ≅ RDET 2 0. 7 ≅ RDET 2 VO. PFC .L NA NP NA NP (35) RDET 1 VO.PFC .H (36) Figure 13. Typical Application Circuit of DET Pin I DET .H = RDET 1 + RDET 1 © 2010 Fairchild Semiconductor Corporation Rev. 1.0.1 • 8/24/10 www.fairchildsemi.com 10 AN-6921 APPLICATION NOTE (38), considering the pulse-by-pulse turn-off delay and increased PFC output voltage ripple at low line. Once the current limit threshold voltage is determined with RDET1, the current sensing resistor value is obtained as: VO . PFC . L VLIMIT = −877 ⋅ ( NA +0.7 NP 0.7 ) + 0.882 RDET 2 (40) RDET 1 + The current sensing resistor value can be obtained from: V RCS 2 = LIMIT (41) I DS LIM Figure 15. Switching Frequency and Peak Drain Current Change as Input Voltage Increases (Design Example) 0 .7 > 30 μ A , RDET 2 < 23.3k Ω RDET 2 0.9 0.85 0.8 0.75 Setting the OVP trip point at 22.5V, K DET = RDET 1 N A VOVP 6 22.5 = ⋅ −1 = ⋅ −1 = 8 RDET 2 NS 2.5 6 2.5 VLIMIT (V) 0.7 0.65 V Then RDET 1 = K DET ⋅ RDET 2 < 196k Ω 0.6 0.55 0.5 0.45 0.4 0 50 100 150 200 250 300 350 400 450 500 550 600 I DS PK . L VO . PFC . H VO . PFC . L + VRO = ⋅ I DS PK . H VO . PFC . L VO . PFC . H + VRO = 400 260 + 130 ⋅ = 1.13 260 400 + 130 Using 116% of 1.13, IDET (µA) Figure 16. IDET-VLIMIT Curve N −994VO.PFC .L A + RDET 1 VLIMIT .L NP = 1.31 ≅ N VLIMIT . H −994 ⋅ VO. PFC .H A + RDET 1 NP 260 + RDET 1 −38, 018 + RDET 1 6.8 = = 400 −994 ⋅ + RDET 1 −58, 490 + RDET 1 6.8 −994 ⋅ The relationship between IDET and VLIMIT in the linear region (IDET=100~500µA) can be approximated as: VLIMIT = −877 ⋅ I DET + 0.882 (37) For a given output power, the ratio between drain peak currents at low line and highline is obtained as: Then, RDET 1 = 124.5k Ω and RDET 2 = 15.6k Ω RDET1 and RDET2 are selected from the off-the-shelf components as 120kΩ and 15kΩ, respectively. Then, the pulse by pulse current limit threshold voltage is obtained as: VO. PFC . L VLIMIT = −877 ⋅ ( = 0.56V NA + 0.7 NP 0.7 ) + 0.882 RDET 2 I DS PK . L VO . PFC . H VO . PFC . L + VRO = ⋅ I DS PK . H VO . PFC . L VO . PFC . H + VRO (38) For a given output power, the ratio between pulse-by-pulse current limit levels at low line and high line is obtained as: −994 ⋅VO. PFC . L VLIMIT . L ≅ VLIMIT . H −994 ⋅ V O . PFC . H NA + RDET 1 NP NA + RDET 1 NP RDET 1 + (39) To set current limit level at low line as 125% of IDSPK 0.56 = 0.2Ω 2.28 A × 1.25 To get a constant power limit, RDET1 should be determined such that Equations (38) and (39) are equal. However, for actual design, it is typical to use 105~120% of Equation © 2010 Fairchild Semiconductor Corporation Rev. 1.0.1 • 8/24/10 www.fairchildsemi.com 11 AN-6921 APPLICATION NOTE [STEP-B4] Design the Feedback Circuit Figure 17 is a typical feedback circuit mainly consisting of a shunt regulator and a photo-coupler. R01 and R02 form a voltage divider for output voltage regulation. RF and CF are adjusted for control-loop compensation. A small-value RC filter (e.g. RFB = 100Ω, CFB = 1nF) placed from the FB pin to GND can increase stability substantially. The maximum source current of the FB pin is about 1.2mA. The phototransistor must be capable of sinking this current to pull the FB level down at no load. The value of the biasing resistor, RBIAS, is determined as: [STEP-B5] Design the Over-Temperature Protection Circuit The adjustable Over-Temperature Protection (OTP) circuit is shown in Figure 18. As can be seen, a constant sourcing current source (IRT) is connected to the RT pin. Once VRT is lower than 0.8V for longer than 10ms debounce time, FAN6921 is latched off. RRT can be determined by: 0.8V = ( RRT + RNTC @ OT ) × 100 μ A (43) VO − VOPD − VKA ⋅ CTR > 1.2 × 10 −3 RBIAS (42) where VOPD is the drop voltage of photodiode, about 1.2V; VKA is the minimum cathode to anode voltage of shunt regulator (2.5V); and CTR is the current transfer rate of the opto-coupler. Figure 18. Adjustable Over-Temperature Protection and External Latched-off Function (Design Example) Assuming the resistance of NTC at over-temperature protection point is 4.3kΩ; RRT = 0.8V - 4.3k Ω = 3.7kΩ 100μ A Figure 17. Feedback Circuit (Design Example) Assuming CTR is 100%; VO − VOPD − VKA ⋅ CTR > 1.2 × 10−3 RBIAS RBIAS < VO − VOPD − VKA 19 − 1.2 − 2.5 = = 12.75k Ω 1.2 ×10−3 1.2 × 10−3 220Ω resistor is selected for RBIAS. The voltage divider resistors for VO sensing are selected as 68kΩ and 10kΩ. © 2010 Fairchild Semiconductor Corporation Rev. 1.0.1 • 8/24/10 www.fairchildsemi.com 12 AN-6921 APPLICATION NOTE Final Schematic of Design Example This section summaries the final design example. The key system specifications are summarized in Table 1 and the key design parameters are summarized in Table 2. The final schematic is in Figure 19. To have enough hold-up time for VDD during startup, a two-stage circuit is used for VDD. Table 1. System Specifications Input Input Voltage Range Line Frequency Range Output Output Voltage (Vo) Output Power (Po) 19V 90W 90~264VAC 47~63Hz Table 2. Key Design Parameters PFC Stage PFC Output Voltage Level 1 (VO.PFC.L) 260V PFC Output Voltage Level 2 (VO.PFC.L) 400V PFC Inductor (LBOOST) 385µH Turns of PFC Inductor (NBOOST) 60T Turns of ZCD Auxiliary Winding (NZCD) 8T min Minimum Switching Frequency (fS.PFC ) 55kHz PWM Stage Turns of Primary Inductor of PWM Transformer (NP) 41T Turns of Auxiliary Winding of PWM Transformer 6T (NAUX) Turns Ratio of PWM Transformer (n) 6.8 Primary Inductor (LP) 700µH min Minimum switching Frequency (fs.QR ) 52kHz Figure 19. Final Schematic of Design Example © 2010 Fairchild Semiconductor Corporation Rev. 1.0.1 • 8/24/10 www.fairchildsemi.com 13 AN-6921 APPLICATION NOTE Lab Note Before modifying or soldering/desoldering the power supply, discharge the primary capacitors through the external bleeding resistor. Otherwise, the PWM IC may be damaged by external high-voltage. This device is sensitive to electrostatic discharge (ESD). To improve the production yield, the production line should be ESD protected as required by ANSI ESD S1.1, ESD S1.4, ESD S7.1, ESD STM 12.1, and EOS/ESD S6.1 standards. Printed Circuit Board Layout Printed circuit board layout and design are very important for switching power supplies where the voltage and current change with high dv/dt and di/dt. Good PCB layout minimizes EMI and prevents the power supply from being disrupted during surge/ESD tests. System Side PFC Stage Guidelines IC Side: Reference ground of the COMP, INV, CSPFC, and CSPWM pins are connected together and then connect to IC’s GND directly. Reference ground of VIN, RT, FB, and DET pins are connected to IC’s GND directly. Small capacitors around IC should be connected to IC directly. The trace line of CSPFC, CSPWM, OPFC, and OPWM should not be paralleled and should be close to each other to avoid introducing noise. Connections of IC’s GND, CBulk’s ground, and auxiliary winding of PWM XFMR: Approach 1: Auxiliary winding’s ground IC’s CBulk’s ground. GND Approach 2: IC’s GND Auxiliary winding’s CBulk’s ground (Trace 2 Trace 1 ground Trace 3). Approach 3: IC’s GND CBulk’s ground and CBulk’s ground. auxiliary winding’s ground Auxiliary winding of PFC choke and RCS,PFC should be connected to CBulk’s ground singly (Trace 4 and Trace 5). Ground of bridge and the C-L-C filter should be connected to CBulk’s ground directly. Current loop constructed by the PFC choke, PFC diode, PFC MOSFET, RCS,PFC, and CBulk should be as short as possible (Loop 7). PWM Stage RCS should be connected to CBulk’s ground directly. Keep it short and wide (Trace 6). Current loop constructed by the CBulk, XFMR, PWM MOSFET, and RCS should be as short as possible (Loop 8). RCD snubber should be close to XFMR and drain of PWM MOSFET. Ground of photo-coupler should be connected to IC’s GND. On the secondary side, current loop constructed by XFMR, Schottky, and output capacitor should be as short as possible (Loop 9). Connections of Y Capacitor: Approach 1: Y CAP’s primary ground ground bridge’s ground. Approach 2: Y CAP’s primary ground CBulk’s ground. ground CBulk’s bridge’s © 2010 Fairchild Semiconductor Corporation Rev. 1.0.1 • 8/24/10 www.fairchildsemi.com 14 AN-6921 APPLICATION NOTE Figure 20. Layout Considerations © 2010 Fairchild Semiconductor Corporation Rev. 1.0.1 • 8/24/10 www.fairchildsemi.com 15 AN-6921 APPLICATION NOTE Related Documents FAN6921MR — Integrated Critical Mode PFC and Quasi-Resonant Current Mode PWM Controller FAN6921ML — Integrated Critical Mode PFC/Quasi-Resonant Current Mode PWM Controller DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. © 2010 Fairchild Semiconductor Corporation Rev. 1.0.1 • 8/24/10 www.fairchildsemi.com 16