AN-8033

www.fairchildsemi.com Application Note AN-8033 Design Guideline for Primary Side Regulated (PSR) Flyback Converter Using FAN103 and FSEZ13X7 1. Introduction More than half of the external power supplies are used for portable electronics such as laptops, cellular phones, and MP3 players and; therefore, have output voltage and output current regulation capabilities for battery charging. In applications where precise output current regulation is required, current sensing in the secondary side is always necessary, which results in additional sensing loss. For power supply designers struggling in an environment of increasing regulatory pressures, the output current sensing is a daunting design challenge. Primary-side regulation (PSR) for power supplies can be an optimal solution for alleviating the burden of achieving international energy efficiency regulations (California Energy Commission (CEC) and Energy Star) in charger designs. The primary-side regulation controls the output voltage and current precisely with the information in the primary side of the power supply only, not only removing the output current sensing loss, but also eliminating all secondary-feedback circuitry. This facilitates a higher efficiency power supply design without incurring tremendous costs. Fairchild Semiconductor PWM PSR controller FAN103 and Fairchild Power Switch (FPS) (MOSFET + Controller, EZ-PSR) FSEZ13X7 significantly simplify the challenge of meeting tighter efficiency requirements while eliminating external components. FAN103 and FSEZ13x7 also have an integrated output cable voltage drop compensation and external component temperature variation compensation circuit, which allows high accuracy even at the end of the output cable for charger applications. This application note presents practical design considerations for battery chargers employing Fairchild Semiconductor PWM PSR controller FAN103 and Power Switch (MOSFET + Controller, EZ-PSR) FSEZ13X7. It includes designing the transformer and output filter, selecting the components, and implementing constantcurrent / constant-voltage control. The step-by-step design procedure described helps engineers design a power supply more easily. The design procedure is verified through an experimental prototype converter using FSEZ1317. Figure 1 shows the typical application circuit of primary-side controlled flyback converter using FSEZ1317. Figure 1. Typical Application Circuit of FSEZ1317 © 2009 Fairchild Semiconductor Corporation Rev. 1.0.1 • 5/6/10 www.fairchildsemi.com AN-8033 2. Operation Principle of PrimarySide Regulation Figure 2 shows the simplified circuit diagram of a primaryside regulated flyback converter and its typical waveforms are shown in Figure 3. Generally, discontinuous conduction mode (DCM) operation is preferred for primary-side regulation since it allows better output regulation. The key of primary-side regulation is how to obtain output voltage and current information without directly sensing them. Once these values are obtained, the control can be accomplished by the conventional feedback compensation method. The operation principles of DCM flyback converter are as follows: During the MOSFET ON time (tON), input voltage (VDL) is applied across the primary-side inductor (Lm). Then, MOSFET current (Ids) increases linearly from zero to the peak value (Ipk). During this time, the energy is drawn from the input and stored in the inductor. When the MOSFET is turned off, the energy stored in the inductor forces the rectifier diode (D) to be turned on. During the diode conduction time (tD), the output voltage (Vo), together with diode forward-voltage drop (VF), are applied across the secondary-side inductor (Lm×Ns2/ Np2) and the diode current (ID) decreases linearly from the peak value (Ipk× Np/Ns) to zero. At the end of tD, all the energy stored in the inductor has been delivered to the output. When the diode current reaches zero, the transformer auxiliary winding voltage (Vw) begins to oscillate by the resonance between the primary-side inductor (Lm) and the MOSFET output capacitor. During the diode conduction time, the sum of output voltage and diode forward-voltage drop is reflected to the auxiliary winding side as (Vo+VF)× Na/Ns. Since the diode forward-voltage drop decreases as current decreases, the auxiliary winding voltage reflects the output voltage best at the end of diode conduction time where the diode current diminishes to zero. By sampling the winding voltage at the end of the diode conduction time, the output voltage information can be obtained. The internal error amplifier for output voltage regulation (EA_V) compares the sampled voltage with internal precise reference to generate an error voltage (VCOMV), which determines the duty cycle of the MOSFET, as shown in Figure 2. Meanwhile, the output current can be estimated through calculation. Assuming that output current is same as the average of the diode current in steady state, the output current can be estimated as: I O = I PK N P tD • N S 2t S The output current estimator picks up the peak value of the drain current with a peak detection circuit and calculates the output current using the diode conduction time (tD) and switching period (ts). These output information is compared with internal precise reference to generate error voltage (VCOMI), which determines the duty cycle of the MOSFET, as shown in the block diagram of Figure 2. Among the two error voltages, VCOMV and VCOMI, the smaller one actually determines the duty cycle. Therefore, during constant voltage regulation mode, VCOMV determines the duty cycle while VCOMI is saturated to HIGH. During constant current regulation mode, VCOMI determines the duty cycle while VCOMV is saturated to HIGH. Figure 2. Primary-Side Regulated Flyback Converter I pk I pk ⋅ Np Ns I D.avg = I o VF ⋅ Na Ns VO ⋅ Na Ns (1) Figure 3. Key Waveforms of Primary-Side Regulated Flyback Converter © 2009 Fairchild Semiconductor Corporation Rev. 1.0.1 • 5/6/10 www.fairchildsemi.com 2 AN-8033 3. Design Consideration Converters with Constant Current (CC) output require more design consideration than the conventional power supply design with a fixed output voltage. In CC operation, the voltage for control IC (VDD), which is usually obtained with an auxiliary winding of the transformer, changes with the output voltage. Thus, the VDD operation range determines the constant current control range. FAN103 and FSEZ13X7 have a wide supply voltage (VDD) operation range from 5V up to 24V, which allows stable CC regulation even with output voltage lower than a quarter of its nominal value. Another important design consideration for CC operation is that the transformer should be designed to guarantee DCM operation in all operation range since the output information is properly obtained only in DCM operation, as described in Section 2. As seen in Figure 4, the MOSFET conduction time (tON) decreases as output voltage decreases in CC mode. Meanwhile, the diode conduction time (tD) increases as the output voltage decreases. Since the increase of tON is dominant to the decrease of tON in determining the sum of tON and tD, the converter tends to enter CCM as output voltage decreases. FAN103 and FSEZ13X7 have a frequency reduction function to prevent CCM operation by extending the switching period, which is activated when the output voltage drops below 70% of its nominal value, as depicted in Figure 5. Therefore, 70% of output voltage and minimum output voltage are the two worst cases for the transformer design. The transformer should be designed for DCM both at 70% of nominal output voltage and minimum output voltage. Once the converter is designed to operate in DCM at 70% of nominal output voltage and minimum output voltage, DCM operation is guaranteed for entire load range. V ds IPK I ds tON tD V ds I ds IPKCC tDCC tONCC VO CC = VO / k Figure 4. TON CC = TON / k TD CC = TD ⋅ k tON and tD Change as Output Voltage Decreases Figure 5. Operation Range of Charger with CC/CV © 2009 Fairchild Semiconductor Corporation Rev. 1.0.1 • 5/6/10 www.fairchildsemi.com 3 AN-8033 4. Design Procedure In this section, a design procedure is presented using the schematic of Figure 6 as a reference. An offline charger with 3.75W/5V output has been selected as a design example. The design specifications are as follows: Line voltage range: 90~264VAC and 60Hz Nominal output voltage and current: 5V/0.75A Output voltage ripple: less than 150mV Minimum output voltage in CC mode: 25% of nominal output (1.25V) Table 1.Typical Efficiency of Flyback Converter Output Voltage Typical Efficiency for Universal Input Typical Efficiency for European Input 3.3~6V 6~12V 12~24V 65~70% 70~77% 77~82% 67~72% 72~79% 79~84% Figure 7. Definition of Primary- and SecondarySide Efficiency With the estimated overall efficiency, the input power at nominal output is given as: PIN = Figure 6. Output Voltage and Current Operating Area VO I O N N η (4) [STEP-1] Estimate the Efficiencies A charger application has output voltage and current that change over wide range as shown in Figure 6. To optimize the power stage design, the efficiencies and input powers should be specified for operating point A (nominal output voltage and current), B (70% of nominal output voltage), and C (minimum output voltage), respectively. Estimated overall efficiency (η) for operating points A, B, and C: The overall power conversion efficiency should be estimated to calculate the input power. If no reference data is available, use the typical efficiency in Table 1. Estimated primary-side efficiency (ηP) and secondaryside efficiency (ηS) for operating points A, B, and C. Figure 7 shows the definition of primary-side and secondary-side efficiencies, where the primary-side efficiency is for the power transfer from AC line input to the transformer primary side, while the secondaryside efficiency is for the power transfer from the transformer primary side to the power supply output. The typical values for the primary-side and secondaryside efficiencies are given as: where VON and ION are the nominal output voltage and current, respectively. Then, the input power of transformer at nominal output is given as: PIN .T = VO N I O N ηS (5) As mentioned in previous section, when the output voltage drops below 70% of its nominal value, the frequency is reduced to 33kHz to prevent CCM operation. Thus, the transformer should be designed for DCM both at 70% of nominal output voltage and minimum output voltage. As output voltage reduces in CC mode, the efficiency also drops. To optimize the transformer design, it is required to estimate the efficiencies properly at 70% of nominal output voltage and minimum output voltage conditions. The overall efficiency at 70% of nominal output voltage (operating point B) can be approximated as: η@ B ≅ η ⋅ 0.7 ⋅ VO N 0.7 ⋅VO + VF N ⋅ VO N + VF VO N (6) where VF is diode forward-voltage drop. The secondary-side efficiency at 70% of nominal output voltage (operating point B) can be approximated as: η S @ B ≅ ηS ⋅ 0.7 ⋅VO N 0.7 ⋅VO N + VF ⋅ VO N + VF VO N ηP ηP 1 ≅ η 3 ,η S 2 ≅η3 1 ≅η3 : output voltage < 10V : output voltage > 10V (2) (3) 2 ≅ η 3 ,η (7) S © 2009 Fairchild Semiconductor Corporation Rev. 1.0.1 • 5/6/10 www.fairchildsemi.com 4 AN-8033 Then, the power supply input power and transformer input power at 70% nominal output voltage (operating point B) are given as: PIN @ B = 0.7 ⋅ VO N ⋅ I O N PIN .T @ B = 0.7 ⋅ VO I O N N ηS @ B = 3.47W η@ B (8) N The efficiencies at the minimum output voltage are: PIN .T @ B = 0.7 ⋅ VO ⋅ I O N η@ C ≅ η ⋅ (9) ηS @ B VO min V N +V ⋅ O N F = 0.540 VO min + VF VO VO min V N +V ⋅ O N F = 0.608 VO min + VF VO IO N IO N The overall efficiency at the minimum output voltage (operating point C) can be approximated as: η@ C ≅ η ⋅ VO min VO min + VF min ηS @ C ≅ ηS ⋅ ⋅ VO N + VF VO N (10) The input powers of the power supply and transformer at the minimum output voltage are obtained as: PIN @ C = VO min where Vo is the minimum output voltage. η@ C min = 1.74W = 1.54W The secondary-side efficiency at minimum output voltage (operating point C) can be approximated as: η S @ C ≅ ηS ⋅ VO min VO min PIN .T @ C = VO + VF ⋅ VO N + VF VO N ηS @C (11) Then, the power supply input power and transformer input power at the minimum output voltage (operating point C) are given as: PIN @ C = VO min ⋅ I O N [STEP-2] Determine the DC Link Capacitor (CDL) and the DC Link Voltage Range It is typical to select the DC link capacitor as 2-3µF per watt of input power for universal input range (90-265VRMS) and 1µF per watt of input power for European input range (195V~265VRMS). With the DC link capacitor chosen, the minimum DC link voltage is obtained as: η@ C (12) (13) PIN .T @ C = VO min ⋅ I O N ηS @C (Design Example) VDL min = 2 ⋅ (VLINE min ) 2 − Assuming the overall efficiency is 70% at operating point A (nominal output voltage and current), the secondary-side efficiency is obtained as: 2 2 PIN (1 − Dch ) CDL ⋅ f L (14) η S ≅ η 3 = 0.7 3 = 0.788 Then, the input powers of the power supply and transformer are obtained as: PIN = PIN .T where VLINEmin is the minimum line voltage, CDL is the DC link capacitor, fL is the line frequency, and Dch is the DC link capacitor charging duty ratio defined as shown in Figure 8, which is typically about 0.2. The maximum DC link voltage is given as: VDL max = 2 ⋅ VLINE max where VLINEmax is the maximum line voltage. (15) 3.75 = 5.36W η 0.7 P 3.75 = OUT = = 4.76W η S 0.7 2 / 3 VO I O N N = The minimum input DC link voltage at 70% nominal output voltage are given as: The efficiencies at 70% of nominal output voltage are: VDL @ B min = 2 ⋅ (VLINE min ) 2 − PIN @ B (1 − Dch ) CDL ⋅ f L (16) η@ B ≅ η ⋅ 0.7 ⋅VO N V N +V ⋅ O N F = 0.67 0.7 ⋅ VO N + VF VO 0.7 ⋅ VO N V N +V ⋅ O N F = 0.756 0.7 ⋅ VO N + VF VO The minimum input DC link voltage at minimum output voltage are given as: ηS @ B ≅ ηS ⋅ VDL @ C min = 2 ⋅ (VLINE min ) 2 − PIN @ C (1 − Dch ) CDL ⋅ f L (17) Then, the input powers of the power supply and transformer at 70% of nominal output voltage are obtained as: PIN @ B = 0.7 ⋅ VO N η@ B IO N = 3.91W www.fairchildsemi.com 5 © 2009 Fairchild Semiconductor Corporation Rev. 1.0.1 • 5/6/10 AN-8033 VD nom = NS VDL max + VO NP (20) Figure 8. DC Link Voltage Waveforms (Design Example) By choosing two 4.7µF capacitors in parallel for the DC link capacitor, the minimum and maximum DC link voltage for each condition are obtained as: As observed in Equations (6) and (7), increasing the transformer turns ratio (Np/Ns) results in increased voltage of MOSFET, while it leads to reduced voltage stress of rectifier diode. Therefore, the transformer turns ratio (Np/Ns) should be determined by the compromise between MOSFET and diode voltage stresses. When determining the transformer turns ratio, the voltage overshoot on drain voltage should be also considered. The maximum voltage stress of MOSFET is given as: VDS max = VDL max + VRO + VOS (21) VDL min = 2 ⋅ (VLINE min )2 − = 2 ⋅ (90)2 − PIN (1 − Dch ) CDL ⋅ f L Vin max 5.36(1 − 0.2) = 93V 2 ⋅ 4.7 × 10−6 ⋅ 60 = 2 ⋅ 264 = 373V For reasonable snubber design, voltage overshoot (VOS) is typically 1~1.5 times of the reflected output voltage. It is also typical to have a margin of 15~20% of breakdown voltage for maximum MOSFET voltage stress. VDL @ B min = 2 ⋅ (VLINE min ) 2 − = 2 ⋅ (90) 2 − PIN @ B (1 − Dch ) CDL ⋅ f L 3.91(1 − 0.2) = 103V 2 ⋅ 4.7 ×10−6 ⋅ 60 PIN @ C (1 − Dch ) CDL ⋅ f L VDL @ C min = 2 ⋅ (VLINE min ) 2 − = 2 ⋅ (90) 2 − 1.74(1 − 0.2) = 117V 2 ⋅ 4.7 ×10−6 ⋅ 60 [STEP-3] Determine the Transformer Turns Ratio Figure 9 shows the MOSFET drain-to-source voltage waveforms. When the MOSFET is turned off, the sum of the input voltage (VDL) and the output voltage reflected to the primary is imposed across the MOSFET as: NP (VO + VF ) NS VDL VDS nom = VDL max + VRO where VRO is reflected output voltage defined as: (18) Figure 9. Transformer Turns Ratio and Voltage Stress on MOSFET and Diode VRO = Np Ns (VO + VF ) (19) where VF is the diode forward voltage drop and NP and NS are number of turns for primary side and secondary side, respectively. When the MOSFET is turned on, the output voltage, together with input voltage reflected to the secondary, are imposed across the diode as: The transformer turns ratio between the auxiliary winding and secondary winding (Na/Ns) should be determined by considering the permissible IC supply voltage (VDD) range and minimum output voltage in CC mode. When the power supply operates in constant current (CC) mode, VDD changes, together with the output voltage, as seen in Figure 10. The overshoot of auxiliary winding voltage caused by the leakage inductance also affects the VDD. VDD voltage at light-load condition, where the overshoot of auxiliary winding voltage is negligible, is given as: www.fairchildsemi.com 6 © 2009 Fairchild Semiconductor Corporation Rev. 1.0.1 • 5/6/10 AN-8033 VDD min1 = Na (Vo + VF ) − VFa NS (22) VDD min1 = Na (5 + 0.55) − 0.7 > 5.5 + 3 NS ∴ The actual VDD voltage at heavy load is higher than Equation (8) due to the overshoot by the leakage inductance, which is proportional to the voltage overshoot of MOSFET drain-to-source voltage shown in Figure 10. Considering the effect of voltage overshoot, the VDD voltages for nominal output voltage and minimum output voltage are given as: Na > 1.66 NS Na 1 (5 + 0.55 + 72) − 0.7 < 24 NS 13 VDD max = VDD max ≅ VDD min 2 Na N (VO + VF + S VOS ) − VFa NS NP N N ≅ a (VO min + VF + S VOS ) − VFa NS NP (23) (24) Na < 2.23 NS N 1 VDD min 2 = a (1.25 + 0.55 + 72) − 0.7 > 5.5 13 NS N ∴ a > 0.84 NS ∴ To minimize the power consumption of PWM IC, it is required to keep VDD as low as possible. Therefore, Na/Ns is determined as 1.66. where VFa is the diode forward-voltage drop of auxiliary winding diode. [STEP-4] Design the Transformer Figure 11 shows the definition of MOSFET conduction time (tON), diode conduction time (tD) and non-conduction time (tOFF). The sum of MOSFET conduction time and diode conduction time at 70% of nominal output voltage is obtained as: TON + TD = TON (1 + min N S VDL @ B ) ⋅ N P 0.7 ⋅ VO + VF (25) The first step to design the transformer is to determine how much non-conduction time (tOFF) is allowed in DCM operation. Once the tOFF is determined by considering the frequency variation caused by frequency hopping and its own tolerance, the MOSFET conduction time is obtained as: Figure 10. VDD and Winding Voltage (Design Example) Assuming that drain voltage TON @ B = 1/ f S − TOFF VDL @ B min NS ⋅ (1 + ) N P 0.7 ⋅ VO N + VF (26) overshoot is same as the reflected output voltage, the maximum drain voltage is given as: VDS max = VDL max + VRO + VOS = VDL max + 2VRO For 700V MOSFET with 25% margin, the reflected output voltage is obtained as: VDS max = 0.75 × 700 > 373 + 2VRO ∴ VRO < 76V Setting VRO=72 and VF=0.55, the turns ratio NP/NS is obtained as: NP VRO 72 = = = 13 N S (Vo + VF ) 5.55 The allowable VDD range is from 5.5 to 24V, considering the tolerance. Considering voltage ripple on VDD caused by burst operation at no load condition, 3V margin is added for VDD voltage calculation at no-load condition as: © 2009 Fairchild Semiconductor Corporation Rev. 1.0.1 • 5/6/10 7 Figure 11. Definition of tON, tD, and tOFF The transformer primary-side inductance can be calculated as: Lm = (VDL @ B min ⋅ TON @ B ) 2 2 PIN .T @ B ⋅ fS (27) www.fairchildsemi.com AN-8033 The maximum peak drain current can be obtained at the nominal output condition as: Then, the non-conduction time at minimum output voltage is given as: I DS PK = 2 PIN .T Lm ⋅ f S (28) TOFF @ C = min N VDL @ C 1 ) − TON @ C (1 + S ⋅ min f SR N P VO + VF (33) The MOSFET conduction time at the nominal output condition is obtained as: TON = I DS PK Lm VDL min (29) The non-conduction time should be larger than 3µs (10% of switching period), considering the tolerance of switching frequency. Table 2.Typical Cores for Battery Charger Application (for Universal Input Range, DCM Operation, and fs=50kHz) Core EE13-Z EI16-Z EE16-Z EI19-Z Cross-sectional Area 17.1mm 2 19.8mm 2 19.0mm 2 24.0mm 2 The minimum number of turns for the transformer primary side to avoid the core saturation is given by: N P min = Lm I DS PK Bsat Ae (30) 2 Rated Input Power 4~7W 4~7W 7~14W 7~14W where Ae is the cross-sectional area of the core in m and Bsat is the saturation flux density in Tesla. Figure 12 shows the typical characteristics of ferrite core from TDK (PC40). Since the saturation flux density (Bsat) decreases as the temperature rises, the high-temperature characteristics should be considered when it comes to charger in enclosed case. If there is no reference data, use Bsat =0.25~0.3 T. Table 2 shows the commonly used cores for battery chargers with output power under 10W. The cores recommended in Table 2 are typical for the universal input range and 50kHz switching frequency. Once the turns ratio is obtained, determine the proper integer for Ns so that the resulting Np is larger than Npmin obtained from Equation (30). (Design Example) Setting the non-conduction time at 70% of nominal output voltage as 4µs, the MOSFET conduction time is obtained as: TON @ B = 1/ f S − TOFF = 5.4μ s min N S VDL @ B ⋅ (1 + ) N P 0.7 ⋅VO + VF The transformer primary-side inductance is calculated as: Lm = (VDL @ B min ⋅ TON @ B ) 2 2 PIN .T @ B ⋅ f S = 2.24mH Then, the peak drain current at maximum output power condition is given as: I DS PK = 2 PIN .T = 292mA Lm ⋅ f S The MOSFET conduction time at the nominal output condition is obtained as: TON = I DS PK Lm VDL min = 0.292 2.24 ×10−3 = 7.03μ s 93 EE16 core is selected for the transformer and the minimum number of turns for the transformer primary side to avoid the core saturation is given by: Figure 12. Typical B-H Curves of Ferrite Core (TDK/PC40) N P min = = Lm I ds PK Bsat Ae 2.24 × 10−3 ⋅ 0.292 = 114 0.3 ⋅19 ×10−6 DCM operation at minimum output voltage should be also checked. The MOSFET conduction time at minimum output voltage is given as: TON @ C = 1 VDL @ C min 2 PIN .T @ C Lm f SR (31) Then, determine the proper integer for Ns so that the resulting Np is larger than Npmin N P = 13 × N S where fSR is the reduced switching frequency to prevent CCM operation. © 2009 Fairchild Semiconductor Corporation Rev. 1.0.1 • 5/6/10 = 13 × 9 = 117 > N P min www.fairchildsemi.com 8 AN-8033 The auxiliary winding turns, Na is given as: Na = Na × N S = 1.65 × 9 = 15 NS [STEP-6] Output Voltage and Current Setting The nominal output current is determined by the sensing resistor value and transformer turns ratio as: The MOSFET conduction time at minimum output voltage is obtained as: TON @ C = 1 VDL @ C min 2 PIN .T @ C Lm f SR RSENSE = = 3.9μ s NP N S I O N × 8.5 (37) The non-conduction time at minimum output voltage: TOFF @ C = min N VDL @ C 1 − TON @ C (1 + S ⋅ min ) f SR N P VO + VF The voltage divider RS1 and RS2 should be determined so that VS is 2.5V at the end of diode current conduction time, as shown in Figure 9. = 6.82μ s > 3 μ s [STEP-5] Calculate the Voltage and Current of the Switching Devices Primary-Side MOSFET: The voltage stress of the MOSFET was discussed when determining the transformer turns ratio in STEP-3. Assuming that drain voltage overshoot is the same as the reflected output voltage, the maximum drain voltage is given as: RS1 NV = ( a O − 1) RS 2 N S 2.5 (38) Select 1% tolerance resistor for better output regulation. (Design Example) The sensing resistor is obtained as: RSENSE = NP 117 = = 2.0Ω N N S I O × 8.5 9 ⋅ 0.75 × 8.5 The voltage divider network is determined as: VDS max = VDL max + VRO + VOS (33) The rms current though the MOSFET is given as: RS1 NV 15 5 = ( a ⋅ O − 1) = ( ⋅ − 1) = 2.33 9 2.5 RS 2 N S 2.5 By setting RS1=34.8kΩ, RS2 is obtained as 82kΩ. I DS rms = I DS PK TON f s 3 (34) It is recommended to place a bypass capacitor of 22~68pF closely between the VS pin and the GND pin to bypass the switching noise and keep the accuracy of the sampled voltage for CV regulation. The value of the capacitor affects the load regulation and constant current regulation. Figure 13 illustrates the measured waveform on the VS pin with a different VS capacitor. If a higher value VS capacitor is used, the charging time becomes longer and the sampled voltage is higher than the actual value. Vs pin waveform higher Vs Cap lower Vs Cap Secondary-Side diode: The maximum reverse voltage and the rms current of the rectifier diode are obtained respectively, as: VD = VO N + NS VDL max NP VDL min N P ⋅ VRO N S (35) (36) I D rms = I DS rms (Design Example) Assuming voltage overshoot of drain-to-source is same as reflected output voltage, the maximum voltage across the MOSFET is calculated as sampling voltage Vds max = VDL max + 2VRO = 517V The rms current though the MOSFET is sampling voltage I DS rms = I DS PK TON f s = 0.1A 3 No - Load The diode voltage and current are obtained as VD = VO + NS 9 VDL max = 5 + ⋅ 373 = 33.8V NP 117 VDL N 93 132 ⋅ P = 0.10 ⋅ = 1.47 A 72 9 VRO N S min Figure 13. Effect on Sampling Voltage with Different VS Capacitor I D rms = I DS rms Scokttky diode SB240 (2A/40V) is selected. © 2009 Fairchild Semiconductor Corporation Rev. 1.0.1 • 5/6/10 www.fairchildsemi.com 9 AN-8033 [STEP-7] Determine the Output Filter Stage The peak to peak ripple of capacitor current is given as: (Design Example) Assuming 26AWG/1.8m cable is used, the voltage drop at maximum output current is: ΔI CAP = NP I DS PK NS N (39) ΔVO = RCABLE ⋅ I O = 0.48 ⋅ 0.75 = 0.36V ΔVO 0.36 = = 7.2% 5 VO The default setting can be used without any resistor on COMR pin. To improve the noise immunity of COMR pin, it is typical to connect a 1µF bypass capacitor on the COMR pin. The voltage ripple on the output is given by: ΔVO = ΔI C ⋅ TD ΔI C − I O 2 ⋅( ) + ΔI C ⋅ RC ΔI C 2CO (40) Sometimes it is impossible to meet the ripple specification with a single output capacitor due to the high ESR of the electrolytic capacitor. Then, additional LC filter stages (post filter) can be used. When using the post filters, be careful not to place the corner frequency too low. Too low a corner frequency may make the system unstable or limit the control bandwidth. It is typical to set the corner frequency of the post filter at around 1/10~1/5 of the switching frequency. (Design Example) Assuming 470µF electrolytic capacitor with 30mΩ ESR for output capacitor, the voltage ripple on the output is: [STEP-9] Design RCD Snubber in Primary Side When the power MOSFET is turned off, there is a highvoltage spike on the drain due to the transformer leakage inductance. This excessive voltage on the MOSFET may lead to an avalanche breakdown and eventually failure of the device. Therefore, it is necessary to use an additional network to clamp the voltage. The RCD snubber circuit and MOSFET drain voltage waveform are shown in Figure 14. The RCD snubber network absorbs the current in the leakage inductance by turning on the snubber diode (Dsn) once the MOSFET drain voltage exceeds the voltage of node X as depicted in Figure 14. In the analysis of snubber network, it is assumed that the snubber capacitor is large enough that its voltage does not change significantly during one switching cycle. The snubber capacitor should be ceramic or a material that offers low ESR. Electrolytic or tantalum capacitors are unacceptable due to these reasons. Np : Ns + VDL Csn1 VSN + Rsn1 X Dsn Llk Ids ID D - VD + + VO L O A D ΔVO = ΔI C ⋅ TD ΔI C − I O N 2 ⋅( ) + ΔI C ⋅ RC = 137 mV ΔI C 2CO [STEP-8] Cable Voltage Drop Compensation When it comes to cellular phone charger application, the actual battery is located at the end of cable, which causes typically several percentage of voltage drop on the actual battery voltage. FAN103 and FSEZ13X7 have cable voltage drop compensation that can be programmed by a resistor on the COMR pin, as shown in Table 3. The resistances of the standard 1.8m cable for different AWG are summarized in Table 4. Table 3. Cable Compensation Percentage of Voltage Drop Compensation 7% 6% 5% 4% 3% 2% 1% 0% COMR Resistor Infinite (Open) 900kΩ 380kΩ 230kΩ 380kΩ 145kΩ 100kΩ 45kΩ Io Lm + Vds Vgs Idspk Ids 15~20% of BVdss VOS Vsn Table 4. Resistance of 1.8M Cable for Different AWG AWG 24 25 26 Ω/m 0.084 0.106 0.134 Resistance for 1.8m Cable 0.30Ω 0.38Ω 0.48Ω 10 NP (VO + VF ) NS BVdss Vds VDL Figure 14. Snubber Circuit and its Waveforms www.fairchildsemi.com © 2009 Fairchild Semiconductor Corporation Rev. 1.0.1 • 5/6/10 AN-8033 The snubber capacitor voltage at full load condition (VSN) is given as: (Design Example) Since the voltage overshoot of drain VSN = VRO + VOS V2 1 VSN PSN = SN = f S LLK ( I DS PK ) 2 RSN 2 VSN − VRO (41) voltage has been determined same as the reflected output voltage, The snubber voltage is: The power dissipated in the snubber network is obtained as: (42) VSN = VRO + VOS = 144V The leakage inductance is measured as 48µH. Then the loss in snubber network is given as: where IDSPK is peak drain current at full load, LLK is the leakage inductance, VSN is the snubber capacitor voltage at full load and RSN is the snubber resistor. The leakage inductance is measured at the switching frequency on the primary winding with all other windings shorted. Then, the snubber resistor with proper rated wattage should be chosen based on the power loss. The maximum ripple of the snubber capacitor voltage is obtained as: PSN = RSN = VSN 1 f S LLK ( I DS PK ) 2 = 0.20W VSN − VRO 2 VSN 2 = 99k Ω PSN VSN 142 = = 1.0nF ΔVsn RSN f s 28 ⋅ 99 ×103 ⋅ 50 × 103 To allow 20% ripple on the snubber voltage (29V). ΔVsn = VSN CSN RSN f s CSN = (43) In general, 5~20% ripple of the selected capacitor voltage is reasonable. In the snubber design in this section, neither the lossy discharge of the inductor nor stray capacitance is considered. In the actual converter, the loss in the snubber network is less than the designed value due to this effect. © 2009 Fairchild Semiconductor Corporation Rev. 1.0.1 • 5/6/10 www.fairchildsemi.com 11 AN-8033 5. Print Circuit Board Layout Print circuit board layout and design are very important for switching power supply where the voltage and current change with high dv/dt and di/dt. Good PCB layout minimizes excessive EMI and prevents the power supply from being disrupted during surge/ESD tests As indicated by 2, the area enclosed by the transformer aux winding, DDD and CDD, should also be kept short path. Place CDD, CS, RS2, and CCOMR close to each pin of PSR controller for good decoupling and to reduce the switching noise. As indicated by 3, the ground of the control circuits should be connected first, then to other circuitry. GND 3→2→4→1: May make it possible to avoid common impedance interference for the sense signal. Regarding the ESD discharge path, put in the shortcut pad between AC line and DC output (which is the best way). The other method is to discharge the ESD energy to AC line through the primary main ground 1. Because ESD energy is delivered from secondary to primary though the transformer stray capacitor, the controller circuit should not be placed on the discharge path. 5 shows places where the point-discharge route can be placed to bypass the static electricity energy. it is suggested to map out this discharge route in Figure 15 and Figure 16. For the surge path, select fusible resistor type with wire wound type to reduce inrush current and surge energy, use π input filter ( two bulk capacitor and one inductance) to share the surge energy. Guidelines: The numbers in the following guidelines refer to Figure 15 and Figure 16. To improve EMI performance and reduce line frequency ripples, the output of the bridge rectifier should be connected to capacitors CDL2 and CDL1 first, then to the primary switching circuits. The primary high-frequency current loop is in CDL1 – Transformer – MOSFET – RCS – CDL1. The area enclosed by this current loop should be kept as short as possible. Place RSTART for protect the inrush spike (100kΩ is recommended). RCS should be connected CDL1’s ground directly. Keep it short and wide (Trace 4→1) and place it close the CS pin for reducing switching noise. High-voltage traces related to the drain of MOSFET and RCD snubber should be kept far way from control circuits to prevent unnecessary interference. If a heat sink is used for the MOSFET, connect this heat sink to ground. Figure 15. EZ-PSR FSEZ13X7 Layout Consideration © 2009 Fairchild Semiconductor Corporation Rev. 1.0.1 • 5/6/10 www.fairchildsemi.com 12 AN-8033 Figure 16. PSR PWM FAN103 Layout Consideration © 2009 Fairchild Semiconductor Corporation Rev. 1.0.1 • 5/6/10 www.fairchildsemi.com 13 AN-8033 6. Final Schematic of Design Example Figure 17 shows the final schematic of the 3.75W charger design example. EE16core is used for the transformer. Figure 18 shows the transformer information. Figure 17. Final Schematic of the EZ-PSR FSEZ1317 3.75W Design Example Core: EE16 PC40 Bobbin: EE16 (10 pins) Horizontal type Figure 18. Transformer Structure Notes: 1. When W4R’s winding is reversed winding, it must wind one layer. 2. When W2 is winding, it must wind three layers and put one layer of tape after winding the first layer. NO TERMINAL S F WIRE ts INSULATION ts BARRIER TAPE Primary Seconds W1 W2 W3 W4 4 3 1 7 5 1 2UEW 0.23*1 2UEW 0.18*1 COPPER SHIELD TEX-E 0.55*1 CORE ROUNDING TAPE Pin 15 41 39 37 1.2 9 2 1 0 2 3 3 3 Remark 100kHz, 1V Short One of the Secondary Windings www.fairchildsemi.com 9 Specification 2.25mH ± 5% 80μH Maximum Primary-Side Inductance Primary-Side Leakage Inductance © 2009 Fairchild Semiconductor Corporation Rev. 1.0.1 • 5/6/10 1－3 1－3 14 AN-8033 7. Test Result of Design Example To show the validity of the design procedure presented in this application note, the converter of the design example has been built and tested. All the circuit components are used as designed in the design example. Figure 19 shows the operation waveforms at 70% of nominal output voltage and minimum line voltage condition. As designed in STEP-4, the non-conduction time is 4μs before frequency reduction occurs, which guarantees DCM operation. Figure 20 shows the operation waveforms at minimum output voltage and minimum line voltage condition. As designed in STEP-4, the non-conduction time is about 6.8μs, which guarantees DCM operation. Figure 21 shows the measured efficiency for different load conditions. The average efficiencies at 115VAC and 230VAC condition are higher than 68%. Figure 22 shows the measured no-load power consumption at different line voltage. As can be seen in the figures, even in the 264VAC AC line, the no-load standby power consumption is still less than 30mW, meeting the five-star level of new power consumption regulation for charger. Figure 23 shows the measured output voltage and output current curve. CV regulation achieves 1.38% for entire line and load condition. The CC regulation can achieve 3.6% with a fold-back voltage of 1.5V. Figure 21. Measured Efficiency Figure 22. Measured No-Load Power Consumption Figure 19. Operation Waveforms at 70% of Nominal Output Voltage and Minimum Line Voltage Condition Figure 20. Operation Waveforms at Minimum Output Voltage and Minimum Line Voltage Condition Figure 23. Measured Output Voltage and Output Current Curve © 2009 Fairchild Semiconductor Corporation Rev. 1.0.1 • 5/6/10 www.fairchildsemi.com 15 AN-8033 8 Related Resources FSEZ1317 — Primary- Side Regulation PWM with Power MOSFET Integrated Datasheet FAN103 — Primary-Side Regulation PWM Controller Datasheet AN-6067 — Design and Application of Primary-Side Regulation (PSR) PWM Controller AN8033 DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. © 2009 Fairchild Semiconductor Corporation Rev. 1.0.1 • 5/6/10 www.fairchildsemi.com 16