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BUZ11

BUZ11

  • 厂商:

    FAIRCHILD(仙童半导体)

  • 封装:

  • 描述:

    BUZ11 - 30A, 50V, 0.040 Ohm, N-Channel Power MOSFET - Fairchild Semiconductor

  • 数据手册
  • 价格&库存
BUZ11 数据手册
BUZ11 Data Sheet June 1999 File Number 2253.2 30A, 50V, 0.040 Ohm, N-Channel Power MOSFET [ /Title (BUZ1 1) /Subject (30A, 50V, 0.040 Ohm, NChannel Power MOSFET) /Autho r () /Keywords (Intersil Corporation, NChannel Power MOSFET, TO220AB ) /Creator () /DOCI NFO pdfmark This is an N-Channel enhancement mode silicon gate power field effect transistor designed for applications such as switching regulators, switching converters, motor drivers, relay drivers and drivers for high power bipolar switching transistors requiring high speed and low gate drive power. This type can be operated directly from integrated circuits. Formerly developmental type TA9771. Features • 30A, 50V • rDS(ON) = 0.040Ω • SOA is Power Dissipation Limited • Nanosecond Switching Speeds • Linear Transfer Characteristics • High Input Impedance • Majority Carrier Device • Related Literature - TB334 “Guidelines for Soldering Surface Mount Components to PC Boards” Ordering Information PART NUMBER BUZ11 PACKAGE TO-220AB BRAND BUZ11 NOTE: When ordering, use the entire part number. Symbol D G S Packaging JEDEC TO-220AB SOURCE DRAIN GATE DRAIN (FLANGE) ©2001 Fairchild Semiconductor Corporation BUZ1 Rev. A BUZ11 Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified BUZ11 50 50 30 120 ±20 75 0.6 -55 to 150 E 55/150/56 300 260 oC oC Drain to Source Breakdown Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDS Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Continuous Drain Current TC = 30oC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VGS Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .PD Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG DIN Humidity Category - DIN 40040 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IEC Climatic Category - DIN IEC 68-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg UNITS V V A A V W W/oC oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TJ = 25oC to 125oC. TC = 25oC, Unless Otherwise Specified SYMBOL BVDSS VGS(TH) IDSS TEST CONDITIONS ID = 250µA, VGS = 0V VGS = VDS, ID = 1mA (Figure 9) TJ = 25oC, VDS = 50V, VGS = 0V TJ = 125oC, VDS = 50V, VGS = 0V Gate to Source Leakage Current Drain to Source On Resistance (Note 2) Forward Transconductance (Note 2) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance Thermal Resistance Junction to Case Thermal Resistance Junction to Ambient IGSS rDS(ON) gfs td(ON) tr td(OFF) tf CISS COSS CRSS RθJC RθJA VDS = 25V, VGS = 0V, f = 1MHz (Figure 10) VGS = 20V, VDS = 0V ID = 15A, VGS = 10V (Figure 8) VDS = 25V, ID = 15A (Figure 11) VCC = 30V, ID ≈ 3A, VGS = 10V, RGS = 50Ω, RL = 10Ω MIN 50 2.1 4 TYP 3 20 100 10 0.03 8 30 70 180 130 1500 750 250 ≤ 1.67 ≤ 75 MAX 4 250 1000 100 0.04 45 110 230 170 2000 1100 400 UNITS V V µA µA nA Ω S ns ns ns ns pF pF pF oC/W oC/W Electrical Specifications PARAMETER Drain to Source Breakdown Voltage Gate Threshold Voltage Zero Gate Voltage Drain Current Source to Drain Diode Specifications PARAMETER Continuous Source to Drain Current Pulsed Source to Drain Current Source to Drain Diode Voltage Reverse Recovery Time Reverse Recovery Charge NOTES: 2. Pulse Test: Pulse width ≤ 300ms, duty cycle ≤ 2%. 3. Repetitive rating: pulse width limited by maximum junction temperature. See Transient Thermal Impedance curve (Figure 3). SYMBOL ISD ISDM VSD trr QRR TEST CONDITIONS TC = 25oC TC = 25oC TJ = 25oC, ISD = 60A, VGS = 0V TJ = 25oC, ISD = 30A, dISD/dt = 100A/µs, VR = 30V MIN TYP 1.7 200 0.25 MAX 30 120 2.6 UNITS A A V ns µC ©2001 Fairchild Semiconductor Corporation BUZ1 Rev. A BUZ11 Typical Performance Curves 1.2 POWER DISSIPATION MULTIPLIER 1.0 ID, DRAIN CURRENT (A) 30 0.8 Unless Otherwise Specified 40 VGS > 10V 0.6 0.4 20 10 0.2 0 0 25 50 75 100 TA , CASE TEMPERATURE (oC) 125 150 0 0 50 100 TC, CASE TEMPERATURE (oC) 150 FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE ZθJC, TRANSIENT THERMAL IMPEDANCE 1 0.5 0.2 0.1 0.05 0.02 0.01 SINGLE PULSE PDM 0.1 t1 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJC + TC 10-3 10-2 10-1 t, RECTANGULAR PULSE DURATION (s) 100 101 0.01 10-5 10-4 FIGURE 3. MAXIMUM TRANSIENT THERMAL IMPEDANCE 103 OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) 102 2.5µs 10µs 100µs 101 1ms TC = 25oC TJ = MAX RATED SINGLE PULSE 100 100 101 VDS, DRAIN TO SOURCE VOLTAGE (V) 10ms 100ms DC 102 60 PD = 75W 50 ID, DRAIN CURRENT (A) VGS = 20V PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX 10V ID, DRAIN CURRENT (A) 40 30 20 10 0 VGS = 8.0V VGS = 7.5V VGS = 7.0V VGS = 6.5V VGS = 6.0V VGS = 5.5V VGS = 5.0V VGS = 4.5V VGS = 4.0V 0 1 2 3 4 5 VDS, DRAIN TO SOURCE VOLTAGE (V) 6 FIGURE 4. FORWARD BIAS SAFE OPERATING AREA FIGURE 5. OUTPUT CHARACTERISTICS ©2001 Fairchild Semiconductor Corporation BUZ1 Rev. A BUZ11 Typical Performance Curves IDS(ON), DRAIN TO SOURCE CURRENT (A) 20 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX VDS = 25V Unless Otherwise Specified (Continued) 0.15 rDS(ON), ON-STATE RESISTANCE (Ω) PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX VGS = 5V 5.5V 6V 6.5V 7V 7.5V 8V 9V 10V 20V 15 0.10 10 0.05 5 0 0 1 3 4 5 6 VGS, GATE TO SOURCE VOLTAGE (V) 2 7 8 0 0 20 40 ID, DRAIN CURRENT (A) 60 FIGURE 6. TRANSFER CHARACTERISTICS FIGURE 7. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT VGS(TH), GATE THRESHOLD VOLTAGE (V) 0.08 rDS(ON), DRAIN TO SOURCE ON RESISTANCE (Ω) PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX ID = 15A, VGS = 10V 4 VDS = VGS ID = 1mA 0.06 3 0.04 2 0.02 1 0 -50 0 50 100 150 0 -50 0 50 100 150 TJ, JUNCTION TEMPERATURE (oC) TJ, JUNCTION TEMPERATURE (oC) FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE FIGURE 9. GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE 101 gfs, TRANSCONDUCTANCE (S) 10 8 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX VDS = 25V TJ = 25oC C, CAPACITANCE (nF) 100 CISS COSS CRSS 6 4 10-1 VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS ≈ CDS + CGD 0 10 20 30 40 2 10-2 0 0 5 10 ID, DRAIN CURRENT (A) 15 20 VDS, DRAIN TO SOURCE VOLTAGE (V) FIGURE 10. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE FIGURE 11. TRANSCONDUCTANCE vs DRAIN CURRENT ©2001 Fairchild Semiconductor Corporation BUZ1 Rev. A BUZ11 Typical Performance Curves 103 ISD, SOURCE TO DRAIN CURRENT (A) PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX TJ = 25oC TJ = 150oC 101 Unless Otherwise Specified (Continued) 15 VGS, GATE TO SOURCE VOLTAGE (V) ID = 45A 102 VDS = 10V 10 VDS = 40V 5 100 10-1 0 0.5 1.0 1.5 2.0 2.5 VSD, SOURCE TO DRAIN VOLTAGE (V) 3.0 0 0 10 20 30 Qg, GATE CHARGE (nC) 40 50 FIGURE 12. SOURCE TO DRAIN DIODE VOLTAGE FIGURE 13. GATE TO SOURCE VOLTAGE vs GATE CHARGE Test Circuits and Waveforms tON td(ON) tr RL VDS 90% tOFF td(OFF) tf 90% + RG DUT - VDD 0 10% 90% 10% VGS VGS 0 10% 50% PULSE WIDTH 50% FIGURE 14. SWITCHING TIME TEST CIRCUIT VDS (ISOLATED SUPPLY) VDD SAME TYPE AS DUT 0.3µF FIGURE 15. RESISTIVE SWITCHING WAVEFORMS CURRENT REGULATOR Qg(TOT) Qgd Qgs 12V BATTERY 0.2µF 50kΩ VGS D VDS G DUT 0 Ig(REF) 0 IG CURRENT SAMPLING RESISTOR S VDS ID CURRENT SAMPLING RESISTOR Ig(REF) 0 FIGURE 16. GATE CHARGE TEST CIRCUIT FIGURE 17. GATE CHARGE WAVEFORMS ©2001 Fairchild Semiconductor Corporation BUZ1 Rev. A TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACEx™ Bottomless™ CoolFET™ CROSSVOLT™ DenseTrench™ DOME™ EcoSPARK™ E2CMOSTM EnSignaTM FACT™ FACT Quiet Series™ DISCLAIMER FAST  FASTr™ GlobalOptoisolator™ GTO™ HiSeC™ ISOPLANAR™ LittleFET™ MicroFET™ MICROWIRE™ OPTOLOGIC™ OPTOPLANAR™ PACMAN™ POP™ PowerTrench  QFET™ QS™ QT Optoelectronics™ Quiet Series™ SILENT SWITCHER  SMART START™ Star* Power™ Stealth™ SuperSOT™-3 SuperSOT™-6 SuperSOT™-8 SyncFET™ TinyLogic™ UHC™ UltraFET™ VCX™ FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life support device or system whose failure to perform can systems which, (a) are intended for surgical implant into be reasonably expected to cause the failure of the life the body, or (b) support or sustain life, or (c) whose support device or system, or to affect its safety or failure to perform when properly used in accordance with instructions for use provided in the labeling, can be effectiveness. reasonably expected to result in significant injury to the user. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Advance Information Product Status Formative or In Design Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Preliminary First Production No Identification Needed Full Production Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Rev. H
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