FAN7389

FAN7389 — 3-Phase Half-Bridge Gate-Drive IC September 2010 FAN7389 3-Phase Half-Bridge Gate-Drive IC Features Floating Channel for Bootstrap Operation to +600V Typically 350mA/650mA Sourcing/Sinking Current Driving Capability for All Channels Extended Allowable Negative VS Swing to -9.8V for Signal Propagation at VDD=VBS=15V Output In-Phase with Input Signal Over-Current Shutdown Turns off All Six Drivers Matched Propagation Delay for All Channels 3.3V and 5V Input Logic Compatible Adjustable Fault-Clear Timing Built-in Advanced Input Filter Built-in Shoot-Through Prevention Logic Built-in Soft Turn-Off Function Common-Mode dv/dt Noise Canceling Circuit Built-in UVLO Functions for All Channels Description The FAN7389 is a monolithic three-phase half-bridge gate-drive IC designed for high-voltage, high-speed driving MOSFETs and IGBTs operating up to +600V. Fairchild’s high-voltage process and common-mode noise canceling technique provide stable operation of high-side drivers under high-dv/dt noise circumstances. An advanced level-shift circuit allows high-side gate driver operation up to VS = -9.8V (typical) for VBS =15V. The protection functions include under-voltage lockout and inverter over-current trip with an automatic faultclear function. Over-current protection that terminates all six outputs can be derived from an external current-sense resistor. An open-drain fault signal is provided to indicate that an over-current or under-voltage shutdown has occurred. The UVLO circuits prevent malfunction when VDD and VBS are lower than the specified threshold voltage. Output drivers typically source and sink 350mA and 650mA, respectively; which is suitable for three-phase half-bridge applications in motor drive systems. Applications 3-Phase Motor Inverter Driver Air Conditioners W ashing Machines General-Purpose Three-Phase Inverters 24-SOIC Ordering Information Part Number FAN7389M (1) (1) Package 24-SOP Operating Temperature -40 to +125°C Packing Method Tube Tape & Reel FAN7389MX Note: 1. These devices passed wave soldering test by JESD22A-111. © 2010 Fairchild Semiconductor Corporation FAN7389 • Rev. 1.0.0 www.fairchildsemi.com FAN7389 — 3-Phase Half-Bridge Gate-Drive IC Typical Application Diagram VDD VMOTOR 1 UU VU VDD HIN1 HIN2 HIN3 LIN1 LIN2 LIN3 FO CS VB1 24 HO1 23 VS1 22 VB2 21 HO2 20 VS2 19 VB3 18 HO3 17 VS3 16 LO1 15 LO2 14 LO3 13 Wup VS3 Udn Vdn Wdn Udn Vdn VS3 Wdn Vup VS2 VS1 U 2 3 4 5 6 7 8 Uup VS1 Uup Vup Wup 3-Phase WU BLDC Motor Controller UL VL WL 3-Phase Inverter VS2 V W CONTROL 9 10 EN 11 CRCIN 12 COM RCIN RCS Figure 1. 3-Phase BLDC Motor Drive Application © 2010 Fairchild Semiconductor Corporation FAN7389 • Rev. 1.0.0 www.fairchildsemi.com 2 FAN7389 — 3-Phase Half-Bridge Gate-Drive IC Internal Block Diagram Figure 2. Functional Block Diagram © 2010 Fairchild Semiconductor Corporation FAN7389 • Rev. 1.0.0 www.fairchildsemi.com 3 FAN7389 — 3-Phase Half-Bridge Gate-Drive IC Pin Configuration Figure 3. Pin Configuration Pin Definitions Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Name VDD HIN1 HIN2 HIN3 LIN1 LIN2 LIN3 FO CS EN RCIN COM LO3 LO2 LO1 VS3 HO3 VB3 VS2 HO2 VB2 VS1 HO1 VB1 Description Logic and low-side gate drivers power supply voltage Logic Input 1 for high-side gate 1 driver Logic Input 2 for high-side gate 2 driver Logic Input 3 for high-side gate 3 driver Logic Input 1 for low-side gate 1 driver Logic Input 2 for low-side gate 2 driver Logic Input 3 for low-side gate 3 driver Fault output with open-drain (indicates over-current and low-side under-voltage) Analog input for over-current shutdown Logic input for shutdown functionality An external RC network input used to define the fault-clear delay Low-side driver return Low-side gate driver 3 output Low-side gate driver 2 output Low-side gate driver 1 output High-side driver 3 floating supply offset voltage High-side driver 3 gate driver output High-side driver 3 floating supply High-side driver 2 floating supply offset voltage High-side driver 2 gate driver output High-side driver 2 floating supply High-side driver 1 floating supply offset voltage High-side driver 1 gate driver output High-side driver 1 floating supply www.fairchildsemi.com 4 © 2010 Fairchild Semiconductor Corporation FAN7389 • Rev. 1.0.0 FAN7389 — 3-Phase Half-Bridge Gate-Drive IC Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. TA=25°C, unless otherwise specified. Symbol VS VB VDD VHO VLO VIN VFO PW HIN dVS/dt PD θJA TJ TSTG Parameter High-Side Floating Offset Voltage High-Side Floating Supply Voltage Low-side and logic-fixed supply voltage High-Side Floating Output Voltage VHO1,2,3 Low-Side Floating Output Voltage VLO1,2,3 Input Voltage (HINx, LINx, CS, and EN) Fault Output Voltage ( FO ) High-Side Input Pulse Width Allowable Offset Voltage Slew Rate Power Dissipation (2,3,4) Min. VB1,2,3-25 -0.3 -0.3 VS1,2,3-0.3 -0.3 -0.3 -0.3 500 Max. VB1,2,3+0.3 625 25 VB1,2,3+0.3 VDD+0.3 5.5 VDD+0.3 ±50 1.4 70 150 Unit V V V V V V V ns V/ns W °C/W °C °C Thermal Resistance Junction Temperature Storage Temperature -55 150 Notes: 2. Mounted on 76.2 x 114.3 x 1.6mm PCB (FR-4 glass epoxy material). 3. Refer to the following standards: JESD51-2: Integral circuits thermal test method environmental conditions - natural convection JESD51-3: Low effective thermal conductivity test board for leaded surface-mount packages. 4. Do not exceed PD under any circumstances. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol VB1,2,3 VS1,2,3 VDD VHO1,2,3 VLO1,2,3 VFO VCS VIN TA Parameter High-Side Floating Supply Voltage High-Side Floating Supply Offset Voltage Low-Side and Logic Fixed Supply Voltage High-Side Output Voltage Low-Side Output Voltage Fault Output Voltage ( FO ) Current-Sense Pin Input Voltage Logic Input Voltage (HIN1,2,3 and LIN1,2,3) Ambient Temperature Min. VS1,2,3+10 6-VDD 10 VS1,2,3 COM COM COM COM -40 Max. VS1,2,3+20 600 20 VB1,2,3 VDD VDD 5 5 +125 Unit V V V V V V V V °C © 2010 Fairchild Semiconductor Corporation FAN7389 • Rev. 1.0.0 www.fairchildsemi.com 5 FAN7389 — 3-Phase Half-Bridge Gate-Drive IC Electrical Characteristics VBIAS (VDD, VBS1,2,3) = 15.0V and TA = 25°C unless otherwise specified. The VIN and IIN parameters are referenced to COM and are applicable to all six channels. The VO and IO parameters are referenced to VS1,2,3 and COM and are applicable to the respective output leads: HO1,2,3 and LO1,2,3. The VDDUV parameters are referenced to COM. The VBSUV parameters are referenced to VS1,2,3. Symbol IQDD IPDD VDDUV+ VDDUVVDDHYS Parameter Quiescent VDD Supply Current Operating VDD Supply Current VDD Supply Under-Voltage Positive-Going Threshold VDD Supply Under-Voltage Negative-Going Threshold VDD Supply Under-Voltage Lockout Hysteresis VBS Supply Under-Voltage Positive-Going Threshold VBS Supply Under-Voltage Negative-Going Threshold VBS Supply Under-Voltage Lockout Hysteresis Offset Supply Leakage Current Quiescent VBS Supply Current Operating VBS Supply Current High-Level Output voltage, VBIAS-VO Low-Level Output voltage, VO Output HIGH Short-Circuit Pulse Current (5) (5) Conditions VLIN1,2,3=0V or 5V, EN=0V fLIN1,2,3=20kHz, rms Value VDD=Sweep VDD=Sweep VDD=Sweep Min. Typ. Max. Unit 200 400 7.5 7.0 8.5 8.0 0.5 9.3 8.7 μA μA V V V Low-Side Power Supply Section Bootstrapped Power Supply Section VBSUV+ VBSUVVBSHYS ILK IQBS IPBS VOH VOL IO+ IOVS VBS1,2,3=Sweep VBS1,2,3=Sweep VBS1,2,3=Sweep VB1,2,3=VS1,2,3=600V VHIN1,2,3=0V or 5V, EN=0V fHIN1,2,3=20kHz, rms Value IO=0mA (No Load) IO=0mA (No Load) VO=0V, VIN=5V with PW ≤10µs VO=15V, VIN=0V with PW ≤10µs 250 500 350 650 -9.8 -7.0 10 200 50 420 7.5 7.0 8.5 8.0 0.5 10 80 480 100 100 9.3 8.7 V V V μA μA μA mV mV mA mA V Gate Driver Output Section Output LOW Short-Circuit Pulsed Current Allowable Negative VS Pin Voltage for HIN Signal Propagation to HO Logic "1" Input Voltage HIN1,2,3, LIN1,2,3 Logic "0" Input Voltage HIN1,2,3, LIN1,2,3 Logic Input Bias Current (HO=LO=HIGH) Logic Input Bias Current (HO=LO=LOW) Logic Input Pull-Down Resistance Enable Positive-Going Threshold Voltage Enable Negative-Going Threshold Voltage Logic Enable “1” Input Bias Current Logic Enable “0” Input Bias Current VEN=5V (Pull-Down=150KΩ) VEN=0V 2.5 VIN=5V VIN=0V 2.5 Logic Input Section VIH VIL IIN+ IINRIN VEN+ VENIEN+ IENV 0.8 100 2 50 V μA μA KΩ V 0.8 33 2 V μA μA Enable Control Section (EN) Continued on the following page… © 2010 Fairchild Semiconductor Corporation FAN7389 • Rev. 1.0.0 www.fairchildsemi.com 6 FAN7389 — 3-Phase Half-Bridge Gate-Drive IC Electrical Characteristics VBIAS (VDD, VBS1,2,3) = 15.0V and TA = 25°C unless otherwise specified. The VIN and IIN parameters are referenced to COM and are applicable to all six channels. The VO and IO parameters are referenced to VS1,2,3 and COM and are applicable to the respective output leads: HO1,2,3 and LO1,2,3. The VDDUV parameters are referenced to COM. The VBSUV parameters are referenced to VS1,2,3. Symbol VCSTH+ VCSTHVCSHYS ICSIN ISOFT Parameter Over-Current Detect Positive Threshold Over-Current Detect Hysteresis Short-Circuit Input Current Soft Turn-Off Sink Current (5) (5) (5) Conditions Min. Typ. Max. Unit 400 500 440 60 600 mV mV mV 15 55 μA mA V V V 7 0.5 100 170 µA V Ω Ω Over-Current Protection Section Over-Current Detect Negative Threshold VCSIN=1V 5 25 10 40 3.3 2.6 0.7 Fault Output Section VRCINTH+ RCIN Positive-Going Threshold Voltage VRCINTHIRCIN VFOL RDSRCIN RDSFO RCIN Negative-Going Threshold Voltage RCIN Internal Current Source Fault Output Low Level Voltage RCIN On Resistance Fault Output On Resistance CRCIN=2nF VCS=1V, IFO=1.5mA IRCIN=1.5mA IFO=1.5mA 50 90 3 VRCINHYS RCIN Hysteresis Voltage 5 0.2 75 130 Note: 5. These parameters are guaranteed by design. Dynamic Electrical Characteristics TA=25°C, VBIAS (VDD, VBS1,2,3) = 15.0V, VS1,2,3 = COM, and CLoad = 1000pF unless otherwise specified. Symbol tON tOFF tR tF tEN tCSBLT tCSFO tCSOFF tFLT,IN tFLTCLR DT MDT MT PM Parameter Turn-On Propagation Delay Turn-Off Propagation Delay Turn-On Rise Time Turn-Off Fall Time Enable LOW to Output Shutdown Delay CS Pin Leading-Edge Blanking Time Time from CS Triggering to FO Time from CS Triggering to All Gate Outputs Turn-Off Input Filtering Time Input Filtering Time Fault-Clear Time Dead Time Dead-Time Matching (All Six Channels) Delay Matching (All Six Channels) Output Pulse-Width Matching (6,8) (7) (7) (6) Conditions VLIN1,2,3=VHIN1,2,3=0V, VS1,2,3=0V VLIN1,2,3=VHIN1,2,3=5V, VS1,2,3=0V VLIN1,2,3=VHIN1,2,3=0V VLIN1,2,3=VHIN1,2,3=5V Min. Typ. Max. 350 350 20 10 400 200 500 500 50 30 500 300 630 640 200 200 250 250 1.3 250 300 350 50 50 300 300 650 650 100 80 600 400 Unit ns ns ns ns ns ns ns ns ns ns ms ns ns ns ns From VCSC=1V to FO Turn-Off From VCSC=1V to Starting Gate Turn-Off (HINx, LINx) (EN) RCIN: CRCIN=2nF PW IN > 1µs 50 100 Notes: 6. These parameters are guaranteed by design. 7. The minimum width of the input pulse should exceed 500ns to ensure the filtering time of the input filter is exceeded. 8. PM is defined as PW IN-PW OUT, © 2010 Fairchild Semiconductor Corporation FAN7389 • Rev. 1.0.0 www.fairchildsemi.com 7 FAN7389 — 3-Phase Half-Bridge Gate-Drive IC Typical Characteristics 650 600 550 650 600 550 tON [ns] 500 450 400 350 -40 High-Side Low-Side tOFF [ns] 500 450 400 350 -40 High-Side Low-Side -20 0 20 40 60 80 100 120 -20 0 20 40 60 80 100 120 Temperature [°C] Temperature [°C] Figure 4. Turn-On Propagation Delay vs. Temperature Figure 5. Turn-Off Propagation Delay vs. Temperature 100 90 80 tR [ns] 80 70 60 60 50 40 30 20 -40 -20 0 20 40 60 80 High-Side Low-Side 100 120 tF [ns] 70 50 40 30 20 10 0 -40 -20 0 20 40 60 80 High-Side Low-Side 100 120 Temperature [°C] Temperature [°C] Figure 6. Turn-On Rise Time vs. Temperature Figure 7. Turn-Off Fall Time vs. Temperature 600 2.0 1.8 550 tFLTCLR [ms] -20 0 20 40 60 80 100 120 tEN [ns] 1.6 1.4 1.2 1.0 -40 500 450 400 -40 -20 0 20 40 60 80 100 120 Temperature [°C] Temperature [°C] Figure 8. Enable LOW to Output Shutdown Delay vs. Temperature Figure 9. Fault-Clear Time vs. Temperature © 2010 Fairchild Semiconductor Corporation FAN7389 • Rev. 1.0.0 www.fairchildsemi.com 8 FAN7389 — 3-Phase Half-Bridge Gate-Drive IC Typical Characteristics (Continued) 400 50 350 25 300 MDT [ns] DT1 DT2 DT [ns] 0 250 -25 200 -40 -20 0 20 40 60 80 100 120 -50 -40 -20 0 20 40 60 80 100 120 Temperature [°C] Temperature [°C] Figure 10. Dead Time vs. Temperature Figure 11. Dead-Time Matching vs. Temperature 50 40 30 20 0 -10 -20 -30 -40 -50 -40 -20 0 20 40 60 80 MTON MTOFF -7 -8 -9 Delay Matching [ns] VS [V] 100 120 10 -10 -11 -12 -13 -40 -20 0 20 40 60 80 100 120 Temperature [°C] Temperature [°C] Figure 12. Delay Matching vs. Temperature Figure 13. Allowable Negative VS Voltage vs. Temperature 400 350 300 100 80 IQDD [μA] IQBS [μA] -20 0 20 40 60 80 100 120 250 200 150 100 50 -40 60 40 20 0 -40 -20 0 20 40 60 80 100 120 Temperature [°C] Temperature [°C] Figure 14. Quiescent VDD Supply Current vs. Temperature Figure 15. Quiescent VBS Supply Current vs. Temperature © 2010 Fairchild Semiconductor Corporation FAN7389 • Rev. 1.0.0 www.fairchildsemi.com 9 FAN7389 — 3-Phase Half-Bridge Gate-Drive IC Typical Characteristics (Continued) 700 600 500 700 600 500 IPDD [μA] 400 300 200 100 -40 IPBS [μA] -20 0 20 40 60 80 100 120 400 300 200 100 -40 -20 0 20 40 60 80 100 120 Temperature [°C] Temperature [°C] Figure 16. Operating VDD Supply Current vs. Temperature Figure 17. Operating VBS Supply Current vs. Temperature 9.5 9.5 9.0 9.0 VDDUV+ [V] VDDUV- [V] -20 0 20 40 60 80 100 120 8.5 8.0 7.5 8.5 8.0 7.0 7.5 -40 6.5 -40 -20 0 20 40 60 80 100 120 Temperature [°C] Temperature [°C] Figure 18. VDD UVLO+ vs. Temperature Figure 19. VDD UVLO- vs. Temperature 9.5 9.0 9.0 8.5 VBSUV+ [V] 8.5 VBSUV- [V] -20 0 20 40 60 80 100 120 8.0 8.0 7.5 7.5 -40 7.0 -40 -20 0 20 40 60 80 100 120 Temperature [°C] Temperature [°C] Figure 20. VBS UVLO+ vs. Temperature Figure 21. VBS UVLO- vs. Temperature © 2010 Fairchild Semiconductor Corporation FAN7389 • Rev. 1.0.0 www.fairchildsemi.com 10 FAN7389 — 3-Phase Half-Bridge Gate-Drive IC Typical Characteristics (Continued) 100 80 High-Side Low-Side 100 80 High-Side Low-Side VOH [mV] VOL [mV] -20 0 20 40 60 80 100 120 60 40 20 0 -40 60 40 20 0 -40 -20 0 20 40 60 80 100 120 Temperature [°C] Temperature [°C] Figure 22. High-Level Output Voltage vs. Temperature Figure 23. Low-Level Output Voltage vs. Temperature 3.0 3.0 2.5 2.5 VIH [V] VIL [V] -20 0 20 40 60 80 100 120 2.0 1.5 2.0 1.5 1.0 0.5 -40 1.0 -40 -20 0 20 40 60 80 100 120 Temperature [°C] Temperature [°C] Figure 24. Logic HIGH Input Voltage vs. Temperature Figure 25. Logic LOW Input Voltage vs. Temperature 160 140 2.0 1.5 IIN+ [μA] 120 100 80 60 -40 IIN- [μA] -20 0 20 40 60 80 100 120 1.0 0.5 0.0 -40 -20 0 20 40 60 80 100 120 Temperature [°C] Temperature [°C] Figure 26. Logic Input HIGH Bias Current vs. Temperature Figure 27. Logic Input LOW Bias Current vs. Temperature © 2010 Fairchild Semiconductor Corporation FAN7389 • Rev. 1.0.0 www.fairchildsemi.com 11 FAN7389 — 3-Phase Half-Bridge Gate-Drive IC Typical Characteristics (Continued) 100 80 60 40 20 0 10 200 180 REN [KΩ] 12 14 16 18 20 RIN [KΩ] 160 140 120 100 10 12 14 16 18 20 Supply Voltage [V] Supply Voltage [V] Figure 28. Input Pull-Down Resistance vs. Supply Voltage Figure 29. Enable Pin Pull-Down Resistance vs. Supply Voltage 400 350 300 100 80 IQDD [μA] IQBS [μA] 12 14 16 18 20 250 200 150 100 50 10 60 40 20 0 10 12 14 16 18 20 Supply Voltage [V] Supply Voltage [V] Figure 30. Quiescent VDD Supply Current vs. Supply Voltage Figure 31. Quiescent VBS Supply Current vs. Supply Voltage 700 600 500 700 600 500 IPDD [μA] 400 300 200 100 10 IPBS [μA] 12 14 16 18 20 400 300 200 100 10 12 14 16 18 20 Supply Voltage [V] Supply Voltage [V] Figure 32. Operating VDD Supply Current vs. Supply Voltage Figure 33. Operating VBS Supply Current vs. Supply Voltage © 2010 Fairchild Semiconductor Corporation FAN7389 • Rev. 1.0.0 www.fairchildsemi.com 12 FAN7389 — 3-Phase Half-Bridge Gate-Drive IC Switching Time Definitions HINx (LINx) 50% 50% tON tR 90% tOFF 90% tF HOx (LOx) 10% 10% Figure 34. Switching Time Waveform Definitions Figure 35. Input / Output Timing Diagram Figure 36. Detailed View of B and C Intervals During Over-Current Protection © 2010 Fairchild Semiconductor Corporation FAN7389 • Rev. 1.0.0 www.fairchildsemi.com 13 FAN7389 — 3-Phase Half-Bridge Gate-Drive IC Applications Information 1. Dead Time Dead time is automatically inserted whenever the dead time of the external two input signals (between HINx and LINx signals) is shorter than internal fixed dead times (DT1 and DT2). Otherwise, external dead times larger than internal dead times are not modified by the gate driver and internal dead-time waveform definition is shown in Figure 37. 2.2 Shoot-Through Protection The shoot-through protection circuitry prevents both high- and low-side switches from conducting at the same time, as shown Figure 39. Figure 37. Internal Dead-Time Definitions 2. Protection Function 2.1 Fault Out ( FO ) and Under-Voltage Lockout The high- and low-side drivers include under-voltage lockout (UVLO) protection circuitry that monitors the supply voltage for VDD and VBS independently. It can be designed to prevent malfunction when VDD and VBS are lower than the specified threshold voltage. Also, the UVLO hysteresis prevents chattering during powersupply transitions. Moreover, the fault signal ( FO ) goes to LOW state to operate reliably during power-on events, when the power supply (VDD) is below the under-voltage lockout high threshold voltage for the circuit (during t1 ~ t2). The UVLO circuit is not otherwise activated; shown Figure 38. Figure 39. Shoot-Through Protection 2.3 Enable Input W hen the EN pin is in HIGH state, the gate driver operates normally. When a condition occurs that should shut down the gate driver, the EN pin should be LOW. The enable circuitry has an input filter; the minimum input duration is specified by tFLT,IN (typically 250ns). Figure 38. Waveforms for Under-Voltage Lockout Figure 40. Output Enable Timing Waveform © 2010 Fairchild Semiconductor Corporation FAN7389 • Rev. 1.0.0 www.fairchildsemi.com 14 FAN7389 — 3-Phase Half-Bridge Gate Driver IC 2.4 Fault-Out ( FO ) and Over-Current Protection FAN7389 provides an integrated fault output ( FO ) and an adjustable fault-clear timer (tFLTCLR). There are two situations that cause the gate driver to report a fault via the FO pin. The first is an under-voltage condition of low-side gate driver supply voltage (VDD) and the second is when the current-sense pin (CS) recognizes a fault. Once the fault condition occurs, the FO pin is internally pulled to COM, the fault-clear timer is activated, and all outputs (HO1,2,3 and LO1,2,3) of the gate driver are turned off. The fault output stays LOW until the fault condition has been removed and the faultclear timer expires. Once the fault-clear timer expires, the voltage on the FO pin returns to pull-up voltage. The fault-clear time (tFLTCLR) is determined by an internal current source (IRCIN=5μA) and an external CRCIN at the RCIN pin, as shown in this equation: t FLTCLR = C RCIN × VRCIN,TH I RCIN Figure 42. RCIN and Fault-Clear Waveform Definition [s ] (1) The RON,RCIN of the MOSFET is a characteristic discharge curve with respect to the external capacitor CRCIN. The time constant is defined by the external capacitor CRCIN and the RON,RCIN of the MOSFET. The output of current-sense comparator (CS_COMP) passes a noise filter, which inhibits an over-current shutdown caused by parasitic voltage spikes of VCS. This corresponds to a voltage level at the comparator of VCSTH+ - VCSHYS= 500mV - 60mV =440mV, where VCSHYS=60mV is the hysteresis of the current comparator (CS_COMP) as shown in Figure 41. 3. Noise Filter 3.1 Input Noise Filter Figure 43 shows the input noise filter method, which has symmetry duration between the input signal (tINPUT) and the output signal (tOUTPUT) and helps to reject noise spikes and short pulses. This input filter is applied to the HINx, LINx, and EN inputs. The upper pair of waveforms (Example A) shows an input signal duration (tINPUT) much longer than input filter time (tFLTIN); it is approximately the same duration between the input signal time (tINPUT) and the output signal time (tOUTPUT). The lower pair of waveforms (Example B) shows an input signal time (tINPUT) slightly longer than input filter time (tFLTIN); it is approximately the same duration between input signal time (tINPUT) and the output signal time (tOUTPUT). VDD RFO FO VREF To low side output Fault VDD_UVLO Q R SET DOMINANT LATCH S SOFT-OFF ISOFT To COM CS LEB iRCIN RCIN VRCIN,TH = 3.3V VRCIN,HYS= 0.7V CS_COMP 3.3V CRCIN 0.5V Protection Circuit Figure 41. Over-Current Protection Figure 42 shows the waveform definitions of RCIN, FO FO and the low-side driver, which uses a soft turn-off method when an under-voltage condition of the low-side gate driver supply voltage (VDD) or the current-sense pin (CS) recognizes a fault. Once a fault condition occurs, the FO pin is internally pulled to COM and all outputs (HO1,2,3 and LO1,2,3) of the gate driver are turned off. Low-side outputs decline linearly by the internal sink current source (ISOFT=40mA) for soft turn-off, as shown in Figure 42. Figure 43. Input Noise Filter Definition © 2010 Fairchild Semiconductor Corporation FAN7389 • Rev. 1.0.0 www.fairchildsemi.com 15 FAN7389 — 3-Phase Half-Bridge Gate Driver IC 3.2. Short-Pulsed Input Noise Rejection Method The input filter circuitry provides protection against short-pulsed input signals (HINx, LINx, and EN) on the input signal lines by applied noise signal. If the input signal duration is less than input filter time (tFLT,IN), the output does not change states. Example A and B of the Figure 44 show the input and output waveforms with short-pulsed noise spikes with a duration less than input filter time; the output does not change states. Figure 44. Noise Rejecting Input Filter Definition Figure 45 shows the characteristics of the input filters while receiving narrow ON and OFF pulses. If input signal pulse duration, PW IN, is less than input filter time, tFLT,IN; the output pulse, PW OUT, is zero. The input signal is rejected by input filter. Once the input signal pulse duration, PW IN, exceeds input filter time, tFLT,IN, the output pulse durations, PW OUT, matches the input pulse durations, PW IN. FAN7389 input filter time, tFLT,IN, is about 250ns for the high- and low-side outputs. Figure 45. Input Filter Characteristic of Narrow ON © 2010 Fairchild Semiconductor Corporation FAN7389 • Rev. 1.0.0 www.fairchildsemi.com 16 Package Dimensions 15.40±0.20 13.970 24 B 13 A 14.52 7.50±0.10 10.325 10.95 9.2 1 PIN ONE INDICATOR 0.51 0.35 0.25 12 1.27 M CBA 1.75 TYP 0.55 TYP 1.27 TYP LAND PATTERN RECOMMENDATION 2.65 MAX SEE DETAIL A C 0.10 C 0.20±0.10 0.75 0.25 0.33 0.20 SEATING PLANE X 45° NOTES: UNLESS OTHERWISE SPECIFIED (R0.10) GAGE PLANE (R0.10) 8° 0° 0.25 A) THIS PACKAGE CONFORMS TO JEDEC MS-013, ISSUE E, DATED SEPT 2005. B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE MOLD FLASH OR BURRS. D) LANDPATERN STANDARD: SOIC127P1030X265-24L E) DRAWING FILENAME: MKT-M24BREV2 0.40~1.27 (1.40) SEATING PLANE DETAIL A SCALE: 2:1 Figure 46. 24-Lead Small Outline Integrated Circuit (24-Wide Body SOIC) Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. © 2010 Fairchild Semiconductor Corporation FAN7389 • Rev. 1.0.0 www.fairchildsemi.com 17 FAN7389 — 3-Phase Half-Bridge Gate Driver IC © 2010 Fairchild Semiconductor Corporation FAN7389 • Rev. 1.0.0 www.fairchildsemi.com 18