FDB8896

FDB8896 May 2008 tm FDB8896 N-Channel PowerTrench® MOSFET 30V, 93A, 5.7mΩ General Description This N-Channel MOSFET has been designed specifically to improve the overall efficiency of DC/DC converters using either synchronous or conventional switching PWM controllers. It has been optimized for low gate charge, low rDS(ON) and fast switching speed. Features • rDS(ON) = 5.7mΩ VGS = 10V, ID = 35A , , • rDS(ON) = 6.8mΩ VGS = 4.5V, ID = 35A • High performance trench technology for extremely low rDS(ON) • Low gate charge Applications • DC/DC converters • High power and current handling capability GATE D SOURCE TO-263AB FDB SERIES DRAIN (FLANGE) G S MOSFET Maximum Ratings TC = 25°C unless otherwise noted Symbol VDSS VGS Parameter Drain to Source Voltage Gate to Source Voltage Drain Current Continuous (TC = 25oC, VGS = 10V) (Note 1) ID Continuous (TC = 25oC, VGS = 4.5V) (Note 1) Continuous (Tamb = 25oC, VGS = 10V, with Rθ JA = 43oC/W) Pulsed EAS PD TJ, TSTG Single Pulse Avalanche Energy (Note 2) Power dissipation Derate above 25oC Operating and Storage Temperature 93 85 19 Figure 4 74 80 0.53 -55 to 175 A A A A mJ W W/oC oC Ratings 30 ±20 Units V V Thermal Characteristics RθJC RθJA RθJA Thermal Resistance Junction to Case TO-263 Thermal Resistance Junction to Ambient TO-263 ( Note 3) Thermal Resistance Junction to Ambient TO-263, 1in2 copper pad area 1.88 62 43 o o C/W C/W oC/W Package Marking and Ordering Information Device Marking FDB8896 Device FDB8896 Package TO-263AB Reel Size 330mm Tape Width 24mm Quantity 800 units ©2008 Fairchild Semiconductor Corporation FDB8896 Rev. B2 FDB8896 Electrical Characteristics TC = 25°C unless otherwise noted Symbol Parameter Test Conditions Min Typ Max Units Off Characteristics BVDSS IDSS IGSS Drain to Source Breakdown Voltage Zero Gate Voltage Drain Current Gate to Source Leakage Current ID = 250µA, VGS = 0V VDS = 24V VGS = 0V VGS = ±20V TC = 150oC 30 1 250 ±100 V µA nA On Characteristics VGS(TH) Gate to Source Threshold Voltage VGS = VDS, ID = 250µA ID = 35A, VGS = 10V rDS(ON) Drain to Source On Resistance ID = 35A, VGS = 4.5V ID = 35A, VGS = 10V, TJ = 175oC 1.2 2.5 V Ω 0.0049 0.0057 0.0059 0.0068 0.0078 0.0094 Dynamic Characteristics CISS COSS CRSS RG Qg(TOT) Qg(5) Qg(TH) Qgs Qgs2 Qgd Input Capacitance Output Capacitance Reverse Transfer Capacitance Gate Resistance Total Gate Charge at 10V Total Gate Charge at 5V Threshold Gate Charge Gate to Source Gate Charge Gate Charge Threshold to Plateau Gate to Drain “Miller” Charge (VGS = 10V) VDD = 15V, ID = 35A VGS = 4.5V, RGS = 6.2Ω 9 102 58 44 167 153 ns ns ns ns ns ns VDS = 15V, VGS = 0V, f = 1MHz VGS = 0.5V, f = 1MHz VGS = 0V to 10V VGS = 0V to 5V VGS = 0V to 1V VDD = 15V ID = 35A Ig = 1.0mA 2525 490 300 2.3 48 25 2.3 8 5.7 9.5 67 36 3.0 pF pF pF Ω nC nC nC nC nC nC Switching Characteristics tON td(ON) tr td(OFF) tf tOFF Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time Drain-Source Diode Characteristics VSD trr QRR Source to Drain Diode Voltage Reverse Recovery Time Reverse Recovered Charge ISD = 35A ISD = 20A ISD = 35A, dISD/dt = 100A/µs ISD = 35A, dISD/dt = 100A/µs 1.25 1.0 27 12 V V ns nC Notes: 1: Package current limitation is 80A. 2: Starting TJ = 25°C, L = 36µH, IAS = 64A, VDD = 27V, VGS = 10V. 3: Pulse width = 100s. 4 ©2008 Fairchild Semiconductor Corporation FDB8896 Rev. B2 FDB8896 Typical Characteristics TC = 25°C unless otherwise noted 1.2 100 CURRENT LIMITED BY PACKAGE 80 ID, DRAIN CURRENT (A) 0.8 VGS = 10V 60 VGS = 4.5V 40 POWER DISSIPATION MULTIPLIER 1.0 0.6 0.4 0.2 20 0 0 25 50 75 100 125 150 175 TC , CASE TEMPERATURE (oC) 0 25 50 75 100 125 150 175 TC, CASE TEMPERATURE (oC) Figure 1. Normalized Power Dissipation vs Case Temperature 2 1 DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.01 Figure 2. Maximum Continuous Drain Current vs Case Temperature ZθJC, NORMALIZED THERMAL IMPEDANCE PDM 0.1 t1 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJC x RθJC + TC 10-3 10-2 t, RECTANGULAR PULSE DURATION (s) 10-1 100 101 SINGLE PULSE 0.01 10-5 10-4 Figure 3. Normalized Maximum Transient Thermal Impedance 1000 TC = 25oC TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT AS FOLLOWS: I = I25 VGS = 4.5V 175 - TC 150 IDM, PEAK CURRENT (A) 100 50 10-5 10-4 10-3 10-2 t, PULSE WIDTH (s) 10-1 100 101 Figure 4. Peak Current Capability ©2008 Fairchild Semiconductor Corporation FDB8896 Rev. B2 FDB8896 Typical Characteristics TC = 25°C unless otherwise noted 1000 10µs ID, DRAIN CURRENT (A) 100 100µs 10 OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) 500 If R = 0 tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD) If R ≠ 0 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1] 100 IAS, AVALANCHE CURRENT (A) STARTING TJ = 25oC 10 1ms 10ms DC 1 SINGLE PULSE TJ = MAX RATED TC = 25oC 0.1 1 10 VDS, DRAIN TO SOURCE VOLTAGE (V) STARTING TJ = 150oC 1 60 0.01 0.1 1 10 tAV, TIME IN AVALANCHE (ms) 100 Figure 5. Forward Bias Safe Operating Area NOTE: Refer to Fairchild Application Notes AN7514 and AN7515 Figure 6. Unclamped Inductive Switching Capability 160 VGS = 10V VGS = 5V ID, DRAIN CURRENT (A) 120 VGS = 4V 160 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX VDD = 15V ID , DRAIN CURRENT (A) 120 25oC TJ = 80 80 VGS = 3V 40 40 TJ = 0 1.5 175oC TJ = -55oC TC = 25oC PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX 0 2.0 2.5 3.0 3.5 4 0 0.25 0.5 0.75 1.0 1.25 1.5 VGS , GATE TO SOURCE VOLTAGE (V) VDS , DRAIN TO SOURCE VOLTAGE (V) Figure 7. Transfer Characteristics 14 NORMALIZED DRAIN TO SOURCE ON RESISTANCE ID = 35A rDS(ON), DRAIN TO SOURCE ON RESISTANCE (mΩ) 12 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX Figure 8. Saturation Characteristics 1.6 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX 1.4 10 1.2 8 1.0 6 ID = 1A 0.8 VGS = 10V, ID = 35A 4 2 4 6 8 10 VGS, GATE TO SOURCE VOLTAGE (V) 0.6 -80 -40 0 40 80 120 TJ, JUNCTION TEMPERATURE (oC) 160 200 Figure 9. Drain to Source On Resistance vs Gate Voltage and Drain Current Figure 10. Normalized Drain to Source On Resistance vs Junction Temperature ©2008 Fairchild Semiconductor Corporation FDB8896 Rev. B2 FDB8896 Typical Characteristics TC = 25°C unless otherwise noted 1.2 VGS = VDS, ID = 250µA NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE 1.2 ID = 250µA NORMALIZED GATE THRESHOLD VOLTAGE 1.0 1.1 0.8 1.0 0.6 0.4 -80 -40 0 40 80 120 160 200 0.9 -80 -40 0 40 80 120 160 200 TJ, JUNCTION TEMPERATURE (oC) TJ , JUNCTION TEMPERATURE (oC) Figure 11. Normalized Gate Threshold Voltage vs Junction Temperature 5000 CISS = CGS + CGD Figure 12. Normalized Drain to Source Breakdown Voltage vs Junction Temperature 10 VGS , GATE TO SOURCE VOLTAGE (V) VDD = 15V 8 C, CAPACITANCE (pF) 1000 CRSS = CGD COSS ≅ CDS + CGD 6 4 WAVEFORMS IN DESCENDING ORDER: ID = 35A ID = 16A 0 10 20 30 40 50 2 VGS = 0V, f = 1MHz 100 0.1 0 1 10 VDS , DRAIN TO SOURCE VOLTAGE (V) 30 Qg, GATE CHARGE (nC) Figure 13. Capacitance vs Drain to Source Voltage Figure 14. Gate Charge Waveforms for Constant Gate Current ©2008 Fairchild Semiconductor Corporation FDB8896 Rev. B2 FDB8896 Test Circuits and Waveforms VDS BVDSS L VARY tP TO OBTAIN REQUIRED PEAK IAS VGS DUT tP 0V RG IAS VDD VDD tP VDS + IAS 0.01Ω 0 tAV Figure 15. Unclamped Energy Test Circuit Figure 16. Unclamped Energy Waveforms VDS VDD L VGS VDS Qg(5) VDD DUT Ig(REF) VGS = 1V 0 Qg(TH) Qgs Ig(REF) 0 Qgd Qgs2 VGS = 5V Qg(TOT) VGS VGS = 10V + Figure 17. Gate Charge Test Circuit Figure 18. Gate Charge Waveforms VDS tON td(ON) RL VDS 90% tr tOFF td(OFF) tf 90% VGS + VDD DUT 0 10% 10% RGS VGS VGS 0 10% 50% PULSE WIDTH 90% 50% Figure 19. Switching Time Test Circuit Figure 20. Switching Time Waveforms ©2008 Fairchild Semiconductor Corporation FDB8896 Rev. B2 FDB8896 Thermal Resistance vs. Mounting Pad Area The maximum rated junction temperature, TJM, and the thermal resistance of the heat dissipating path determines the maximum allowable device power dissipation, PDM, in an application. Therefore the application’s ambient temperature, TA (oC), and thermal resistance RθJA (oC/W) must be reviewed to ensure that TJM is never exceeded. Equation 1 mathematically represents the relationship and serves as the basis for establishing the rating of the part. ( T JM – TA ) P DM = ----------------------------Rθ JA 80 RθJA = 26.51+ 19.84/(0.262+Area) EQ.2 RθJA = 26.51+ 128/(1.69+Area) EQ.3 60 RθJA (oC/W) 40 20 0.1 (0.645) 1 (6.45) AREA, TOP COPPER AREA in2 (cm2) 10 (64.5) (EQ. 1) In using surface mount devices such as the TO-263 package, the environment in which it is applied will have a significant influence on the part’s current and maximum power dissipation ratings. Precise determination of PDM is complex and influenced by many factors: 1. Mounting pad area onto which the device is attached and whether there is copper on one side or both sides of the board. 2. The number of copper layers and the thickness of the board. 3. The use of external heat sinks. 4. The use of thermal vias. 5. Air flow and board orientation. 6. For non steady state applications, the pulse width, the duty cycle and the transient thermal response of the part, the board and the environment they are in. Fairchild provides thermal information to assist the designer’s preliminary application evaluation. Figure 21 defines the RθJA for the device as a function of the top copper (component side) area. This is for a horizontally positioned FR-4 board with 1oz copper after 1000 seconds of steady state power with no air flow. This graph provides the necessary information for calculation of the steady state junction temperature or power dissipation. Pulse applications can be evaluated using the Fairchild device Spice thermal model or manually utilizing the normalized maximum transient thermal impedance curve. Thermal resistances corresponding to other copper areas can be obtained from Figure 21 or by calculation using Equation 2 or 3. Equation 2 is used for copper area defined in inches square and equation 3 is for area in centimeters square. The area, in square inches or square centimeters is the top copper area including the gate and source pads. Figure 21. Thermal Resistance vs Mounting Pad Area R θ JA = 26.51 + -----------------------------------128 ( 1.69 + Area ) 19.84 ( 0.262 + Area ) (EQ. 2) Area in Inches Squared R θ JA = 26.51 + --------------------------------- (EQ. 3) Area in Centimeters Squared ©2008 Fairchild Semiconductor Corporation FDB8896 Rev. B2 FDB8896 PSPICE Electrical Model .SUBCKT FDB8896 2 1 3 ; rev December 2003 Ca 12 8 2.3e-9 Cb 15 14 2.3e-9 Cin 6 8 2.3e-9 Dbody 7 5 DbodyMOD Dbreak 5 11 DbreakMOD Dplcap 10 5 DplcapMOD Ebreak 11 7 17 18 33 Eds 14 8 5 8 1 Egs 13 8 6 8 1 Esg 6 10 6 8 1 Evthres 6 21 19 8 1 Evtemp 20 6 18 22 1 It 8 17 1 Lgate 1 9 5.5e-9 Ldrain 2 5 1.0e-9 Lsource 3 7 2.7e-9 S1A S2A 13 8 S1B CA 13 + EGS 6 8 EDS 14 13 S2B CB + 5 8 8 RVTHRES 14 IT VBAT + 22 15 17 ESG + LGATE GATE 1 RLGATE CIN EVTEMP RGATE + 18 22 9 20 6 MSTRO LSOURCE 8 RSOURCE RLSOURCE 12 RBREAK 18 RVTEMP 19 7 SOURCE 3 6 8 EVTHRES + 19 8 LDRAIN DPLCAP 10 RSLC1 51 ESLC 50 RDRAIN 21 16 RLDRAIN DBREAK 11 + 17 EBREAK 18 MWEAK MMED 5 DRAIN 2 RSLC2 5 51 - RLgate 1 9 55 RLdrain 2 5 10 RLsource 3 7 27 Mmed 16 6 8 8 MmedMOD Mstro 16 6 8 8 MstroMOD Mweak 16 21 8 8 MweakMOD Rbreak 17 18 RbreakMOD 1 Rdrain 50 16 RdrainMOD 2.1e-3 Rgate 9 20 2.3 RSLC1 5 51 RSLCMOD 1e-6 RSLC2 5 50 1e3 Rsource 8 7 RsourceMOD 2e-3 Rvthres 22 8 RvthresMOD 1 Rvtemp 18 19 RvtempMOD 1 S1a 6 12 13 8 S1AMOD S1b 13 12 13 8 S1BMOD S2a 6 15 14 13 S2AMOD S2b 13 15 14 13 S2BMOD Vbat 22 19 DC 1 ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*500),10))} .MODEL DbodyMOD D (IS=4E-12 IKF=10 N=1.01 RS=2.6e-3 TRS1=8e-4 TRS2=2e-7 + CJO=8.8e-10 M=0.57 TT=1e-16 XTI=2.2) .MODEL DbreakMOD D (RS=8e-2 TRS1=1e-3 TRS2=-8.9e-6) .MODEL DplcapMOD D (CJO=9.4e-10 IS=1e-30 N=10 M=0.4) .MODEL MmedMOD NMOS (VTO=1.98 KP=10 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=2.3 T_ABS=25) .MODEL MstroMOD NMOS (VTO=2.4 KP=350 IS=1e-30 N=10 TOX=1 L=1u W=1u T_ABS=25) .MODEL MweakMOD NMOS (VTO=1.68 KP=0.05 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=23 RS=0.1 T_ABS=25) .MODEL RbreakMOD RES (TC1=8.3e-4 TC2=-4e-7) .MODEL RdrainMOD RES (TC1=1.2e-3 TC2=8e-6) .MODEL RSLCMOD RES (TC1=9e-4 TC2=1e-6) .MODEL RsourceMOD RES (TC1=7.5e-3 TC2=1e-6) .MODEL RvthresMOD RES (TC1=-2.4e-3 TC2=-8.8e-6) .MODEL RvtempMOD RES (TC1=-2.6e-3 TC2=2e-7) .MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-4 VOFF=-3) .MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-3 VOFF=-4) .MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-2 VOFF=-0.5) .MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-0.5 VOFF=-2) .ENDS Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley. ©2008 Fairchild Semiconductor Corporation + DBODY FDB8896 Rev. B2 FDB8896 SABER Electrical Model rev December 2003 template FDB8896 n2,n1,n3 =m_temp electrical n2,n1,n3 number m_temp=25 { var i iscl dp..model dbodymod = (isl=4e-12,ikf=10,nl=1.01,rs=2.6e-3,trs1=8e-4,trs2=2e-7,cjo=8.8e-10,m=0.57,tt=1e-16,xti=2.2) dp..model dbreakmod = (rs=8e-2,trs1=1e-3,trs2=-8.9e-6) dp..model dplcapmod = (cjo=9.4e-10,isl=10e-30,nl=10,m=0.4) m..model mmedmod = (type=_n,vto=1.98,kp=10,is=1e-30, tox=1) m..model mstrongmod = (type=_n,vto=2.4,kp=350,is=1e-30, tox=1) m..model mweakmod = (type=_n,vto=1.68,kp=0.05,is=1e-30, tox=1,rs=0.1) LDRAIN sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-4,voff=-3) DPLCAP 5 sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-3,voff=-4) 10 sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=-2,voff=-0.5) RLDRAIN RSLC1 sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=-0.5,voff=-2) 51 c.ca n12 n8 = 2.3e-9 RSLC2 c.cb n15 n14 = 2.3e-9 ISCL c.cin n6 n8 = 2.3e-9 dp.dbody n7 n5 = model=dbodymod dp.dbreak n5 n11 = model=dbreakmod dp.dplcap n10 n5 = model=dplcapmod spe.ebreak n11 n7 n17 n18 = 33 spe.eds n14 n8 n5 n8 = 1 spe.egs n13 n8 n6 n8 = 1 spe.esg n6 n10 n6 n8 = 1 spe.evthres n6 n21 n19 n8 = 1 spe.evtemp n20 n6 n18 n22 = 1 i.it n8 n17 = 1 l.lgate n1 n9 = 5.5e-9 l.ldrain n2 n5 = 1.0e-9 l.lsource n3 n7 = 2.7e-9 CA 12 S1B 13 + EGS 6 8 EDS LGATE GATE 1 RLGATE CIN ESG + EVTEMP RGATE + 18 22 9 20 6 MSTRO 8 6 8 EVTHRES + 19 8 50 RDRAIN 21 16 MWEAK MMED EBREAK + 17 18 DBREAK 11 DBODY DRAIN 2 LSOURCE 7 RLSOURCE SOURCE 3 RSOURCE S1A 13 8 S2A 14 13 S2B CB + 5 8 8 RVTHRES 14 IT VBAT + 22 15 17 RBREAK 18 RVTEMP 19 res.rlgate n1 n9 = 55 res.rldrain n2 n5 = 10 res.rlsource n3 n7 = 27 m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u, temp=m_temp m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u, temp=m_temp m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u, temp=m_temp res.rbreak n17 n18 = 1, tc1=8.3e-4,tc2=-4e-7 res.rdrain n50 n16 = 2.1e-3, tc1=1.2e-3,tc2=8e-6 res.rgate n9 n20 = 2.3 res.rslc1 n5 n51 = 1e-6, tc1=9e-4,tc2=1e-6 res.rslc2 n5 n50 = 1e3 res.rsource n8 n7 = 2e-3, tc1=7.5e-3,tc2=1e-6 res.rvthres n22 n8 = 1, tc1=-2.4e-3,tc2=-8.8e-6 res.rvtemp n18 n19 = 1, tc1=-2.6e-3,tc2=2e-7 sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod v.vbat n22 n19 = dc=1 equations { i (n51->n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/500))** 10)) } } ©2008 Fairchild Semiconductor Corporation FDB8896 Rev. B2 FDB8896 PSPICE Thermal Model REV 23 December 2003 FDB8896T CTHERM1 TH 6 9e-4 CTHERM2 6 5 1e-3 CTHERM3 5 4 2e-3 CTHERM4 4 3 3e-3 CTHERM5 3 2 7e-3 CTHERM6 2 TL 8e-2 RTHERM1 TH 6 3.0e-2 RTHERM2 6 5 1.0e-1 RTHERM3 5 4 1.8e-1 RTHERM4 4 3 2.8e-1 RTHERM5 3 2 4.5e-1 RTHERM6 2 TL 4.6e-1 th JUNCTION RTHERM1 CTHERM1 6 RTHERM2 CTHERM2 5 SABER Thermal Model SABER thermal model FDB8896T template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th 6 =9e-4 ctherm.ctherm2 6 5 =1e-3 ctherm.ctherm3 5 4 =2e-3 ctherm.ctherm4 4 3 =3e-3 ctherm.ctherm5 3 2 =7e-3 ctherm.ctherm6 2 tl =8e-2 rtherm.rtherm1 th 6 =3.0e-2 rtherm.rtherm2 6 5 =1.0e-1 rtherm.rtherm3 5 4 =1.8e-1 rtherm.rtherm4 4 3 =2.8e-1 rtherm.rtherm5 3 2 =4.5e-1 rtherm.rtherm6 2 tl =4.6e-1 } RTHERM3 CTHERM3 4 RTHERM4 CTHERM4 3 RTHERM5 CTHERM5 2 RTHERM6 CTHERM6 tl CASE ©2008 Fairchild Semiconductor Corporation FDB8896 Rev. B2 FDB8896 TRADEMARKS The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidianries, and is not intended to be an exhaustive list of all such trademarks. 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Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. A critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Advance Information Product Status Formative or In Design Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve the design. This datasheet contains specifications on a product that is discontinued by Fairchild Semiconductor. The datasheet is for reference information only. Rev. I34 FDB8896 Rev. B2 Preliminary First Production No Identification Needed Obsolete Full Production Not In Production