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N-Channel PowerTrench® MOSFET
30V, 93A, 5.7mΩ
General Description
Features
• rDS(ON) = 5.7mΩ, VGS = 10V, ID = 35A
• rDS(ON) = 6.8mΩ, VGS = 4.5V, ID = 35A
This N-Channel MOSFET has been designed specifically to
improve the overall efficiency of DC/DC converters using
either synchronous or conventional switching PWM
controllers. It has been optimized for low gate charge, low
rDS(ON) and fast switching speed.
• High performance trench technology for extremely low
rDS(ON)
• Low gate charge
• High power and current handling capability
• Qualified to AEC Q101
Applications
• RoHS Compliant
• DC/DC converters
®
FDB8896-F085 N-Channel PowerTrench MOSFET
FDB8896-F085
D
GATE
G
SOURCE
TO-263AB
FDB SERIES
DRAIN
(FLANGE)
S
MOSFET Maximum Ratings TC = 25°C unless otherwise noted
Parameter
S
Symbol
VDSS
Drain to Source Voltage
Ratings
30
Units
V
VGS
Gate to Source Voltage
±20
V
93
A
Drain Current
Continuous (TC = 25oC, VGS = 10V) (Note 1)
ID
Continuous (TC =
25oC,
VGS = 4.5V) (Note 1)
Continuous (Tamb = 25oC, VGS = 10V, with RθJA = 43oC/W)
Pulsed
EAS
Single Pulse Avalanche Energy (Note 2)
Power dissipation
PD
Derate above 25oC
TJ, TSTG
Operating and Storage Temperature
85
A
19
A
Figure 4
A
74
mJ
80
W
0.53
W/oC
-55 to 175
oC
Thermal Characteristics
1.88
o
C/W
Thermal Resistance Junction to Ambient TO-263 ( Note 3)
62
o
C/W
Thermal Resistance Junction to Ambient TO-263, 1in2 copper pad area
43
oC/W
RθJC
Thermal Resistance Junction to Case TO-263
RθJA
RθJA
Package Marking and Ordering Information
Device Marking
FDB8896
Device
FDB8896-F085
©2010 Semiconductor Components Industries, LLC.
September-2017, Rev. 1
Package
TO-263AB
Reel Size
330mm
Tape Width
24mm
Quantity
800 units
Publication Order Number:
FDB8896-F085/D
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
V
Off Characteristics
BVDSS
Drain to Source Breakdown Voltage
IDSS
Zero Gate Voltage Drain Current
IGSS
Gate to Source Leakage Current
ID = 250μA, VGS = 0V
VDS = 24V
VGS = 0V
TC = 150oC
VGS = ±20V
30
-
-
-
-
1
-
-
250
-
-
±100
nA
-
2.5
V
μA
On Characteristics
VGS(TH)
rDS(ON)
Gate to Source Threshold Voltage
Drain to Source On Resistance
VGS = VDS, ID = 250μA
1.2
ID = 35A, VGS = 10V
-
0.0049 0.0057
ID = 35A, VGS = 4.5V
-
0.0059 0.0068
ID = 35A, VGS = 10V,
TJ = 175oC
-
0.0078 0.0094
Ω
Dynamic Characteristics
Input Capacitance
COSS
Output Capacitance
CRSS
Reverse Transfer Capacitance
RG
Gate Resistance
Qg(TOT)
Total Gate Charge at 10V
-
2525
-
-
490
-
pF
-
300
-
pF
VGS = 0.5V, f = 1MHz
-
2.3
-
Ω
VGS = 0V to 10V
-
48
67
nC
VDS = 15V, VGS = 0V,
f = 1MHz
Qg(5)
Total Gate Charge at 5V
VGS = 0V to 5V
Qg(TH)
Threshold Gate Charge
VGS = 0V to 1V
Qgs
Gate to Source Gate Charge
Qgs2
Gate Charge Threshold to Plateau
Qgd
Gate to Drain “Miller” Charge
Switching Characteristics
VDD = 15V
ID = 35A
Ig = 1.0mA
pF
-
25
36
nC
-
2.3
3.0
nC
-
8
-
nC
-
5.7
-
nC
-
9.5
-
nC
(VGS = 10V)
tON
Turn-On Time
-
-
167
ns
td(ON)
Turn-On Delay Time
-
9
-
ns
tr
Rise Time
td(OFF)
Turn-Off Delay Time
tf
tOFF
-
102
-
ns
-
58
-
ns
Fall Time
-
44
-
ns
Turn-Off Time
-
-
153
ns
V
VDD = 15V, ID = 35A
VGS = 4.5V, RGS = 6.2Ω
Drain-Source Diode Characteristics
ISD = 35A
-
-
1.25
ISD = 20A
-
-
1.0
V
Reverse Recovery Time
ISD = 35A, dISD/dt = 100A/μs
-
-
27
ns
Reverse Recovered Charge
ISD = 35A, dISD/dt = 100A/μs
-
-
12
nC
VSD
Source to Drain Diode Voltage
trr
QRR
Notes:
1: Package current limitation is 80A.
2: Starting TJ = 25°C, L = 36μH, IAS = 64A, VDD = 27V, VGS = 10V.
3: Pulse width = 100s.
4
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2
®
CISS
FDB8896-F085 N-Channel PowerTrench MOSFET
Electrical Characteristics TC = 25°C unless otherwise noted
100
CURRENT LIMITED
BY PACKAGE
1.0
80
ID, DRAIN CURRENT (A)
POWER DISSIPATION MULTIPLIER
1.2
0.8
0.6
0.4
VGS = 10V
60
VGS = 4.5V
40
20
0.2
0
0
25
50
75
100
150
125
0
175
25
50
75
TC , CASE TEMPERATURE (oC)
100
125
150
175
TC, CASE TEMPERATURE (oC)
Figure 1. Normalized Power Dissipation vs Case
Temperature
Figure 2. Maximum Continuous Drain Current vs
Case Temperature
2
ZθJC, NORMALIZED
THERMAL IMPEDANCE
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
0.1
0.05
0.02
0.01
®
1
PDM
0.1
t1
t2
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJC x RθJC + TC
SINGLE PULSE
0.01
10-5
10-4
10-3
10-2
10-1
100
101
t, RECTANGULAR PULSE DURATION (s)
Figure 3. Normalized Maximum Transient Thermal Impedance
1000
IDM, PEAK CURRENT (A)
TC = 25oC
FOR TEMPERATURES
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
ABOVE 25oC DERATE PEAK
CURRENT AS FOLLOWS:
175 - TC
I = I25
VGS = 4.5V
150
100
50
10-5
10-4
FDB8896-F085 N-Channel PowerTrench MOSFET
Typical Characteristics TC = 25°C unless otherwise noted
10-3
10-2
t, PULSE WIDTH (s)
Figure 4. Peak Current Capability
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3
10-1
100
101
500
1000
IAS, AVALANCHE CURRENT (A)
ID, DRAIN CURRENT (A)
10μs
100
100μs
10
OPERATION IN THIS
AREA MAY BE
LIMITED BY rDS(ON)
1ms
1
10ms
SINGLE PULSE
TJ = MAX RATED
TC = 25oC
If R = 0
tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)
If R ≠ 0
tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]
100
STARTING TJ = 25oC
10
DC
STARTING TJ = 150oC
1
0.1
1
60
10
0.01
0.1
1
10
tAV, TIME IN AVALANCHE (ms)
VDS, DRAIN TO SOURCE VOLTAGE (V)
Figure 5. Forward Bias Safe Operating Area
Figure 6. Unclamped Inductive Switching
Capability
160
160
VGS = 10V
®
VGS = 5V
ID, DRAIN CURRENT (A)
ID , DRAIN CURRENT (A)
PULSE DURATION = 80μs
DUTY CYCLE = 0.5% MAX
VDD = 15V
120
o
TJ = 25 C
80
40
o
TJ = 175 C
120
VGS = 4V
80
VGS = 3V
40
TC = 25oC
PULSE DURATION = 80μs
DUTY CYCLE = 0.5% MAX
TJ = -55oC
0
0
1.5
2.0
2.5
3.0
3.5
0
4
VGS , GATE TO SOURCE VOLTAGE (V)
0.25
0.5
0.75
1.0
1.25
1.5
VDS , DRAIN TO SOURCE VOLTAGE (V)
Figure 7. Transfer Characteristics
Figure 8. Saturation Characteristics
14
1.6
NORMALIZED DRAIN TO SOURCE
ON RESISTANCE
PULSE DURATION = 80μs
DUTY CYCLE = 0.5% MAX
ID = 35A
rDS(ON), DRAIN TO SOURCE
ON RESISTANCE (mΩ)
100
12
10
8
6
ID = 1A
PULSE DURATION = 80μs
DUTY CYCLE = 0.5% MAX
1.4
1.2
1.0
0.8
VGS = 10V, ID = 35A
4
2
4
6
8
10
0.6
-80
VGS, GATE TO SOURCE VOLTAGE (V)
Figure 9. Drain to Source On Resistance vs Gate
Voltage and Drain Current
-40
0
40
80
120
TJ, JUNCTION TEMPERATURE (oC)
160
Figure 10. Normalized Drain to Source On
Resistance vs Junction Temperature
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4
FDB8896-F085 N-Channel PowerTrench MOSFET
Typical Characteristics TC = 25°C unless otherwise noted
200
1.2
1.2
ID = 250μA
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
NORMALIZED GATE
THRESHOLD VOLTAGE
VGS = VDS, ID = 250μA
1.0
0.8
0.6
0.4
-80
-40
0
40
80
120
160
1.1
1.0
0.9
-80
200
-40
TJ, JUNCTION TEMPERATURE (oC)
Figure 11. Normalized Gate Threshold Voltage vs
Junction Temperature
40
120
160
200
10
COSS ≅ CDS + CGD
1000
CRSS = CGD
VDD = 15V
®
VGS , GATE TO SOURCE VOLTAGE (V)
CISS = CGS + CGD
8
6
4
WAVEFORMS IN
DESCENDING ORDER:
ID = 35A
ID = 16A
2
VGS = 0V, f = 1MHz
100
0.1
80
Figure 12. Normalized Drain to Source
Breakdown Voltage vs Junction Temperature
5000
C, CAPACITANCE (pF)
0
TJ , JUNCTION TEMPERATURE (oC)
0
30
1
10
VDS , DRAIN TO SOURCE VOLTAGE (V)
0
10
20
30
40
50
Qg, GATE CHARGE (nC)
Figure 13. Capacitance vs Drain to Source
Voltage
FDB8896-F085 N-Channel PowerTrench MOSFET
Typical Characteristics TC = 25°C unless otherwise noted
Figure 14. Gate Charge Waveforms for Constant
Gate Current
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5
VDS
BVDSS
tP
L
VDS
VARY tP TO OBTAIN
REQUIRED PEAK IAS
IAS
+
RG
VDD
VDD
-
VGS
DUT
tP
IAS
0V
0
0.01Ω
tAV
Figure 15. Unclamped Energy Test Circuit
Figure 16. Unclamped Energy Waveforms
®
VDS
FDB8896-F085 N-Channel PowerTrench MOSFET
Test Circuits and Waveforms
VDD
Qg(TOT)
VDS
L
VGS
VGS = 10V
VGS
Qg(5)
+
Qgs2
VDD
VGS = 5V
DUT
VGS = 1V
Ig(REF)
0
Qg(TH)
Qgs
Qgd
Ig(REF)
0
Figure 17. Gate Charge Test Circuit
Figure 18. Gate Charge Waveforms
VDS
tON
tOFF
td(ON)
td(OFF)
RL
tf
tr
VDS
90%
90%
+
VGS
VDD
-
10%
0
10%
DUT
90%
RGS
VGS
VGS
0
Figure 19. Switching Time Test Circuit
50%
10%
50%
PULSE WIDTH
Figure 20. Switching Time Waveforms
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6
( T JM – TA )
P DM = ----------------------------Rθ JA
80
RθJA = 26.51+ 19.84/(0.262+Area) EQ.2
RθJA = 26.51+ 128/(1.69+Area) EQ.3
60
RθJA (oC/W)
The maximum rated junction temperature, TJM, and the
thermal resistance of the heat dissipating path determines
the maximum allowable device power dissipation, PDM, in an
application.
Therefore the application’s ambient
temperature, TA (oC), and thermal resistance RθJA (oC/W)
must be reviewed to ensure that TJM is never exceeded.
Equation 1 mathematically represents the relationship and
serves as the basis for establishing the rating of the part.
40
(EQ. 1)
In using surface mount devices such as the TO-263
package, the environment in which it is applied will have a
significant influence on the part’s current and maximum
power dissipation ratings. Precise determination of PDM is
complex and influenced by many factors:
1. Mounting pad area onto which the device is attached and
whether there is copper on one side or both sides of the
board.
20
0.1
1
10
(0.645)
(6.45)
AREA, TOP COPPER AREA in2 (cm2)
(64.5)
Figure 21. Thermal Resistance vs Mounting
Pad Area
2. The number of copper layers and the thickness of the
board.
®
3. The use of external heat sinks.
4. The use of thermal vias.
5. Air flow and board orientation.
6. For non steady state applications, the pulse width, the
duty cycle and the transient thermal response of the part,
the board and the environment they are in.
ON Semiconductor provides thermal information to
designer’s
preliminary
application
assist
the
evaluation. Figure 21
defines the RθJA for the device as a function of the top
copper (component side) area. This is for a horizontally
positioned FR-4 board with 1oz copper after 1000 seconds
of steady state power with no air flow. This graph provides
the necessary information for calculation of the steady state
junction temperature or power dissipation. Pulse
be
evaluated
using
the
ON
applications
can
Semiconductor device Spice thermal model or manually
utilizing the normalized maximum transient thermal
impedance curve.
Thermal resistances corresponding to other copper areas
can be obtained from Figure 21 or by calculation using
Equation 2 or 3. Equation 2 is used for copper area defined
in inches square and equation 3 is for area in centimeters
square. The area, in square inches or square centimeters is
19.84
(0.262 + Area)
R θJA = 26.51 + -------------------------------------
(EQ. 2)
Area in Inches Squared
128
(1.69 + Area)
R θJA = 26.51 + ----------------------------------
FDB8896-F085 N-Channel PowerTrench MOSFET
Thermal Resistance vs. Mounting Pad Area
(EQ. 3)
Area in Centimeters Squared
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7
.SUBCKT FDB8896 2 1 3 ; rev December 2003
Ca 12 8 2.3e-9
Cb 15 14 2.3e-9
Cin 6 8 2.3e-9
LDRAIN
DPLCAP
10
RSLC2
5
51
EVTHRES
+ 19 8
+
LGATE
GATE
1
EVTEMP
RGATE +
18 22
9
20
11
+
17
EBREAK 18
-
21
16
DBODY
MWEAK
6
MMED
MSTRO
RLGATE
LSOURCE
CIN
Lgate 1 9 5.5e-9
Ldrain 2 5 1.0e-9
Lsource 3 7 2.7e-9
8
7
SOURCE
3
RSOURCE
RLSOURCE
S1A
RLgate 1 9 55
RLdrain 2 5 10
RLsource 3 7 27
12
S2A
13
8
15
14
13
S1B
CA
RBREAK
17
18
RVTEMP
S2B
13
19
CB
6
8
EGS
VBAT
5
8
EDS
-
IT
14
+
+
-
Rbreak 17 18 RbreakMOD 1
Rdrain 50 16 RdrainMOD 2.1e-3
Rgate 9 20 2.3
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
Rsource 8 7 RsourceMOD 2e-3
Rvthres 22 8 RvthresMOD 1
Rvtemp 18 19 RvtempMOD 1
S1a 6 12 13 8 S1AMOD
S1b 13 12 13 8 S1BMOD
S2a 6 15 14 13 S2AMOD
S2b 13 15 14 13 S2BMOD
+
8
22
RVTHRES
Vbat 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*500),10))}
.MODEL DbodyMOD D (IS=4E-12 IKF=10 N=1.01 RS=2.6e-3 TRS1=8e-4 TRS2=2e-7
+ CJO=8.8e-10 M=0.57 TT=1e-16 XTI=2.2)
.MODEL DbreakMOD D (RS=8e-2 TRS1=1e-3 TRS2=-8.9e-6)
.MODEL DplcapMOD D (CJO=9.4e-10 IS=1e-30 N=10 M=0.4)
.MODEL MmedMOD NMOS (VTO=1.98 KP=10 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=2.3 T_ABS=25)
.MODEL MstroMOD NMOS (VTO=2.4 KP=350 IS=1e-30 N=10 TOX=1 L=1u W=1u T_ABS=25)
.MODEL MweakMOD NMOS (VTO=1.68 KP=0.05 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=23 RS=0.1 T_ABS=25)
.MODEL RbreakMOD RES (TC1=8.3e-4 TC2=-4e-7)
.MODEL RdrainMOD RES (TC1=1.2e-3 TC2=8e-6)
.MODEL RSLCMOD RES (TC1=9e-4 TC2=1e-6)
.MODEL RsourceMOD RES (TC1=7.5e-3 TC2=1e-6)
.MODEL RvthresMOD RES (TC1=-2.4e-3 TC2=-8.8e-6)
.MODEL RvtempMOD RES (TC1=-2.6e-3 TC2=2e-7)
.MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-4 VOFF=-3)
.MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-3 VOFF=-4)
.MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-2 VOFF=-0.5)
.MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-0.5 VOFF=-2)
.ENDS
Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank
Wheatley.
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8
®
Mmed 16 6 8 8 MmedMOD
Mstro 16 6 8 8 MstroMOD
Mweak 16 21 8 8 MweakMOD
ESLC
50
RDRAIN
6
8
ESG
DBREAK
+
It 8 17 1
RLDRAIN
RSLC1
51
Dbody 7 5 DbodyMOD
Dbreak 5 11 DbreakMOD
Dplcap 10 5 DplcapMOD
Ebreak 11 7 17 18 33
Eds 14 8 5 8 1
Egs 13 8 6 8 1
Esg 6 10 6 8 1
Evthres 6 21 19 8 1
Evtemp 20 6 18 22 1
DRAIN
2
5
FDB8896-F085 N-Channel PowerTrench MOSFET
PSPICE Electrical Model
rev December 2003
template FDB8896 n2,n1,n3 =m_temp
electrical n2,n1,n3
number m_temp=25
{
var i iscl
dp..model dbodymod = (isl=4e-12,ikf=10,nl=1.01,rs=2.6e-3,trs1=8e-4,trs2=2e-7,cjo=8.8e-10,m=0.57,tt=1e-16,xti=2.2)
dp..model dbreakmod = (rs=8e-2,trs1=1e-3,trs2=-8.9e-6)
dp..model dplcapmod = (cjo=9.4e-10,isl=10e-30,nl=10,m=0.4)
m..model mmedmod = (type=_n,vto=1.98,kp=10,is=1e-30, tox=1)
m..model mstrongmod = (type=_n,vto=2.4,kp=350,is=1e-30, tox=1)
m..model mweakmod = (type=_n,vto=1.68,kp=0.05,is=1e-30, tox=1,rs=0.1)
LDRAIN
sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-4,voff=-3)
DPLCAP 5
sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-3,voff=-4)
10
sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=-2,voff=-0.5)
RLDRAIN
RSLC1
sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=-0.5,voff=-2)
51
c.ca n12 n8 = 2.3e-9
RSLC2
c.cb n15 n14 = 2.3e-9
ISCL
c.cin n6 n8 = 2.3e-9
EVTHRES
+ 19 8
+
LGATE
GATE
1
EVTEMP
RGATE + 18 22
9
20
21
11
DBODY
16
MWEAK
6
EBREAK
+
17
18
-
MMED
MSTRO
RLGATE
CIN
8
LSOURCE
7
RSOURCE
RLSOURCE
i.it n8 n17 = 1
S1A
12
l.lgate n1 n9 = 5.5e-9
l.ldrain n2 n5 = 1.0e-9
l.lsource n3 n7 = 2.7e-9
RBREAK
15
14
13
13
8
S1B
CA
res.rlgate n1 n9 = 55
res.rldrain n2 n5 = 10
res.rlsource n3 n7 = 27
S2A
17
18
RVTEMP
S2B
13
CB
6
8
EGS
19
-
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u, temp=m_temp
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u, temp=m_temp
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u, temp=m_temp
res.rbreak n17 n18 = 1, tc1=8.3e-4,tc2=-4e-7
res.rdrain n50 n16 = 2.1e-3, tc1=1.2e-3,tc2=8e-6
res.rgate n9 n20 = 2.3
res.rslc1 n5 n51 = 1e-6, tc1=9e-4,tc2=1e-6
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 2e-3, tc1=7.5e-3,tc2=1e-6
res.rvthres n22 n8 = 1, tc1=-2.4e-3,tc2=-8.8e-6
res.rvtemp n18 n19 = 1, tc1=-2.6e-3,tc2=2e-7
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/500))** 10))
}
}
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9
VBAT
5
8
EDS
-
IT
14
+
+
+
8
22
RVTHRES
SOURCE
3
®
spe.ebreak n11 n7 n17 n18 = 33
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evthres n6 n21 n19 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
RDRAIN
6
8
ESG
DBREAK
50
-
dp.dbody n7 n5 = model=dbodymod
dp.dbreak n5 n11 = model=dbreakmod
dp.dplcap n10 n5 = model=dplcapmod
DRAIN
2
FDB8896-F085 N-Channel PowerTrench MOSFET
SABER Electrical Model
th
JUNCTION
REV 23 December 2003
FDB8896T
CTHERM1 TH 6 9e-4
CTHERM2 6 5 1e-3
CTHERM3 5 4 2e-3
CTHERM4 4 3 3e-3
CTHERM5 3 2 7e-3
CTHERM6 2 TL 8e-2
RTHERM1
CTHERM1
6
RTHERM1 TH 6 3.0e-2
RTHERM2 6 5 1.0e-1
RTHERM3 5 4 1.8e-1
RTHERM4 4 3 2.8e-1
RTHERM5 3 2 4.5e-1
RTHERM6 2 TL 4.6e-1
RTHERM2
CTHERM2
5
SABER Thermal Model
RTHERM3
CTHERM3
4
RTHERM4
rtherm.rtherm1 th 6 =3.0e-2
rtherm.rtherm2 6 5 =1.0e-1
rtherm.rtherm3 5 4 =1.8e-1
rtherm.rtherm4 4 3 =2.8e-1
rtherm.rtherm5 3 2 =4.5e-1
rtherm.rtherm6 2 tl =4.6e-1
}
CTHERM4
3
RTHERM5
CTHERM5
2
CTHERM6
RTHERM6
tl
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10
CASE
®
SABER thermal model FDB8896T
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 6 =9e-4
ctherm.ctherm2 6 5 =1e-3
ctherm.ctherm3 5 4 =2e-3
ctherm.ctherm4 4 3 =3e-3
ctherm.ctherm5 3 2 =7e-3
ctherm.ctherm6 2 tl =8e-2
FDB8896-F085 N-Channel PowerTrench MOSFET
PSPICE Thermal Model
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