FDC6320

October 1997 FDC6320C Dual N & P Channel , Digital FET General Description These dual N & P Channel logic level enhancement mode field effec transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. The device is an improved design especially for low voltage applications as a replacement for bipolar digital transistors in load switching applications. Since bias resistors are not required, this dual digital FET can replace several digital transistors with difference bias resistors. Features N-Ch 25 V, 0.22 A, RDS(ON) = 5 Ω @ VGS= 2.7 V. P-Ch 25 V, -0.12 A, RDS(ON) = 13 Ω @ VGS= -2.7 V. Very low level gate drive requirements allowing direct operation in 3 V circuits. VGS(th) < 1.5 V. Gate-Source Zener for ESD ruggedness. >6kV Human Body Model Replace NPN & PNP digital transistors. SOT-23 SuperSOTTM-6 SuperSOTTM-8 SO-8 SOT-223 SOIC-16 4 3 5 2 6 1 Absolute Maximum Ratings Symbol VDSS, VCC VGSS, VIN ID, IO PD TJ,TSTG ESD Parameter TA = 25oC unless other wise noted N-Channel 25 8 P-Channel -25 -8 -0.12 -0.5 0.9 0.7 -55 to 150 6 °C kV W Units V V A Drain-Source Voltage, Power Supply Voltage Gate-Source Voltage, Drain/Output Current - Continuous - Pulsed Maximum Power Dissipation (Note 1a) (Note 1b) 0.22 0.5 Operating and Storage Tempature Ranger Electrostatic Discharge Rating MIL-STD-883D Human Body Model (100pf / 1500 Ohm) THERMAL CHARACTERISTICS RθJA RθJC Thermal Resistance, Junction-to-Ambient Thermal Resistance, Junction-to-Case (Note 1a) (Note 1) 140 60 °C/W °C/W © 1997 Fairchild Semiconductor Corporation FDC6320C.Rev C DMOS Electrical Characteristics (TA = 25 OC unless otherwise noted ) Symbol Parameter Conditions Type N-Ch P-Ch N-Ch P-Ch N-Ch TJ = 55°C Min Typ Max Units OFF CHARACTERISTICS BVDSS Drain-Source Breakdown Voltage VGS = 0 V, ID = 250 µA VGS = 0 V, ID = -250 µA ID= 250 µA, Referenced to 25 oC ID = -250 µA, Referenced to 25 oC IDSS IDSS IGSS Zero Gate Voltage Drain Current VDS= 20 V, VGS= 0 V, VDS =-20 V, VGS = 0 V, TJ = 55°C Gate - Body Leakage Current VGS = 8 V, VDS= 0 V VGS = -8 V, VDS= 0 V ON CHARACTERISTICS (Note 2) N-Ch P-Ch 25 -25 25 -20 1 10 P-Ch -1 -10 100 -100 nA nA mV / oC µA µA mV /oC V ∆BVDSS/∆TJ Breakdown Voltage Temp. Coefficient Zero Gate Voltage Drain Current ∆VGS(th)/∆TJ VGS(th) RDS(ON) Gate Threshold Voltage Temp. Coefficient ID = 250 µA, Referenced to 25 o C ID= -250 µA, Referenced to 25 C o N-Ch P-Ch N-Ch P-Ch N-Ch 0.65 -0.65 -2.1 1.9 0.85 -1 3.8 6.3 3.1 1.5 -1.5 5 9 4 13 21 10 Gate Threshold Voltage VDS = VGS, ID= 250 µA VDS = VGS, ID= -250 µA VGS = 2.7 V, ID = 0.2 A TJ =125°C VGS = 4.5 V, ID = 0.4 A VGS = -2.7 V, ID = -0.05 A TJ =125°C VGS = -4.5 V, ID = -0.2 A V Static Drain-Source On-Resistance Ω P-Ch 10.6 15 7.9 ID(ON) gFS On-State Drain Current VGS = 2.7 V, VDS = 5 V VGS = -2.7 V, VDS = -5 V VDS = 5 V, ID= 0.4 A VDS = -5 V, ID= -0.2 A N-Ch P-Ch N-Ch P-Ch 0.2 -0.05 0.2 0.135 A Forward Transconductance S DYNAMIC CHARACTERISTICS Ciss Coss Crss Input Capacitance N-Channel VDS = 10 V, VGS = 0 V, f = 1.0 MHz P-Channel VDS = -10 V, VGS = 0 V, f = 1.0 MHz N-Ch P-Ch N-Ch P-Ch N-Ch P-Ch 9.5 11 6 7 1.3 1.4 pF pF pF Output Capacitance Reverse Transfer Capacitance FDC6320C.Rev C DMOS Electrical Characteristics (TA = 25 OC unless otherwise noted ) Symbol Parameter Conditions Type N-Ch P-Ch N-Ch P-Ch Min Typ Max Units SWITCHING CHARACTERISTICS (Note 2) tD(on) tr Turn - On Delay Time N-Channel VDD = 6 V, ID = 0.5 A, Turn - On Rise Time VGS = 4.5 V, RGEN = 50 Ω P-Channel VDD = -6 V, ID = -0.5 A, tf Turn - Off Fall Time VGEN= -4.5 V, RGEN = 50 Ω N-Channel VDS = 5 V, ID = 0.2 A, VGS = 4.5 V P-Channel VDS = -5 V, ID = -0.2A, VGS = -4.5 V 5 6 4.5 6 4 7.4 3.2 4 0.29 0.23 0.105 0.12 0.045 0.03 0.5 -0.5 0.97 -1 1.3 -1.3 V A nC 11 12 10 12 10 15 8 10 0.4 0.32 nC nC nS nS nS nS tD(off) Turn - Off Delay Time N-Ch P-Ch N-Ch P-Ch Qg Qgs Qgd Total Gate Charge N-Ch P-Ch N-Ch P-Ch N-Ch P-Ch Gate-Source Charge Gate-Drain Charge DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS IS VSD Notes: 1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RθJC is guaranteed by design while RθCA is determined by the user's board design. Typical RθJA using the board layouts shown below on FR-4 PCB in a still air environment: Maximum Continuous Drain-Source Diode Forward Current N-Ch P-Ch Drain-Source Diode Forward Voltage VGS = 0 V, IS = 0.5 A VGS = 0 V, IS = -0.5 A (Note 2) (Note 2) N-Ch P-Ch a. 140OC/W on a 0.125 in2 pad of 2oz copper. b. 180OC/W on a 0.005 in2 o f pad of 2oz copper. Scale 1 : 1 on letter size paper 2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%. FDC6320C.Rev C Typical Electrical Characteristics: N-Channel 0.5 0.4 3 .5 3.0 2.7 R DS(on) , NORMALIZED DRAIN-SOURCE ON-RESISTANCE V GS = 4.5V 1.4 4 .0 I D , DRAIN-SOURCE CURRENT (A) VGS = 2.0V 1.2 0.3 2 .5 2.5 1 2.7 3.0 3.5 0.2 2.0 0.1 0.8 4.0 4.5 1 .5 0 0 0.5 V DS 1 1.5 2 , DRAIN-SOURCE VOLTAGE (V) 2.5 3 0.6 0 0.1 0.2 0.3 0.4 0.5 I D , DRAIN CURRENT (A) Figure 1. On-Region Characteristics. Figure 2. On-Resistance Variation with Drain Current and Gate Voltage. 1.8 DRAIN-SOURCE ON-RESISTANCE R DS(ON), NORMALIZED 15 1.6 1.4 1.2 1 0.8 0.6 -50 I D = 0.2A VGS = 2.7 V R DS(on) , ON-RESISTANCE (OHM) I D = 0.2A 12 25°C 9 125°C 6 3 0 -25 0 25 50 75 100 T , JUNCTION TEMPERATURE (°C) J 125 150 2 2.5 3 3.5 4 V GS , GATE TO SOURCE VOLTAGE (V) Figure 3. On-Resistance Variation with Temperature. Figure 4. On Resistance Variation with Gate-To- Source Voltage. 0.2 0.5 V DS = 5.0V I S, REVERSE DRAIN CURRENT (A) T = -55°C J 25°C 125°C V GS = 0V 0.2 0.1 TJ = 125°C 25°C I D , DRAIN CURRENT (A) 0.15 0.01 0.1 - 55°C 0.05 0.001 0 0.5 1 1.5 2 V GS , GATE TO SOURCE VOLTAGE (V) 2.5 0.0001 0.2 0.4 0.6 0.8 1 V , BODY DIODE FORWARD VOLTAGE (V) SD 1.2 Figure 5. Transfer Characteristics. Figure 6. Body Diode Forward Voltage Variation with Source Current and Temperature. FDC6320C.Rev C Typical Electrical Characteristics: N-Channel (continued) 30 5 VGS , GATE-SOURCE VOLTAGE (V) 20 I D = 0.2A 4 VDS = 5.0V CAPACITANCE (pF) 10 C i ss C o ss 3 5 2 3 2 f = 1 MHz V GS = 0V C r ss 0.5 1 2 5 10 25 1 1 0.1 0 V , DRAIN TO SOURCE VOLTAGE (V) DS 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 Q g , GATE CHARGE (nC) Figure 7. Capacitance Characteristics. Figure 8. Gate Charge Characteristics. 0.8 0.5 ID , DRAIN CURRENT (A) IT IM )L ON S( RD 5 1m s 10 ms 4 POWER (W) 0.2 0.1 0.05 10 1s DC 0m SINGLE PULSE RθJA =See note 1b TA = 25°C s 3 2 0.02 0.01 0.5 V GS = 2.7V SINGLE PULSE RθJA =See note 1b TA = 25°C 1 V DS 1 2 5 10 20 40 0 0.01 0.1 1 10 100 300 , DRAI N-SOURCE VOLTAGE (V) SINGLE PULSE TIME (SEC) Figure 9. Maximum Safe Operating Area. Figure 10. Single Pulse Maximum Power Dissipation. FDC6320C.Rev C Typical Electrical Characteristics: P-Channel -I D , DRAIN-SOURCE CURRENT (A) V GS = -5.0V -4.5 0.15 -4.0 -3.5 RDS(ON), NORMALIZED DRAIN-SOURCE ON-RESISTANCE 0.2 2 -3.0 -2.7 V GS = -2.0 V 1.5 -2.5 -2.7 -3.0 0.1 -2.5 1 -4.0 -3.5 -4.5 0.05 -2.0 0 0.5 0 1 2 3 4 -VDS , DRAIN-SOURCE VOLTAGE (V) 0 0.05 0.1 -I D , DRAIN CURRENT (A) 0.15 0.2 Figure 11. On-Region Characteristics. Figure 12. On-Resistance Variation with Drain Current and Gate Voltage. 25 ,DRAIN-SOURCE ON-RESISTANCE 1.6 DRAIN-SOURCE ON-RESISTANCE I D = -0.05A 1.4 R DS(ON) , NORMALIZED V GS = -2.7V 20 TA= 25°C 125 °C ID = -0.05A 1.2 15 1 10 0.8 5 0.6 -50 R DS(ON) -25 0 25 50 75 100 TJ , JUNCTION TEMPERATURE (°C) 125 150 0 0 1 2 3 4 5 6 7 8 -V GS ,GATE TO SOURCE VOLTAGE (V) Figure 13. On-Resistance Variation with Temperature. Figure 14. On Resistance Variation with Gate-To- Source Voltage. -1 0.5 25°C I D , DRAIN CURRENT (A) -0.75 -I , REVERSE DRAIN CURRENT (A) V DS = -5V T = -55°C J VGS = 0V 0.1 TJ = 125°C 25°C 125°C -0.5 0.01 - 55°C -0.25 0 -0.5 -1 -1.5 -2 -2.5 V GS , GATE TO SOURCE VOLTAGE (V) -3 S 0.0001 0 0.2 0.4 0.6 0.8 1 -V SD , BODY DIODE FORWARD VOLTAGE (V) 1.2 Figure 15. Transfer Characteristics. Figure 16. Body Diode Forward Voltage Variation with Source Current and Temperature. FDC6320C.Rev C Typical Electrical Characteristics: P-Channel (continued) 8 -V GS , GATE-SOURCE VOLTAGE (V) 0.8 I D = -0.2A 6 VDS = -5V -15 -10 -ID , DRAIN CURRENT (A) 0.5 N) LIM IT 1m s 10 m s 0.2 R (O DS 10 0m s 4 0.1 0.05 1s DC 2 0.02 0 0 0.1 0.2 0.3 0.4 0.5 VGS = -2.7V SINGLE PULSE RθJA =See Note 1b TA = 25°C 1 2 -V DS 0.01 5 10 20 40 , DRAIN-SOURCE VOLTAGE (V) Q g , GATE CHARGE (nC) Figure 17. Gate Charge Characteristics. Figure 18. Maximum Safe Operating Area. 25 15 CAPACITANCE (pF) 10 5 C iss POWER (W) 4 Coss 5 3 2 3 SINGLE PULSE RθJA =See note 1b TA = 25°C 2 f = 1 MHz V GS = 0 V 0.3 1 2 5 1 Crss 10 15 25 0 0.01 0.1 1 10 100 300 1 0.1 -V DS , DRAIN TO SOURCE VOLTAGE (V) SINGLE PULSE TIME (SEC) Figure 19. Capacitance Characteristics. Figure 20. Single Pulse Maximum Power Dissipation. 1 r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE 0.5 D = 0.5 0.2 0.1 0.05 0.2 0.1 P(pk) 0.05 0.02 0.01 Single Pulse RθJA (t) = r(t) * R θJA R θJA = See Note 1b t1 t2 0.02 0.01 0.0001 TJ - TA = P * R JA(t) θ Duty Cycle, D = t 1/ t 2 0.01 0.1 t 1, TIME (sec) 1 10 100 300 0.001 Figure 21. Transient Thermal Response Curve. Note: Thermal characterization performed using the conditions described in note 1b.Transient thermal response will change depending on the circuit board design. FDC6320C.Rev C