FDM2452NZ

FDM2452NZ July 2005 FDM2452NZ Monolithic Common Drain N-Channel 2.5V Specified PowerTrench® MOSFET General Description This dual N-Channel MOSFET has been designed using Fairchild Semiconductor’s advanced Power Trench process to optimize the RDS(ON) @ VGS = 2.5v on special MicroFET lead frame with all the drains on one side of the package. Features • 8.1 A, 30 V RDS(ON) = 21 mΩ @ VGS = 4.5 V RDS(ON) = 25 mΩ @ VGS = 2.5 V • ESD protection Diode(note 3) • Low Profile – 0.8 mm maximum – in the new package MicroFET 2 x 5 mm Applications • Li-Ion Battery Pack PIN 1 S1 S1 G1 G2 Bottom Drain Contact 4 Q2 3 G1 S2 5 6 2 1 S1 S2 S2 S2 G2 Q1 Bottom Drain Contact S1 MLP 2x5 Absolute Maximum Ratings Symbol VDSS VGSS ID PD TJ, TSTG TA=25oC unless otherwise noted Parameter Drain-Source Voltage Gate-Source Voltage Drain Current – Continuous – Pulsed Power Dissipation (Steady State) Ratings 30 ±12 8.1 30 2.2 0.8 –55 to +150 Units V V A W °C (Note 1a) (Note 1a) (Note 1b) Operating and Storage Junction Temperature Range Thermal Characteristics RθJA RθJA Thermal Resistance, Junction-to-Ambient Thermal Resistance, Junction-to-Ambient (Note 1a) (Note 1b) 55 145 °C/W Package Marking and Ordering Information Device Marking 2452Z Device FDM2452NZ Reel Size 13’’ Tape width 12mm Quantity 3000 units ©2005 Fairchild Semiconductor Corporation FDM2452NZ Rev C1 FDM2452NZ Electrical Characteristics Symbol BVDSS ∆BVDSS ∆TJ IDSS IGSS VGS(th) ∆VGS(th) ∆TJ RDS(on) TA = 25°C unless otherwise noted Parameter Drain–Source Breakdown Voltage Breakdown Voltage Temperature Coefficient Zero Gate Voltage Drain Current Gate–Body Leakage, (Note 2) Test Conditions VGS = 0 V, ID = 250 µA Min 30 Typ Max Units V Off Characteristics ID = 250 µA, Referenced to 25°C VDS = 24 V, VGS = ±12 V, VGS = 0 V VDS = 0 V 0.55 0.8 –3 13.6 13.9 14.6 15.7 19 46 24 1 ±10 1.5 mV/°C µA µA V mV/°C mΩ On Characteristics Gate Threshold Voltage Gate Threshold Voltage Temperature Coefficient Static Drain–Source On–Resistance ID = 250 µA VDS = VGS, ID = 250 µA, Referenced to 25 C VGS = 4.5 V, ID = 8.1 A ID = 8.0 A VGS = 4.0 V, ID = 7.7 A VGS = 3.1 V, ID = 7.4 A VGS = 2.5 V, VGS = 4.5 V, ID = 8.1 A, TJ=125°C VDS = 5 V, ID =8.1 A 21 21.5 23 25 31 gFS Ciss Coss Crss RG Forward Transconductance S Dynamic Characteristics Input Capacitance Output Capacitance Reverse Transfer Capacitance Gate Resistance (Note 2) VDS = 15 V, f = 1.0 MHz V G S = 0 V, V G S = 0 V, 980 160 110 1.8 pF pF pF Ω f = 1.0 MHz Switching Characteristics td(on) tr td(off) tf Qg Qgs Qgd VSD trr Qrr Turn–On Delay Time Turn–On Rise Time Turn–Off Delay Time Turn–Off Fall Time Total Gate Charge Gate–Source Charge Gate–Drain Charge VDD = 15 V, VGS = 4.5 V, ID = 1 A, RGEN = 6 Ω 9 10 30 8.7 18 20 48 17 19 ns ns ns ns nC nC nC VDS = 15 V, VGS = 4.5 V ID = 8.1 A, 14 1.8 3.8 Drain–Source Diode Characteristics Drain–Source Diode Forward Voltage Diode Reverse Recovery Time Diode Reverse Recovery Charge VGS = 0 V, IS = 1.8 A (Note 2) 0.7 15 4 1.2 V nS nC IF = 8.1 A, dIF/dt = 100 A/µs Notes: 1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RθJC is guaranteed by design while RθCA is determined by the user's board design. a) 55°C/W when mounted on a 1in2 pad of 2 oz copper b) 145°C/W when mounted on a minimum pad of 2 oz copper Scale 1 : 1 on letter size paper 2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0% 3. The diode connected between the gate and source serves only as protection againts ESD. No gate overvoltage rating is implied. FDM2452NZ Rev C1 FDM2452NZ Typical Characteristics 40 35 ID, DRAIN CURRENT (A) 3.5V 2.0V RDS(ON), NORMALIZED DRAIN-SOURCE ON-RESISTANCE VGS = 4.5V 2.5V 1.5 1.4 VGS = 2.0V 1.3 1.2 1.1 1 0.9 30 3.0V 25 20 15 10 1.5V 2.5V 3.0V 3.5V 4.0V 4.5V 5 0 0 0.5 1 1.5 2 2.5 VDS, DRAIN-SOURCE VOLTAGE (V) 0 5 10 15 20 25 30 35 40 ID, DRAIN CURRENT (A) Figure 1. On-Region Characteristics. Figure 2. On-Resistance Variation with Drain Current and Gate Voltage. 0.04 RDS(ON), ON-RESISTANCE (OHM) 1.6 RDS(ON), NORMALIZED DRAIN-SOURCE ON-RESISTANCE ID = 8.1A VGS = 4.5V 1.4 ID = 4.0A 0.035 0.03 TA = 125oC 1.2 0.025 0.02 0.015 0.01 1 0.8 TA = 25oC 0.6 -50 -25 0 25 50 75 100 o 125 150 1 2 3 4 5 TJ, JUNCTION TEMPERATURE ( C) VGS, GATE TO SOURCE VOLTAGE (V) Figure 3. On-Resistance Variation with Temperature. 40 35 ID, DRAIN CURRENT (A) 30 125oC 25 20 15 10 5 0 0.5 1 1.5 2 2.5 VGS, GATE TO SOURCE VOLTAGE (V) IS, REVERSE DRAIN CURRENT (A) Figure 4. On-Resistance Variation with Gate-to-Source Voltage. 100 VDS = 5V TA = -55oC 25oC VGS = 0V 10 TA = 125oC 1 25oC 0.1 -55oC 0.01 0.001 0.0001 0 0.2 0.4 0.6 0.8 1 1.2 VSD, BODY DIODE FORWARD VOLTAGE (V) Figure 5. Transfer Characteristics. Figure 6. Body Diode Forward Voltage Variation with Source Current and Temperature. FDM2452NZ Rev C1 FDM2452NZ Typical Characteristics 5 VGS, GATE-SOURCE VOLTAGE (V) ID = 8.1A 4 20V 3 CAPACITANCE (pF) 1600 VDS = 10V 15V 1400 1200 f = 1MHz VGS = 0 V Ciss 1000 800 600 400 200 2 1 Coss Crss 0 0 4 8 Qg, GATE CHARGE (nC) 12 16 0 0 5 10 15 20 25 30 VDS, DRAIN TO SOURCE VOLTAGE (V) Figure 7. Gate Charge Characteristics. 100 P(pk), PEAK TRANSIENT POWER (W) RDS(ON) LIMIT ID, DRAIN CURRENT (A) 100us 10 1ms 10ms 100ms 1s 10s DC 0.1 VGS = 4.5V SINGLE PULSE RθJA = 145oC/W TA = 25oC 0.01 0.1 1 10 100 VDS, DRAIN-SOURCE VOLTAGE (V) 50 Figure 8. Capacitance Characteristics. 40 SINGLE PULSE RθJA = 145°C/W TA = 25°C 30 1 20 10 0 0.001 0.01 0.1 1 t1, TIME (sec) 10 100 1000 Figure 9. Maximum Safe Operating Area. Figure 10. Single Pulse Maximum Power Dissipation. r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE 1 D = 0.5 RθJA(t) = r(t) * RθJA RθJA =145 °C/W P(pk) t1 t2 TJ - TA = P * RθJA(t) Duty Cycle, D = t1 / t2 SINGLE PULSE 0.2 0.1 0.1 0.05 0.02 0.01 0.01 0.0001 0.001 0.01 0.1 t1, TIME (sec) 1 10 100 1000 Figure 11. Transient Thermal Response Curve. Thermal characterization performed using the conditions described in Note 1b. Transient thermal response will change depending on the circuit board design. FDM2452NZ Rev C1 FDM2452NZ Dimensional Outline and Pad Layout FDM2452NZ Rev C1 TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. 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PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Advance Information Product Status Formative or In Design Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Preliminary First Production No Identification Needed Full Production Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Rev. I16