FSB50250UTD

FSB50250UTD Smart Power Module (SPM®) April 2010 FSB50250UTD Smart Power Module (SPM®) Features • 500V RDS(on)=4.2W( max) 3-phase FRFET inverter including high voltage integrated circuit (HVIC) • 3 divided negative dc-link terminals for inverter current sensing applications • HVIC for gate driving and undervoltage protection • 3/5V CMOS/TTL compatible, active-high interface • Optimized for low electromagnetic interference • Isolation voltage rating of 1500Vrms for 1min. • Embedded bootstrap diode in the package Motion-SPM General Description TM FSB50250UTD is a tiny smart power module (SPM®) based on FRFET technology as a compact inverter solution for small power motor drive applications such as fan motors and water suppliers. It is composed of 6 fast-recovery MOSFET (FRFET), and 3 half-bridge HVICs for FRFET gate driving. FSB50250UTD provides low electromagnetic interference (EMI) characteristics with optimized switching speed. Moreover, since it employs FRFET as a power switch, it has much better ruggedness and larger safe operation area (SOA) than that of an IGBT-based power module or one-chip solution. The package is optimized for the thermal performance and compactness for the use in the built-in motor application and any other application where the assembly space is concerned. FSB50250UTD is the most solution for the compact inverter providing the energy efficiency, compactness, and low electromagnetic interference. Absolute Maximum Ratings Symbol VPN ID25 ID80 IDP PD V CC VBS V IN TJ TSTG R qJC VISO Parameter DC Link Input Voltage, Drain-source Voltage of each FRFET Each FRFET Drain Current, Continuous Each FRFET Drain Current, Continuous Each FRFET Drain Current, Peak Maximum Power Dissipation Control Supply Voltage High-side Bias Voltage Input Signal Voltage Operating Junction Temperature Storage Temperature Junction to Case Thermal Resistance Isolation Voltage TC = 25°C TC = 80°C Conditions Rating 500 1.1 0.8 2.8 13 20 20 -0.3 ~ VCC+0.3 -40 ~ 150 -40 ~ 125 Units V A A A W V V V °C °C °C/W Vrms TC = 25°C, PW < 100ms TC = 25°C, Each FRFET Applied between V CC and COM Applied between V B(U)-U, VB(V)-V, VB(W)-W Applied between IN and COM Each FRFET under inverter operating condition (Note 1) 60Hz, Sinusoidal, 1 minute, Connection pins to heatsink 9.3 1500 ©2010 Fairchild Semiconductor Corporation 1 www.fairchildsemi.com FSB50250UTD Rev. A FSB50250UTD Smart Power Module (SPM®) Pin Descriptions Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Pin Name COM VB(U) V CC(U) IN(UH) IN(UL) NC V B(V) VCC(V) IN (VH) IN (VL) NC VB(W) V CC(W) IN(WH) IN(WL) NC P U, VS(U) NU NV V, VS(V) NW W, VS(W) IC Common Supply Ground Pin Description Bias Voltage for U Phase High Side FRFET Driving Bias Voltage for U Phase IC and Low Side FRFET Driving Signal Input for U Phase High-side Signal Input for U Phase Low-side No Connection Bias Voltage for V Phase High Side FRFET Driving Bias Voltage for V Phase IC and Low Side FRFET Driving Signal Input for V Phase High-side Signal Input for V Phase Low-side No Connection Bias Voltage for W Phase High Side FRFET Driving Bias Voltage for W Phase IC and Low Side FRFET Driving Signal Input for W Phase High-side Signal Input for W Phase Low-side No Connection Positive DC–Link Input Output for U Phase & Bias Voltage Ground for High Side FRFET Driving Negative DC–Link Input for U Phase Negative DC–Link Input for V Phase Output for V Phase & Bias Voltage Ground for High Side FRFET Driving Negative DC–Link Input for W Phase Output for W Phase & Bias Voltage Ground for High Side FRFET Driving (1) COM (2) VB(U) (3) VCC(U) (4) IN(UH) (5) IN(UL) (6) NC (7) VB(V) (8) VCC(V) (9) IN(VH) (10) IN(VL) (11) NC (12) VB(W) (13) VCC(W) (14) IN(WH) (15) IN(WL) (16) NC Note: Source terminal of each low-side MOSFET is not connected to supply ground or bias voltage ground inside SPM®. External connections should be made as indicated in Figure 2 and 5. (17) P VCC HIN LIN COM VB HO VS LO (19) NU VCC HIN LIN COM VB HO VS LO (21) V,Vs(v) (20) NV (18) U,Vs(u) VCC HIN LIN COM VB HO VS LO (22) NW (23) W,Vs(w) Figure 1. Pin Configuration and Internal Block Diagram (Bottom View) FSB50250UTD Rev. A 2 www.fairchildsemi.com FSB50250UTD Smart Power Module (SPM®) Electrical Characteristics (TJ = 25°C, VCC=VBS=15V Unless Otherwise Specified) Inverter Part (Each FRFET Unless Otherwise Specified) Symbol BV DSS DBVDSS/ DTJ IDSS RDS(on) VSD tON tOFF trr EON EOFF RBSOA (Note 3) V = 400V, VCC = VBS = 15V, ID = IDP, V DS=BVDSS, Reverse-bias Safe Oper- PN TJ = 150°C ating Area High- and low-side FRFET switching (Note 4) Switching Times Parameter Conditions Min 500 - Typ 0.53 3.5 1050 850 170 40 10 Max Units 250 4.2 1.2 V V mA W V ns ns ns mJ mJ Drain-Source Breakdown V IN= 0V, ID = 250m A (Note 2) Voltage Breakdown Voltage TemID = 250mA, Referenced to 25°C perature Coefficient Zero Gate Voltage Drain Current Static Drain-Source On-Resistance Drain-Source Diode Forward Voltage V IN= 0V, VDS = 500V V CC = VBS = 15V, V IN = 5V, ID = 0.5A V CC = VBS = 15V, V IN = 0V, ID = -0.5A V PN = 300V, VCC = VBS = 15V, ID = 0.5A V IN = 0V « 5V Inductive load L=3mH High- and low-side FRFET switching Full Square Control Part (Each HVIC Unless Otherwise Specified) Symbol IQCC IQBS UVCCD UVCCR UVBSD UVBSR V IH V IL IIH IIL Parameter Quiescent VCC Current Quiescent VBS Current Low-side Undervoltage Protection (Figure 7) High-side Undervoltage Protection (Figure 8) ON Threshold Voltage OFF Threshold Voltage Input Bias Current V CC=15V, V IN=0V V BS=15V, V IN=0V Conditions Applied between VCC and COM Applied between VB(U)-U, V B(V)-V, VB(W)-W Min Typ Max Units 7.4 8.0 7.4 8.0 2.9 8.0 8.9 8.0 8.9 10 160 100 9.4 9.8 9.4 9.8 0.8 20 2 mA mA V V V V V V mA mA V CC Undervoltage Protection Detection Level V CC Undervoltage Protection Reset Level V BS Undervoltage Protection Detection Level V BS Undervoltage Protection Reset Level Logic High Level Logic Low Level V IN = 5V V IN = 0V Applied between IN and COM Applied between IN and COM Bootstrap Diode Part Symbol VRRM IF IFP TJ Note: 1. For the measurement point of case temperature T C, please refer to Figure 4 in page 5. 2. BVDSS is the absolute maximum voltage rating between drain and source terminal of each FRFET inside SPM®. VPN should be sufficiently less than this value considering the effect of the stray inductance so that VDS should not exceed BVDSS in any case. 3. tON and tOFF include the propagation delay time of the internal drive IC. Listed values are measured at the laboratory test condition, and they can be different according to the field applcations due to the effect of different printed circuit boards and wirings. Please see Figure 5 for the switching time definition with the switching test circuit of Figure 6. 4. The peak current and voltage of each FRFET during the switching operation should be included in the safe operating area (SOA). Please see Figure 6 for the RBSOA test circuit that is same as the switching test circuit. Parameter Maixmum Repetitive Reverse Voltage Forward Current Forward Current (Peak) Operating Junction Temperature TC = 25°C Conditions Rating 500 0.5 2 -40 ~ 150 Units V A A °C TC = 25°C, Under 1ms Pulse Width FSB50250UTD Rev. A 3 www.fairchildsemi.com FSB50250UTD Smart Power Module (SPM®) Bootstrap Diode Part Symbol VF trr Parameter Forward Voltage Reverse Recovery Time Conditions IF = 0.1A, TC = 25°C IF = 0.1A, TC = 25°C Min. - Typ. 2.0 80 Max. - Units V ns 1.0 0.9 0.8 0.7 0.6 Built in Bootstrap Diode VF-IF Characteristic IF [A ] 0.5 0.4 0.3 0.2 0.1 0.0 TC=25℃ 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 VF [V] Note: Built in bootstrap diode includes around 15 Ω resistance characteristic. Figure 2. Built in Bootstrap Diode Characteristics Package Marking & Ordering Information Device Marking FSB50250UTD Device FSB50250UTD Package SPM23-ED Reel Size _ Packing Type _ Quantity 15 FSB50250UTD Rev. A 4 www.fairchildsemi.com FSB50250UTD Smart Power Module (SPM®) Recommended Operating Conditions Symbol V PN VCC VBS VIN(ON) VIN(OFF) tdead fPWM Parameter Supply Voltage Control Supply Voltage High-side Bias Voltage Input ON Threshold Voltage Input OFF Threshold Voltage Conditions Applied between P and N Applied between V CC and COM Applied between V B and output(U, V, W) Applied between IN and COM Value Min. 13.5 13.5 3.0 0 1.0 - Typ. 300 15 15 15 Max. 400 16.5 16.5 V CC 0.6 - Units V V V V V ms kHz Blanking Time for Preventing VCC =VBS=13.5 ~ 16.5V, TJ £ 150°C Arm-short PWM Switching Frequency TJ £ 150°C These values depend on PWM control algorithm 15-V Line C1 P VCC HIN LIN C5 COM VB HO VS LO N 10mF C2 One-Leg Diagram of SPM * Example of bootstrap paramters: C1 = C2 = 1mF ceramic capacitor, R3 VDC HIN 0 LIN 0 1 0 1 Open Output Z 0 VDC Forbidden Z Note Both FRFET Off Low-side FRFET On High-side FRFET On Shoot-through Same as (0, 0) R5 Micom Inverter Output C3 0 1 1 Open Note: (1) It is recommended the bootstrap diode D1 to have soft and fast recovery characteristics with 500-V rating (2) Parameters for bootsrap circuit elements are dependent on PWM algorithm. For 15 kHz of switching frequency, typical example of parameters is shown above. (3) RC coupling(R5 and C5) at each input (indicated as dotted lines) may be used to prevent improper input signal due to surge noise. Signal input of SPM®is compatible with standard CMOS or LSTTL outptus. (4) Bold lines should be short and thick in PCB pattern to have small stray inductance of circuit, which results in the reduction of surge voltage. Bypass capacitors such as C1, C2 and C3 should have good high-frequency characteristics to absorb high-frequency ripple current. Figure 3. Recommended CPU Interface and Bootstrap Circuit with Parameters 14.50mm 3.80mm MOSFET Note: Case Temperature(Tc) Detecting Point Attach the thermocouple on top of the heatsink-side of SPM® (between SPM® and heatsink if applied) to get the correct temperature measurement. Figure 4. Case Temperature Measurement FSB50250UTD Rev. A 5 www.fairchildsemi.com FSB50250UTD Smart Power Module (SPM®) VIN Irr VDS 100% of ID 120% of ID VIN ID 10% of ID ID VDS tON trr tOFF (a) Turn-on Figure 5. Switching Time Definition CBS (b) Turn-off VCC ID VCC HIN LIN COM VB HO VS LO + VDS - L VDC One-leg Diagram of SPM Figure 6. Switching and RBSOA(Single-pulse) Test Circuit (Low-side) Input Signal UV Protection Status RESET DETECTION RESET Low-side Supply, VCC UVCCR UVCCD MOSFET Current Figure 7. Undervoltage Protection (Low-side) Input Signal UV Protection Status RESET DETECTION RESET High-side Supply, VBS UVBSR UVBSD MOSFET Current Figure 8. Undervoltage Protection (High-side) FSB50250UTD Rev. A 6 www.fairchildsemi.com FSB50250UTD Smart Power Module (SPM®) C1 (1) COM (2) VB(U) (3) VCC(U) R5 (4) IN (UH) (5) IN (UL) C5 C2 (6) NC (7) VB(V) (8) VCC(V) (9) IN (VH) VCC HIN LIN COM VB HO VS LO VCC HIN LIN COM VB HO VS LO (19) N U (20) N V (21) V,Vs(v) (18) U,Vs(u) C3 VDC (17) P Micom (10) IN(VL) C2 (11) NC (12) VB(W) (13) VCC(W) (14) IN(WH) (15) IN(WL) C2 (16) NC M VCC HIN LIN COM VB HO VS LO (22) N W (23) W,Vs(w) For 3-phase current sensing and protection 15-V Supply R4 C4 R3 Figure 9. Example of Application Circuit FSB50250UTD Rev. A 7 www.fairchildsemi.com FSB50250UTD Smart Power Module (SPM®) Detailed Package Outline Drawings Max 1.00 0.60±0.10 (1.165) 15*1.778=26.67±0.30 13.34±0.30 13.34±0.30 (1.80) (1.00) #1 #16 R0 .4 0 0 .4 R0 19. 00 12 .00±0.20 12.23±0.30 29.00±0.20 2x3.90=7.80±0.30 (2.275) 13.13±0.30 3.10±0.20 6.20±0.20 4x3.90=15.60±0.30 1.95±0.30 (1.80) (1.30) 0.60±0.10 Max 1.00 FSB50250UTD Rev. A 8 0.5 0+0.10 -0 .0 5 #17 #23 5° 3° 14.58±0.30 www.fairchildsemi.com 1 9.58±0.30 14.00 FSB50250UTD Smart Power Module (SPM®) Rev. I15 9 FSB50250UTD Rev. A www.fairchildsemi.com