FUSB1501

FUSB1500 / FUSB1501 — USB2.0 Full-Speed / Low-Speed Transceiver with Charger Detection October 2009 FUSB1500 / FUSB1501 — USB2.0 Full-Speed / Low-Speed Transceiver with Charger Detection Features Complies with USB2.0 Specification Supports 12Mbps and 1.5Mbps USB2.0 Speeds FUSB1501: Differential Mode Signaling FUSB1500: Single Ended (SE) Mode Signaling Slew-Rate Controlled Differential Data Driver Differential Input Receiver with Wide CommonMode Range and High Input Sensitivity Stable RCV Output during SE0 Condition Two Single-Ended Receivers with Hysteresis Supports I/O Voltage: 1.65V to 3.6V Description The FUSB1500/1501 is a USB2.0 FS/LS transceiver with resistive charger detection. It is compliant with the Universal Serial Bus Specification, Rev. 2.0 (USB2.0). Ideal for portable electronic devices; such as mobile phones, digital still cameras, and personal digital assistants; it allows USB Application Specific ICs (ASICs) and Programmable Logic Devices (PLDs) with power supply voltages from 1.65V to 3.6V to interface with the physical layer of the Universal Serial Bus. The FUSB1500/1501 can be used as a USB device transceiver or a USB host transceiver. It can transmit and receive serial data at both full-speed (12Mbps) and low-speed (1.5Mbps) data rates. The FUSB1500 supports the SE Mode controller interface and the FUSB1501 supports the differential mode controller interface. Applications Dual-Camera Applications for Cell Phones Dual-LCD Applications for Cell Phones, Digital Camera Displays, and Viewfinders IMPORTANT NOTE: For additional performance information, please contact analogswitch@fairchildsemi.com. Ordering Information Part Number FUSB1500MHX FUSB1501MHX (Preliminary) Operating Temperature Range -40 to +85°C -40 to +85°C Top Mark FUSB 1500 FUSB 1501 Eco Status Green Green Package 16-Pin, Molded Leadless Package (MLP), JEDEC MO217 Equivalent, 3mm Square 16-Pin, Molded Leadless Package (MLP), JEDEC MO217 Equivalent, 3mm Square Packing Method Tape and Reel Tape and Reel For Fairchild’s definition of Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html. © 2008 Fairchild Semiconductor Corporation FUSB1500 / FUSB1501 • Rev. 1.0.0 www.fairchildsemi.com FUSB1500 / FUSB1501 — USB2.0 Full-Speed / Low-Speed Transceiver with Charger Detection Block Diagram + + VIO INT_N SUSPEND SPEED_N CONFIG Auto Connect & Charger Detection Control CONFIG_INT Level Translators & Control Logic VREF + + VREG3V3 Vpu3V3 150k OE_N 1.5k (FS connection) VO/VPO FSE0/VMO 33 D+ D- 33 HiZ & Pull Downs + RCV + - VP VM HIZ RHIZ GND Figure 1. Functional Block Diagram © 2008 Fairchild Semiconductor Corporation FUSB1500 / FUSB1501 • Rev. 1.0.0 www.fairchildsemi.com 2 FUSB1500 / FUSB1501 — USB2.0 Full-Speed / Low-Speed Transceiver with Charger Detection Pin Configuration Figure 2. Pin Configuration (Top-Through View) Pin Definitions Pin # 1 Name I/O Description 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Exposed Die Pad Output enable. Active LOW enables the transceiver to transmit data on the bus. When OE_N I not active, the transceiver is in the receive mode (CMOS level is relative to VIO). Receive data output. Non-inverted CMOS level output for USB differential input (CMOS output level is relative to VIO). Driven LOW when SUSPND mode is active; RCV O (SUSPND is only enabled per the specific extended control table – see Table 4); RCV output is stable and preserved during SE0 condition. Single-ended D+ receiver output VP (CMOS level relative to VIO); used for external detection of SE0, error conditions, speed of connected device; driven HIGH when no VP O supply connected to VREG3V3. Single-ended D- receiver output VM (CMOS level relative to VIO); used for external detection of SE0, error conditions, speed of connected device; driven HIGH when no VM O supply is connected to VREG3V3. Suspend. Enables a low-power state (CMOS level is relative to VIO). While the FUSB1500/1501 is suspended, it drives the RCV pin to logic “0” state. (Suspend is SUSPND I only enabled per the specific extended control table – see Table 4). High-Z input (CMOS level is relative to VIO). HIGH selects the high-Z mode, which puts HiZ I all the outputs, including VPU, in high impedance. There is a 100kΩ weak pull-down on this pin. Supply voltage for digital I/O pins (1.65V to 3.6V). When not connected, the D+ and DVIO pins are in three-state. This supply bus is independent of VPU and VREG3V3. Speed selection input (CMOS level relative to VIO); adjusts the slew rate of differential SPEED_N I outputs D+ and D- according to the extended control table (see Table 4). DAI/O Data- bus connection. D+ AI/O Data+ bus connection; for FS peripheral mode, connect to VPU via 1.5kΩ. Driver data input (CMOS level is relative to VIO); Schmitt-trigger input; VO is input pin for SE Mode (FUSB1500); VPO is input for Differential Mode (FUSB1501), see Table 2 VO/VPO I and Table 3. Driver data input (CMOS level is relative to VIO); Schmitt-trigger input; FSE0 is input pin for SE Mode (FUSB1500); VMO is input for Differential Mode (FUSB1501), see FSE0/VMO I Table 2 and Table 3. VREG3V3 Supply voltage input for 3.3V operation. This interrupt is active LOW. It is asserted when an SE0 is seen on the USB bus (SE0 INT_N O detection circuit is only enabled per the specific extended control table). It is also referenced to VIO. Pull-up supply voltage (3.3V±300mV); connect an external 1.5kΩ resistor on D+ VPU (FS data rate) or D- (LS data rate). Internal switch is controlled by the CONFIG, SPEED_N, and SUSPND input pins (see Table 4). USB connect or disconnect, software-control input. SPEED_N and SUSPND also gate CONFIG I the pull-up resistor (see Table 4). GND GND GND supply bonded to exposed die pad to be connected to the PCB GND. © 2008 Fairchild Semiconductor Corporation FUSB1500 / FUSB1501 • Rev. 1.0.0 www.fairchildsemi.com 3 FUSB1500 / FUSB1501 — USB2.0 Full-Speed / Low-Speed Transceiver with Charger Detection Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol VIO VPU, VREG3V3 ILU IIK VIN IOK VOUT Parameter I/O Supply Voltage Regulated Supply Voltage and Pull-up Supply Latch-up Current DC Input Current DC Input Voltage (1) Test Conditions Min. -0.5 -0.5 Max. 4.6 4.6 150 -50 Units V V mA mA V mA V VIN = -1.8 to +5.4V VIN < 0 -0.5 VOUT > VREG3V3 or < 0 -0.5 VOUT = 0 to VREG3V3 VOUT = 0 to VREG3V3 VIO +0.5 ±50 VIO +0.5 ±50 DC Output Diode Current DC Output Voltage (1) IOUT DC Output Source or Sink Current for D+, Dpins DC Output Source or Sink Current for RCV, VM/VP DC VVREG3V3 or GND Current mA ±15 ±100 Pins D+, D-, ILI < 3μA -10500 -12000 -6500 +10500 +12000 +6500 V 200 +1500 Air Gap Contact -40 ICC(VREG3V3) ICCIO +15000 +8000 +125 48 9 °C mW mA IVREG3V3, IGND Human Body Model, JEDEC: JESD22-A114 VREG3V3, VIO, and GND; ILI < 3μA; All Other Pins, ILI < 1μA ESD Machine Model, JESD22-A115 Charged Device Model, JEDEC: JESD-C101 IEC 61000-4-2 TSTG PD Storage Temperature Range Power Dissipation Note: 1. Absolute maximum ratings for I/O must be observed. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Symbol VREG3V3 VIO VIN VAI/O TA Parameter DC Supply Voltage I/O DC Voltage DC Input Voltage Range DC Input Range for AI/Os Operating Ambient Temperature Test Conditions Min. 3.0 1.65 0 Max. 3.6 3.6 VIO 3.6 +85 Units V V V V °C Pins D+ and D- 0 -40 © 2008 Fairchild Semiconductor Corporation FUSB1500 / FUSB1501 • Rev. 1.0.0 www.fairchildsemi.com 4 FUSB1500 / FUSB1501 — USB2.0 Full-Speed / Low-Speed Transceiver with Charger Detection Electrical Characteristics — Supply Pins DC Characteristics Unless otherwise noted, values are over the recommended range of supply voltage and operating free air temperature. VREG3V3 = 3.0V to 3.6V and VIO = 1.65V to 3.6V. Symbol VREG3V3 IVREG3V3 ICCIO IIDLE ICCIO(STATIC) ISUSPND Parameter Regulated Supply Input (2,3) Test Conditions TA=-40°C to 85°C Min. 3.0 Units V mA mA μA μA μA μA μA μA V mV Typ. 3.3 4 1 Max. 3.6 8 2 500 20 25 Operating Supply Current (4) (VREG3V3) I/O Operating Supply Current (4) Transmitting and Receiving at 12Mbps; CLOAD = 50pF(D+, D-) Transmitting and Receiving at 12Mbps Supply Current During FS Idle and IDLE: VD+ ≥ 3.0V, VD- ≤ 0.3V; (5) SE0 (VREG3V3) SE0: VD+ ≤ 0.3V, VD- ≤ 0.3V I/O Static Supply Current Suspend (VREG3V3) Supply (5) Current Disable-Mode (VREG3V3) Supply (5) Current I/O Sharing-Mode Supply Current Sharing-Mode Load Current on D+/D- Pins VIO Threshold-Detection Voltage VIO Threshold-Detection (4) Hysteresis Voltage IDLE, SUSPND, or SE0 SUSPND = H; OE_N = H or L; D+ = D- = Not Floating; VM = VP = Open VIO Not Connected, D+ = D- = Not Floating VREG3V3 Not Connected VREG3V3 Not Connected, CONFIG = LOW, VD± = 3.6V Supply Lost Supply Present VREG3V3 = 3.3V 1.4 450 IDISABLE ISHARING ID± (SHARING) VREF VIO_hys 25 20 10 0.5 Notes: 2. ILOAD includes the pull-up resistor current via the VPU pin. 3. The minimum voltage in Suspend Mode is 2.7V. 4. Not tested in production; value based on characterization. 5. Excludes any current from load and VPU or VSW current to the 1.5kΩ and 15kΩ pull-up / pull-down resistors (200μA typical). © 2008 Fairchild Semiconductor Corporation FUSB1500 / FUSB1501 • Rev. 1.0.0 www.fairchildsemi.com 5 FUSB1500 / FUSB1501 — USB2.0 Full-Speed / Low-Speed Transceiver with Charger Detection Electrical Characteristics — Digital Pins DC Characteristics Excludes D+ and D- pins. Unless otherwise noted, values are over the recommended range of supply voltage and operating free air temperature. VREG3V3 = 3.0V to 3.6V and VIO = 1.65V to 3.6V. Symbol Input Levels VIL VIH Parameter Test Conditions TA=-40°C to 85°C Min. Max. Units LOW-Level Input Voltage HIGH-Level Input Voltage 0.6 • VIO 0.3 V V Output Levels VOL LOW-Level Output Voltage IOL = 2.0mA IOL = 100μA IOH = 2.0mA IOH = 100μA VIO - 0.4 VIO - 0.15 0.4 V 0.15 V VOH HIGH-Level Output Voltage Leakage Current ILI Input Leakage Current, Excluding HIZ VIO = 1.65 to 3.60V -1 +1 μA Capacitance CIN, CI/O Input Capacitance (6) Pin to GND 10 pF Resistance RHIZ RCHRGPU Pull-Down Resistance on HIZ Input Pin Pull-Up Resistance for CHRGR Function 100 105 171 kΩ kΩ Note: 6. Not tested in production; value based on characterization. © 2008 Fairchild Semiconductor Corporation FUSB1500 / FUSB1501 • Rev. 1.0.0 www.fairchildsemi.com 6 FUSB1500 / FUSB1501 — USB2.0 Full-Speed / Low-Speed Transceiver with Charger Detection Electrical Characteristics — Analog I/O Pins DC Characteristics Unless otherwise noted, values are over the recommended range of supply voltage and operating free air temperature. VREG3V3 = 3.0V to 3.6V and VIO = 1.65V to 3.6V. Symbol Parameter Test Conditions TA=-40°C to 85°C Min. Max. Units Input Levels – Differential Receiver VDI VCM Differential Input Sensitivity Differential Common Mode Voltage ⏐ VIN(D+) - VIN(D-) ⏐ 0.2 0.8 2.5 V V Input Levels – Single-Ended Receiver VIL VIH VHYS LOW-Level Input Voltage HIGH-Level Input Voltage Hysteresis Voltage (7) 0.8 2.0 0.4 0.7 V V V Output Levels VOL VOH LOW-Level Output Voltage HIGH-Level Output Voltage (8) RL = 1.5kΩ to 3.6V RL = 15kΩ to GND 2.8 0.3 3.6 V V Leakage Current IOFF Input Leakage Current – Off State -1 +1 µA Capacitance CI/O I/O Capacitance (7) Pin to GND 20 pF Resistance ZDRV ZIN RSW VTERM Driver Output Impedance Driver Input Impedance Switch Resistance Termination Voltage (10,11) (9) Steady State 34 10 44 Ω MΩ ISW = 0 to 10mA RPU - Upstream Port 3.0 15 3.6 Ω V Notes: 7. Not tested in production; value based on characterization. 8. VOH minimum = VREG3V3 – 0.2V. 9. Includes external 33Ω ± 1% on both D+ and D- pins to comply with USB2.0. 10. This voltage is available at the VPU and VREG3V3 pins. 11. Minimum voltage is 2.7V in Suspend Mode. © 2008 Fairchild Semiconductor Corporation FUSB1500 / FUSB1501 • Rev. 1.0.0 www.fairchildsemi.com 7 FUSB1500 / FUSB1501 — USB2.0 Full-Speed / Low-Speed Transceiver with Charger Detection Electrical Characteristics — AI/O Pins AC Characteristics, Full Speed Unless otherwise noted, values are over the recommended range of supply voltage and operating free air temperature. VREG3V3 = 3.0V to 3.6V and VIO= 1.65V to 3.6V. Symbol Parameter Test Conditions TA=-40°C to 85°C Min. Typ. (13) Units Max. Driver Characteristics, FS Mode tFR tFF tFRFM VCRS FS Output Rise Time FS Output Fall Time (13,14) 10% to 90% ⏐VOH - VOL⏐; CL = 50 pF; Figure 3 90% to 10% ⏐VOH - VOL⏐; CL = 50 pF; Figure 3 tR/tF Excludes First Transition from Idle State (13,14) 4 4 90.0 1.3 VREG3V3/2 ±200mV 20 20 111. 1 2.0 ns (13,14) FS Rise/Fall Time Match (13,14) % V Output Signal Crossover Voltage Excludes First Transition from Idle State Driver Characteristics, LS Mode tLR tLF tLRFM VCRS LS Output Rise Time LS Output Fall Time (13,14) 10% to 90% ⏐VOH - VOL⏐; CL = 50 to 600pF; Figure 3 90% to 10% ⏐VOH - VOL⏐; CL = 50 to 600pF; Figure 3 tR/tF Excludes First Transition from Idle State (13,14) 75 75 80 1.3 300 300 125 2.0 ns (13,14) LS Rise/Fall Time Match (13,14) % V Output Signal Crossover Voltage Excludes First Transition from Idle State Driver Timing, FS Mode tPLH tPHL tPHZ tPLZ tPZH tPZL Driver Timing, LS Mode (13) Propagation Delay, FSE0/VO/VPO/ VMO to D+/DDriver Disable Delay, OE_N to D+/D- Input Edge Rates = 2.5ns; Figure 4 Figure 6 , Figure 8 20 20 18 18 ns ns ns ns ns ns Driver Enable Delay, OE_N to D+/D- Figure 6 , Figure 8 18 18 Receiver Timing, FS and LS Mode tPLH tPHL tPLH tPHL Differential Receiver Propagation (15) Delay, D+/D- to RCV Single-Ended Receiver Propagation Delay, D+/D- to VP, VM (13) CL = 15pF, Figure 5, Figure 9 21 21 18 18 ns ns ns ns CL = 15pF, Figure 5, Figure 9 SE0 Detection Timing tPWSE0 SE0 Pulse Width Detection for (13) INT_N Suspend, Config,Speed_N=011 VIO=VREG3V3= 3.6V 260 ns Notes: 12. Edge rates of Low Speed (LS) mode dominate; consequently, there are no propagation delays specified for LS Mode. 13. Not production tested; guaranteed by characterization. 14. Typical conditions are at 25°C and 3.3V. 15. Excludes exiting Suspend or HiZ Mode. © 2008 Fairchild Semiconductor Corporation FUSB1500 / FUSB1501 • Rev. 1.0.0 www.fairchildsemi.com 8 FUSB1500 / FUSB1501 — USB2.0 Full-Speed / Low-Speed Transceiver with Charger Detection Typical Performance Characteristics tRISE tFALL VIO Logic Input VIO /2 t PLH D+ VOH VCRS D- VOL VCRS VIO /2 t PHL V OH 90% V OL 10% 90% 10% GND Figure 3. Rise and Fall Time Figure 4. VO/FSE0/VPO/VMO to D+/D- D+ D- 2.0 0.8 V OH VCRS t PLH VIO/2 VCRS t PHL 1.8V 0.9V 0V V OH tPZH tPZL 0.9V tPHZ tPLZ Logic Output V OL VIO/2 V OL V CRS VOH - 0.3 V +0.3 OL Figure 5. D+/D- to RCV, VP, and VM Figure 6. OE_N to D+/D- Vpu Test Point D.U.T D .U.T 33 33 1.5K [1] Test Point 500 V Dn 15K RL CL D.U.T 50pF CL= 50 to 125pf, Full Speed CL= 50 to 600pf, Low Speed [1] FS V = 0 for tPZH, tPHZ V = VREG for tPZL, tPLZ mode connect to D+; D+ and D- to be matched for R L /C L termination. Figure 7. Load for D+/D- Figure 8. Load for Enable and Disable Time Test Point DUT 15pf Figure 9. Load for VM, VP, and RCV © 2008 Fairchild Semiconductor Corporation FUSB1500 / FUSB1501 • Rev. 1.0.0 www.fairchildsemi.com 9 FUSB1500 / FUSB1501 — USB2.0 Full-Speed / Low-Speed Transceiver with Charger Detection Functional Description The FUSB1500/1501 transceiver is designed to convert CMOS data into USB differential bus signal levels and to convert USB differential bus signals to CMOS data. The FUSB1500 supports the SE Mode interface from the controller, whereas the FUSB1501 supports the differential control interface. In addition, both devices have an extended Control Mode that enables a simplified dedicated charger functionality via a weak pull-up resistance (nominally 125kΩ). This mode is described in Table 4. To minimize EMI and noise, the outputs are edge-rate controlled with the rise and fall times defined for fullspeed (12Mbps) and low-speed (1.5Mbps) data rates. The rise and fall times are balanced between the differential pins to minimize skew. Table 1. Function Table for USB Mode The FUSB1500/1501 is defined as a self-powered device, or bus-powered where the regulation down to 3.3V is external to the FUSB1500/1501, so it accepts the regulated 3.3V as its supply input. The VIO rail supports I/Os of 1.65V to 3.6V. If VIO is lost, the pins go into the high-Z state. If VIO is present, but the VREG3V3 power supply is lost, the high-Z detection circuit still functions. USB Mode Table 1 describes the specific pin functionality when USB Traffic Mode is selected. This is also referred to as normal mode. Table 2 and Table 3 describe the specific truth tables for driver and receiver operating functions. OE_N LOW HIGH LOW Hi-Z LOW LOW LOW D+, DDriving & Receiving Receiving Driving (16) RCV Active Active Inactive (17) VP/VM Active Active Active ) (18 Function Normal Driving (Differential Receiver Active) Receiving Driving during Suspend (Differential Receiver Inactive) Notes: 16. Signal levels on the D+ and D- pins are determined by external connections and Table 4 (Extended Control Configurations). 17. When in Suspend Mode (see Table 4 for suspended configurations), the differential receiver is inactive and the RCV output is forced LOW. Out-of-suspend signaling (K) is detected via the single-ended receiver outputs VP and VM. 18. The states of VP and VM are functions of signal levels on D+/D- in normal mode. Table 2. Driver Function (OE_N = L, HiZ= L or Floating ) USB Transmit Mode FSE0/VMO LOW LOW HIGH HIGH VO/VPO LOW HIGH LOW HIGH FUSB1500 Data (D+, D-) Differential Logic 0 (01) Differential Logic 1 (10) SE0 SE0 (19) (19) FUSB1501 Data (D+, D-) SE0 (19) (00) Differential Logic 1 (10) Differential Logic 0 (01) Illegal State (11) (00) (00) Note: 19. SE0 – Single-Ended Zero. Table 3. Receiver Function (OE_N = H, HiZ= L or Floating ) USB Receive Mode D+, DDifferential Logic 1 Differential Logic 0 SE0 X-(Sharing Mode) (22) RCV HIGH LOW RCV (21) VP (20) VM (20) HIGH LOW LOW HIGH LOW HIGH LOW HIGH LOW Note: 20. VP = VM = HIGH indicates Sharing Mode. 21. Denotes the signal level on output RCV prior to the SE0 event. This level is stable during the SE0 event period. 22. Sharing mode is not a function of D+/D- but is entered when VIO is present and VREG3V3 is disconnected. © 2008 Fairchild Semiconductor Corporation FUSB1500 / FUSB1501 • Rev. 1.0.0 www.fairchildsemi.com 10 FUSB1500/1501 — USB2.0 Full-Speed / Low-Speed Transceiver with Charger Detection Functional Description (Continued) Extended Control Mode This block of control has a multi-function role; it is used to signal a SE0 detect to the host via INT_N and uses a weak resistor pull-up method for charger detection. Note that the signaling of SE0 via INT_N is only enabled for the state “011” and all SE0 events can still be decoded from the VP, VM, and RCV outputs. When the three inputs (SUSPND, CONFIG, and SPEED_N) are not “011,” INT_N is not active; the SE0 detector (RCV = 0) is not active and its latch is set to HIGH. When the “011” is seen on the inputs, the FUSB1500/1501 is waiting for an SE0 event. When the SE0 event (deglitched) is detected, INT_N goes active (HL transition). The host detects this INT_N signal and configures the inputs to the pattern “110” or “010” to keep the 1.5kΩ pull-up enabled. The INT_N signal is then de-asserted and the SE0 detector reset. If a code other than “010” or “110” is written, the mode configuration is a function as described in Table 4 and the SE0 detector and INT_N are de-asserted to reset states. When entering the state “111,” which enables the weak pull up resistor for charger detection, the D+/D- drivers are automatically configured to USB receive mode (equivalent to OE_N HIGH). Figure 10 shows the extended control logic and Table 4 the truth table for the extended control. Figure 10. Table 4. Extended Control Extended Control Function Hi-Z 0 0 0 0 0 0 0 0 1 SUSPND CONFIG SPEED_N 0 0 0 0 1 1 1 1 X 0 1 0 1 0 1 0 1 X 0 0 1 1 0 0 1 1 X No 1.5kΩ Pull-up 1.5kΩ Pull-up No 1.5kΩ Pull-up Function FS FS LS FS FS FS LS USB Mode, Default State USB Mode USB Mode Suspend, Conditional Pull-up Suspend Suspend Suspend USB Rx Mode & RWPU On Hi-Z Mode Pull-up On After Detecting SE0 No 1.5kΩ Pull-up 1.5kΩ Pull-up No 1.5kΩ Pull-up No 1.5kΩ Pull-up, 125kΩ Pull-up Connected VP, VM, D+, D-, RCV High Impedance, SW1 and SW2 Open © 2008 Fairchild Semiconductor Corporation FUSB1500 / FUSB1501 • Rev. 1.0.0 www.fairchildsemi.com 11 FUSB1500 / FUSB1501 — USB2.0 Full-Speed / Low-Speed Transceiver with Charger Detection Functional Description (Continued) Power Supply Configurations and Options The three modes of power-supply operation are: Normal Mode – The VIO and VREG3V3 pins are connected. VIO is an independent voltage source (1.65 to 3.6V) that is a function of the external circuit configuration. Disable Mode – VIO is not connected; VREG3V3 is connected. In this mode, the D+, D- pins are threestate and the device enters low-power (suspended) state upon detection of VIO lost. Hi-Z Mode – W hen the Hi-Z pin is pulled HIGH, with VREG3V3 powered, the RCV/VP/VM interface can be used to access the Baseband for production test programming. VP/VM/RCV are in high impedance states. Sharing Mode – VIO is the only supply connected. In this mode, the D+ and D- pins are three-state and the FUSB1500 / FSUSB1501 allows external signals up to 3.6V to share the D+ and D- bus lines. Internally, the circuitry limits leakage from the D+ and D- pins (maximum 10μA) and VIO such that device is in low-power (suspended) state. The VP and VM pins are driven HIGH and RCV is forced LOW as an indication of this mode. Can be used for production test programming via D+/D-. to UART or Baseband processor. HiZ is to be Low or Floating to ensure VP/VM/RCV is signaled to processor. A summary of the supply configurations is described in Table 5. Table 5. Power Supply Mode Configuration Options Pin VREG3V3 VIO VPU D+, DVP / VM RCV VPO, VMO, SPEED_N,OE_N, SUSPND, CONFIG HiZ INT_N Note: 23. Three-state or driven LOW. Hi-Z 3.3V Externally Supplied 1.65 - 3.6V Source Three-State (Off) Three-State Three-State Three-State Inputs HIGH HIGH Sharing Not Connected 1.65-3.60V Source Three-State (Off) Three-State HIGH LOW Inputs LOW or Floating HIGH Disable Connected Not Connected Three-State (Off) Three-State Invalid Invalid (23) (23) Normal 3.3V Externally Supplied 1.65V- 3.60V Source Function of Mode Set-up Function of Mode Set-up Function of Mode Set-up Function of Mode Set-up Function of Mode Set-up LOW or Floating Function of Mode Set-up Three-state Three-state Three-State Single Ended Zero Detection Timing The SE0 detection logic is activated when entering the state “011” (SUSPND, CONFIG, and SPEED_N) and the logic waits to detect an SE0 event. Since the FUSB1500/1501 can also be used as an LS host device, it is important to ensure that the tLST time for the USB2.0 specification is met. tLST is the minimum time to not interpret LS differential signaling as an SE0 and is 210ns in duration. Similarly for FS differential signaling, there is a time period, tFST time, of 14ns. Seeing an SE0 for greater than tLST results in the INT_N pin toggling LOW. The FUSB1500/1501 is designed for 260ns (typical). Exiting HiZ or Suspend Mode Timing As the RCV path is required to maintain the previous state through an SE0 event, there is the possibility when exiting HiZ or Suspend Mode to have the previous result stored. The transition through the SE0 decode logic is such that software should ignore RCV for at least 100ns when exiting HiZ mode to ensure the correct D+/D- state is available on the RCV output. © 2008 Fairchild Semiconductor Corporation FUSB1500 / FUSB1501 • Rev. 1.0.0 www.fairchildsemi.com 12 FUSB1500 / FUSB1501 — USB2.0 Full-Speed / Low-Speed Transceiver with Charger Detection Hi-Z and Sharing Mode for Production Test W hen in production test, to gain access to the processor or UART, the D+/D- pins can be used (Sharing Mode) or the RCV/VP/VM interface of the host side of the FUSB1500/FUSB1501 (Hi-Z). If sharing the D+/D- pins then VREG3V3 is unpowered and the processor is signaled this mode via the VP/VM outputs being pulled High and the RCV pin is pulled Low. If the RCV/VP/VM interface is to be used by production test then Hi-Z is pulled High, with VREG3V3 remaining powered. Figure 11 indicates the production test scenarios. 1.65-1.95V 3.0-3.6V 1.65-1.95V UNPOWERED VIO VREG3V3 VIO VREG3V3 Production Test Jig 3-STATE 3-STATE BaseBand Processor SUSPND CONFIG SPEED_N OEb VPO FSE0 3-STATE RCV 3-STATE VP 3-STATE VM HIGH HiZ D+ D- 3-STATE 3-STATE BaseBand Processor SUSPND CONFIG SPEED_N OEb VPO FSE0 LOW HIGH HIGH L RCV VP VM HiZ To UART or Baseband D+ D- Production Test Jig Using RCV/VP/VM/HiZ as Interface to Production Test -VREG3V3 Powered Using D+/D- as Interface to Production Test -VREG3V3 Unpowered Figure 11. Production Test Using Hi-Z or Sharing Mode © 2008 Fairchild Semiconductor Corporation FUSB1500 / FUSB1501 • Rev. 1.0.0 www.fairchildsemi.com 13 FUSB1500 / FUSB1501 — USB2.0 Full-Speed / Low-Speed Transceiver with Charger Detection Physical Dimensions 0.10 C 2X PIN #1 IDENT. 3.0 A B 3.20 2.20 1.35 3.0 1.35 0.50 TYP 2.20 3.20 0.10 C TOP VIEW 0.8 MAX (0.70-0.80) 0.10 C 2X 0.50 TYP 0.30 TYP 0.50 TYP RECOMMENDED LAND PATTERN 0.08 C 0.05 0.00 SIDE VIEW C 0.25~0.35 12X 0.10 CAB 0.05 C 0.25~0.35 12X 0.10 CAB 0.05 C SEATING PLANE (3.10) 2.90 2.50 2.45 1.45 MAX 5 9 0.73 0.30~0.40 0.10 0.05 4X CAB C (3.10) 2.50 2.90 2.45 1.45 MAX 0.50 0.30~0.40 4X 0.10 CAB 0.05 C PIN #1 IDENT 0.73 1 13 DETAIL A DETAIL A 0.50 BOTTOM VIEW NOTES: A. SIMILAR TO JEDEC REGISTRATION MO-217, B. DIMENSIONS ARE IN MILLIMETERS. C. DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994 D. LANDPATTERN RECOMMENDATION IS PER FSC INTERNAL DESIGN E. DRAWING FILENAME: MLP16HBrev4 Figure 12. 16-Pin, Molded Leadless Package (MLP), JEDEC MO217 Equivalent, 3mm Square Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. Tape and Reel Specifications Please visit Fairchild Semiconductor’s online packaging area for the most recent tape and reel specifications: http://www.fairchildsemi.com/packaging/3x3MLP_Pack_TNR_16L.pdf. © 2008 Fairchild Semiconductor Corporation FUSB1500 / FUSB1501 • Rev. 1.0.0 www.fairchildsemi.com 14 FUSB1500 / FUSB1501 — USB2.0 Full-Speed / Low-Speed Transceiver with Charger Detection © 2008 Fairchild Semiconductor Corporation FUSB1500 / FUSB1501 • Rev. 1.0.0 www.fairchildsemi.com 15