FUSB2500

FUSB2500 — USB2.0 High-Speed OTG Transceiver with ULPI Interface April 2010 FUSB2500 USB2.0 High-Speed OTG Transceiver with ULPI Interface Features Complies with USB 2.0 OTG Rev 1.3 Supplement and ULPI Rev 1.1 Specifications Supports 480Mbps, 12Mbps, and 1.5Mbps USB2.0 Speeds Integrated Termination Resistors Meet USB2.0 Resistor ECN Integrated Serializer and Deserializer Insertion and Removal of Stuffed Bits as Appropriate USB Clock and Data Recovery to ±150ppm Supports USB OTG Rev 1.3 Host Negotiation Protocol (HNP) and Session Request Protocol (SRP) Description The FUSB2500 is a UTMI+ Low-Pin Interface (ULPI) USB2.0 On-The-Go (OTG) transceiver. It is compliant with the Universal Serial Bus Specification Rev 2.0 (USB2.0), the ULPI Specification Rev. 1.1, and the OOTG Supplement to USB2.0, Rev. 1.3. The FUSB2500 is optimized to connect the USB2.0 host, peripheral, or OTG-controller to the USB connector via the ULPI link. Data can be transmitted and received at high speed (480Mbps), full speed (12Mbps), and low speed (1.5Mbps) through a 12-bit (SDR) interface. The FUSB2500 also includes a charger-detection functional block that enables automatic detection for charging USB2.0 host ports or dedicated chargers. The FUSB2500 is compliant with Battery Charging Specification Rev. 1.0. Applications Cell phones, Digital Still Camera, PDA DVD Recorder, Scanner, Printer Video Camera, Set-Top Box, MP3 Player Related Resources UTMI+ Low Pin Interface Specification (ULPI), Revision 1.1, October 20, 2004. http://www.ulpi.org UTMI+ Specification, Revision 1.0, February 22, 2004. http://www.ulpi.org IMPORTANT NOTE: For additional performance information, please contact analogswitch@fairchildsemi.com. Ordering Information Part Number FUSB2500GFX Top Mark FUSB2500 Operating Temperature Range -40 to +85°C Package 36-Ball, Ball Grid Array (BGA), 3.5 x 3.5 x 1.0mm, 0.5mm Pitch © 2010 Fairchild Semiconductor Corporation FUSB2500 • Rev. 1.0.0 www.fairchildsemi.com FUSB2500 — USB2.0 High-Speed OTG Transceiver with ULPI Interface Block Diagram Figure 1. Functional Block Diagram © 2010 Fairchild Semiconductor Corporation FUSB2500 • Rev. 1.0.0 www.fairchildsemi.com 2 FUSB2500 — USB2.0 High-Speed OTG Transceiver with ULPI Interface Ball Configuration F Polarity Select Charger Detect VBATT VBUS CLKIN (19.2MHz) I.C. E Charger Detect Enable_N VREF5V_ FAULT VCC3V3 GND DIR VDD1V2 D DP GND ID PSW NXT STP C DM RREF Chip Select_N Reset_N GND D7 B D0 VIO (1.8V) Chip_Select CFG1 (GND 19.2MHz) VIO (1.8V) D6 A D1 D2 D3 CLOCK D4 D5 1 2 3 4 5 6 Figure 2. Ball Configuration (Bottom Up View) © 2010 Fairchild Semiconductor Corporation FUSB2500 • Rev. 1.0.0 www.fairchildsemi.com 3 FUSB2500 — USB2.0 High-Speed OTG Transceiver with ULPI Interface Pin Definitions Symbol (1) Ball B3 Type I (2) Description Active HIGH. LOW – ULPI pin three-stated; HIGH – ULPI operates normally. TTL compatible; CMOS input with hysteresis. If either Chip_Select or Chip_Select_N are de-asserted, the FUSB2500 is in power down and the ULPI bus is three-stated. For ULPI to operate, both signals need to be active. Active LOW. HIGH – ULPI pin three-stated; LOW – ULPI operates normally. TTL compatible; CMOS input with hysteresis. If either Chip_Select or Chip_Select_N are de-asserted, the FUSB2500 is in power down and the ULPI bus is three-stated. For ULPI to operate, both signals need to be active. Resistor reference. Connect through 12kΩ ±1% to GND. USB D- pin. This pin is 5V tolerant. USB mode: data minus (D-) pin of the USB cable. USB D+ pin. This pin is 5V tolerant. USB mode: data plus (D+) pin of the USB cable. VREF5V_FAULT is used to signal a VBUS over-current/over-voltage condition from an external SMPS or power management IC. The link must enable this function via the ExternalVbusFault register bit and the polarity must be set via the ExternalVbusActiveLow register bit. Identification (ID) pin of the micro-USB cable. TTL, If not used, connect to the VCC3V3 pin. If polarity is to be active LOW, connect 100KΩ to VBATT (in open-drain mode). If polarity is to be active HIGH, 100KΩ to GND is needed (open source). This is a 5V-tolerant pin referenced to an internal 3.3V rail generated from VBATT for charger detection when in power-down mode. When connected to GND, the charger-detect signal is active LOW. When connected to VBATT, the charger detect signal is active HIGH. This is a 5Vtolerant pin referenced to an internal 3.3V rail generated from VBATT for charger detection when in power-down mode. Active LOW. Connect to GND to activate. Connect to VBATT when charger detection is not required. This is a 5V-tolerant pin referenced to an internal 3.3V rail generated from VBATT for charger detection when in power-down mode. Input supply voltage or battery source. Nominally 2.7V to 4.5V. Operation of USB should function down to VBATT of 3.0V. Products may stop operating at (4) VBATT of 3.1V. Controls an external, active HIGH, VBUS power switch/charge pump and/or an SMPS charger IC. An external 100KΩ pull-down resistor is required. Open source, this pin is referenced to VCC3V3. Should be connected to the VBUS pin of the USB cable. Leave open circuit if not used. An internal 90KΩ ±11% pull-down resistor is present on this pin. 3.3V regulator output requiring capacitors. Internally powers OTG, analog core, and ATX. External capacitors are 0.1µF and 4.7µF. Clock input; 1.8V peak input allowed; frequency depends on the CFG1 pin. This is a digital input buffer, not analog for a crystal. Internally connected; leave OPEN. Continued on the following page... Chip_Select Chip Select_N RREF DM DP (3) C3 C2 C1 D1 I AI/O AI/O AI/O VREF5V_FAULT E2 I ID D3 I Charger Detect F2 O Polarity Select F1 I Charger Detect Enable_N E1 I VBATT F3 P PSW D4 O VBUS VCC3V3 CLKIN I.C. F4 E3 F5 F6 AI/O P I I/O © 2010 Fairchild Semiconductor Corporation FUSB2500 • Rev. 1.0.0 www.fairchildsemi.com 4 FUSB2500 — USB2.0 High-Speed OTG Transceiver with ULPI Interface Pin Definitions (Continued) Symbol CFG1 VDD1V2 DIR STP NXT D7 D6 D5 D4 D3 D2 D1 D0 CLOCK VIO Reset_N GND (1) Ball B4 E6 E5 D6 D5 C6 B6 A6 A5 A3 A2 A1 B1 A4 B2, B5 C4 E4,D2, C5 Type I P O I O I/O I/O I/O I/O I/O I/O I/O I/O O P I P (2) Description Configures the clock frequency; 0: input is 19.2MHz. 1: input is 26MHz. 1.2V regulator output requiring capacitors. Internally powers the digital core. External capacitors are 0.1µF and 4.7µF. ULPI direction output signal; slew-rate-controlled output (2ns typical). ULPI stop input signal; CMOS input. ULPI next output signal; slew-rate-controlled output (2ns typical). ULPI data pin 7; three-state output; slew-rate-controlled output (2ns typical); CMOS input. ULPI data pin 6; three-state output; slew-rate-controlled output (2ns typical); CMOS input. ULPI data pin 5; three-state output; slew-rate-controlled output (2ns typical); CMOS input. ULPI data pin 4; three-state output; slew-rate-controlled output (2ns typical); CMOS input. ULPI data pin 3; three-state output; slew-rate-controlled output (2ns typical); CMOS input. ULPI data pin 2; three-state output; slew-rate-controlled output ( 2ns typical); CMOS input. ULPI data pin 1; three-state output; slew-rate-controlled output ( 2ns typical); CMOS input. ULPI data pin 0; three-state output; slew-rate-controlled output ( 2ns typical); CMOS input. 60MHz clock output when digital 19.2MHz (or 26MHz) clock is applied; Push-pull output; slew-rate-controlled output (2ns). Input I/O supply rail; 1.65V-1.95V; nominally 1.8V. 0.1µF capacitor connected to power input. Connect to VIO 1.8V when not used. Resets the transceiver; active LOW. Connect to ground. Notes: 1. Symbol names ending with underscore N (for example, NAME_N) indicate active LOW signals. 2. I=input; O=output; I/O=digital input/output; OD=open-drain output; AI/O=analog input/output; P=power or ground pin. 3. A 125KΩ resistor is used for basic charger detection. 4. Per the USB2.0 specification, below a supply of 2.97V, USB full-speed and low-speed transactions are not guaranteed; although some devices may continue to function with the FUSB2500 at the lower supply rail. © 2010 Fairchild Semiconductor Corporation FUSB2500 • Rev. 1.0.0 www.fairchildsemi.com 5 FUSB2500 — USB2.0 High-Speed OTG Transceiver with ULPI Interface Physical Dimensions 2X 0.10 C 3.50 A B 0.50 Ø0.270 Ø0.370 TERMINAL A1 CORNER INDEX AREA 3.50 2.50 2X 0.10 C 2.50 TOP VIEW 1.08 STATISTICAL MAX 0.10 C NSMD LAND PATTERN RECOMMENDATION 0.50±0.03 0.26±0.05 C SEATING PLANE 0.08 C 0.22±0.05 (0.5) 2.5 (0.35) (0.35) F E D C B A 0.5 0.5 (0.50) A. CONFORMS TO JEDEC REGISTRATION MO-195 DESIGN STANDARD. B. DIMENSIONS ARE IN MILLIMETERS. 2.5 C. DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994 D. LAND PATTERN RECOMENDATION PER IPC-7351 E. DRAWING FILENAME MKT-BGA36Brev1 1 2 3 4 5 6 Ø0.3±0.05 X36 BOTTOM VIEW 0.15 0.05 CAB C Figure 24. 36-Ball BGA Package Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. © 2010 Fairchild Semiconductor Corporation FUSB2500 • Rev. 1.0.0 www.fairchildsemi.com 55 FUSB2500 — USB2.0 High-Speed OTG Transceiver with ULPI Interface © 2010 Fairchild Semiconductor Corporation FUSB2500 • Rev. 1.0.0 www.fairchildsemi.com 56