NDS351N

March 1996 NDS351N N-Channel Logic Level Enhancement Mode Field Effect Transistor General Description These N-Channel logic level enhancement mode power field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. These devices are particularly suited for low voltage applications in notebook computers, portable phones, PCMCIA cards, and other battery powered circuits where fast switching, and low in-line power loss are needed in a very small outline surface mount package. Features 1.1A, 30V. RDS(ON) = 0.25Ω @ VGS = 4.5V. Proprietary package design using copper lead frame for superior thermal and electrical capabilities. High density cell design for extremely low RDS(ON). Exceptional on-resistance and maximum DC current capability. Compact industry standard SOT-23 surface mount package. ________________________________________________________________________________ D G S Absolute Maximum Ratings Symbol VDSS VGSS ID PD TJ,TSTG Parameter Drain-Source Voltage T A = 25°C unless otherwise noted NDS351N 30 20 (Note 1a) Units V V A Gate-Source Voltage - Continuous Maximum Drain Current - Continuous - Pulsed Maximum Power Dissipation (Note 1a) (Note 1b) ± 1.1 ± 10 0.5 0.46 -55 to 150 W Operating and Storage Temperature Range °C THERMAL CHARACTERISTICS RθJA RθJC Thermal Resistance, Junction-to-Ambient (Note 1a) 250 (Note 1) °C/W °C/W Thermal Resistance, Junction-to-Case 75 © 1997 Fairchild Semiconductor Corporation NDS351N Rev. E2 Electrical Characteristics (TA = 25°C unless otherwise noted) Symbol Parameter Conditions Min Typ Max Units OFF CHARACTERISTICS BVDSS IDSS IGSSF IGSSR VGS(th) RDS(ON) Drain-Source Breakdown Voltage Zero Gate Voltage Drain Current VGS = 0 V, ID = 250 µA VDS = 24 V, VGS = 0 V TJ =125°C Gate - Body Leakage, Forward Gate - Body Leakage, Reverse VGS = 12 V, VDS = 0 V VGS = -12 V, VDS = 0 V VDS = VGS, ID = 250 µA TJ =125°C Static Drain-Source On-Resistance VGS = 4.5 V, ID = 1.1 A TJ =125°C VGS = 10 V, ID = 1.4 A ID(ON) gFS Ciss Coss Crss td(on) tr td(off) tf Qg Qgs Qgd On-State Drain Current Forward Transconductance VGS = 4.5 V, VDS = 5 V VDS = 5 V, ID = 1.1 A VDS = 10 V, VGS = 0 V, f = 1.0 MHz 5 2.5 0.8 0.5 1.6 1.3 0.185 0.26 0.135 30 1 10 100 -100 V µA µA nA nA ON CHARACTERISTICS (Note 2) Gate Threshold Voltage 2 1.5 0.25 0.37 0.16 A S V Ω DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Reverse Transfer Capacitance 140 80 18 pF pF pF SWITCHING CHARACTERISTICS (Note 2) Turn - On Delay Time Turn - On Rise Time Turn - Off Delay Time Turn - Off Fall Time Total Gate Charge Gate-Source Charge Gate-Drain Charge VDS = 10 V, ID = 1.1 A, VGS = 5 V VDD = 10 V, ID = 1 A, VGS = 10 V, RGEN = 50 Ω 9 16 26 19 2 15 30 50 40 3.5 1 2 ns ns ns ns nC nC nC NDS351N Rev. E2 Electrical Characteristics (TA = 25°C unless otherwise noted) Symbol Parameter Conditions Min Typ Max Units DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS IS ISM VSD Notes: 1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RθJC is guaranteed by design while RθCA is determined by the user's board design. Maximum Continuous Drain-Source Diode Forward Current Maximum Pulsed Drain-Source Diode Forward Current Drain-Source Diode Forward Voltage VGS = 0 V, IS = 1.1 A (Note 2) 0.8 0.6 5 1.2 A A V PD(t ) = R θJ At ) ( TJ −TA = TJ −TA R θJ C RθCA t ) + ( = I 2 (t ) × RDS ( ON ) D TJ Typical RθJA using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment: a. 250oC/W when mounted on a 0.02 in2 pad of 2oz cpper. b. 270oC/W when mounted on a 0.001 in2 pad of 2oz cpper. 1a 1b Scale 1 : 1 on letter size paper 2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%. NDS351N Rev. E2 Typical Electrical Characteristics 8 2.5 VGS = 1 0V I D , DRAIN-SOURCE CURRENT (A) 6 6.0 5.0 DRAIN-SOURCE ON-RESISTANCE 4.5 R DS(on) , NORMALIZED VGS = 3 .0V 3.5 2 4 .0 4.0 1.5 4 3 .5 4.5 5 .0 1 2 3 .0 2.5 6 .0 10 0 0 1 V DS 2 3 , DRAIN-SOURCE VOLTAGE (V) 4 0.5 0 2 4 I D , DRAIN CURRENT (A) 6 8 Figure 1. On-Region Characteristics Figure 2. On-Resistance Variation with Gate Voltage and Drain Current 1.6 2.5 I D = 1.1A 1.4 R DS(ON), NORMALIZED V GS = 4.5V RDS(on) , NORMALIZED DRAIN-SOURCE ON-RESISTANCE V GS = 4.5 V 2 DRAIN-SOURCE ON-RESISTANCE 1.2 1.5 TJ = 125°C 1 25°C 1 0.8 -55°C 0.5 0.6 -50 -25 0 25 50 75 100 TJ , JUNCTION TEMPERATURE (°C) 125 150 0 2 4 I , DRAIN CURRENT (A) D 6 8 Figure 3. On-Resistance Variation with Temperature Figure 4. On-Resistance Variation with Drain Current and Temperature 5 GATE-SOURCE THRESHOLD VOLTAGE 1.2 V DS = 10V 4 ID , DRAIN CURRENT (A) TJ = -55°C 25 1 25°C V DS = V 1.1 GS I D = -250µA 3 V th , NORMALIZED 1 2 0.9 1 0.8 0 1 2 3 4 V GS , GATE TO SOURCE VOLTAGE (V) 5 0.7 -50 -25 0 25 50 75 100 TJ , JUNCTION TEMPERATURE (°C) 125 150 Figure 5. Transfer Characteristics Figure 6. Gate Threshold Variation with Temperature NDS351N Rev. E2 Typical Electrical Characteristics (continued) 1.15 DRAIN-SOURCE BREAKDOWN VOLTAGE 5 I D = 250µA I S, REVERSE DRAIN CURRENT (A) 1.1 2 1 0.5 0.2 0.1 V GS = 0V BV DSS , NORMALIZED 1.05 T J = 125°C 25°C - 55°C 1 0.01 0.95 0.9 -50 -25 0 T J 25 50 75 100 , JUNCTION TEMPERATURE (°C) 125 150 0.001 0.3 V SD 0.6 0.9 1.2 , BODY DIODE FORWARD VOLTAGE (V) Figure 7. Breakdown Voltage Variation with Temperature Figure 8. Body Diode Forward Voltage Variation with Current and Temperature 300 200 VGS , GATE-SOURCE VOLTAGE (V) 10 C i ss CAPACITANCE (pF) 100 I DS = 1.1A 8 VDS = 5V 10V C o ss 6 50 30 20 4 f = 1 MHz V GS = 0V C r ss 2 10 0.1 0 0.2 V 0.5 DS 1 2 5 10 20 30 0 1 2 Q g , GATE CHARGE (nC) 3 4 , DRAIN TO SOURCE VOLTAGE (V) Figure 9. Capacitance Characteristics Figure 10. Gate Charge Characteristics VDD t d(on) t on tr 90% t off t d(off) 90% tf V IN D RL V OUT DUT Output, Vout VGS 10% 10% 90% R GEN Inverted G Input, Vin S 10% 50% 50% Pulse Width Figure 11. Switching Test Circuit Figure 12. Switching Waveforms NDS351N Rev. E2 Typical Electrical Characteristics (continued) 6 20 V DS = 5 V , TRANSCONDUCTANCE (SIEMENS) 10 T J = -55°C I D, DRAIN CURRENT (A) 4 5 2 1 0.5 R ( DS ) ON LIM IT 10 1m 10 10 ms s 0u s 2 5°C s 1 25°C 2 0m 0.1 0.05 V GS = 10V SINGLE PULSE T A = 25°C 1 10 s s DC g 0 0 2 4 I D , DRAIN CURRENT (A) 6 8 FS 0.01 0.1 0.2 0.5 V DS 1 2 5 10 30 50 , D RAIN-SOURCE VOLTAGE (V) Figure 13. Transconductance Variation with Drain Current and Temperature Figure 14. Maximum Safe Operating Area 1 0.5 r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE D = 0 .5 0.2 0.1 0.05 0.02 0.01 0.005 0.002 0.001 0.0001 0 .2 0 .1 0 .05 0 .02 0 .01 P(pk) R θJA (t) = r(t) * RθJA R = 250 °C/W θJA t1 S ingle Pulse t2 TJ - T A = P * R θJA (t) D uty Cycle, D = t1 /t2 0.001 0.01 0.1 t1 , TIME (sec) 1 10 100 300 Figure 15. Transient Thermal Response Curve Note : Characterization performed using the conditions described in note 1c. Transient thermal response will change depending on the circuit board design. NDS351N Rev. E2