NDS351AN
NDS351AN
N-Channel, Logic Level, PowerTrench MOSFET
General Description
Features
These N-Channel Logic Level MOSFETs are produced
using
ON
Semiconductor’s
advanced
PowerTrench process that has been especially tailored
to minimize the on-state resistance and yet maintain
superior switching performance.
• 1.4 A, 30 V.
RDS(ON) = 160 mΩ @ VGS = 10 V
RDS(ON) = 250 mΩ @ VGS = 4.5 V
• Ultra-Low gate charge
These devices are particularly suited for low voltage
applications in notebook computers, portable phones,
PCMCIA cards, and other battery powered circuits
where fast switching, and low in-line power loss are
needed in a very small outline surface mount package.
• Industry standard outline SOT-23 surface mount
package using proprietary SuperSOTTM-3 design for
superior thermal and electrical capabilities
• High performance trench technology for extremely
low RDS(ON)
D
D
S
S
G
TM
SuperSOT -3
G
Absolute Maximum Ratings
Symbol
TA=25oC unless otherwise noted
Parameter
VDSS
Drain-Source Voltage
VGSS
Gate-Source Voltage
ID
Drain Current
– Continuous
(Note 1a)
– Pulsed
TJ, TSTG
Units
30
V
± 20
V
1.4
A
10
Power Dissipation for Single Operation
PD
Ratings
(Note 1a)
0.5
(Note 1b)
0.46
W
–55 to +150
°C
(Note 1a)
250
°C/W
(Note 1)
75
Operating and Storage Junction Temperature Range
Thermal Characteristics
RθJA
Thermal Resistance, Junction-to-Ambient
RθJC
Thermal Resistance, Junction-to-Case
Package Marking and Ordering Information
Device Marking
Device
Reel Size
Tape width
Quantity
351A
NDS351AN
7’’
8mm
3000 units
© 2003 Semiconductor Components Industries, LLC.
September-2017, Rev. 5
Publication Order Number:
NDS351AN/D
Symbol
Parameter
TA = 25°C unless otherwise noted
Test Conditions
Min
Typ
Max Units
Off Characteristics
ID = 250 µA
BVDSS
Drain–Source Breakdown Voltage
VGS = 0 V,
∆BVDSS
∆TJ
IDSS
Breakdown Voltage Temperature
Coefficient
Zero Gate Voltage Drain Current
ID = 250 µA,Referenced to 25°C
VDS = 24 V,
30
V
26
VGS = 0 V
VDS = 24 V, VGS = 0 V, TJ = 55°C
IGSS
Gate–Body Leakage
On Characteristics
VGS = ±20 V,
VDS = 0 V
ID = 250 µA
mV/°C
1
µA
10
µA
±100
nA
(Note 2)
VGS(th)
Gate Threshold Voltage
VDS = VGS,
∆VGS(th)
∆TJ
RDS(on)
Gate Threshold Voltage
Temperature Coefficient
Static Drain–Source
On–Resistance
ID = 250 µA,Referenced to 25°C
0.8
2.1
–4
3
V
92
120
114
ID(on)
On–State Drain Current
VGS = 10 V,
ID = 1.4 A
VGS = 4.5 V,
ID = 1.2 A
VGS = 10 V, ID = 1.4 A, TJ = 125°C
VGS = 4.5V,
VDS = 5 V
gFS
Forward Transconductance
VDS = 5 V,
ID = 1.4 A
4
S
VDS = 15 V,
f = 1.0 MHz
V GS = 0 V,
145
pF
35
pF
15
pF
Ω
mV/°C
160
250
214
3.5
mΩ
A
Dynamic Characteristics
Ciss
Input Capacitance
Coss
Output Capacitance
Crss
Reverse Transfer Capacitance
RG
Gate Resistance
Switching Characteristics
VGS = 15 mV,
f = 1.0 MHz
1.6
VDD = 15 V,
VGS = 10 V,
ID = 1 A,
RGEN = 6 Ω
3
6
ns
8
16
ns
(Note 2)
td(on)
Turn–On Delay Time
tr
Turn–On Rise Time
td(off)
Turn–Off Delay Time
16
29
ns
tf
Turn–Off Fall Time
2
4
ns
Qg
Total Gate Charge
1.3
1.8
nC
Qgs
Gate–Source Charge
Qgd
Gate–Drain Charge
VDS = 15 V,
VGS = 4.5 V
ID = 1.4 A,
0.5
nC
0.5
nC
Drain–Source Diode Characteristics and Maximum Ratings
IS
Maximum Continuous Drain–Source Diode Forward Current
VSD
trr
Drain–Source Diode Forward
Voltage
Diode Reverse Recovery Time
Qrr
Diode Reverse Recovery Charge
VGS = 0 V,
IF = 1.4 A,
IS = 0.42 A
(Note 2)
diF/dt = 100 A/µs
0.8
0.42
A
1.2
V
11
nS
4
nC
Notes:
1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of
the drain pins. RθJC is guaranteed by design while RθCA is determined by the user's board design.
a) 250°C/W when mounted on a
0.02 in2 pad of 2 oz. copper.
b) 270°C/W when mounted on a
minimum pad.
Scale 1 : 1 on letter size paper
2.
Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2.0%
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NDS351AN
Electrical Characteristics
NDS351AN
Typical Characteristics
5
2.8
VGS = 10V
4.5V
2.6
RDS(ON), NORMALIZED
DRAIN-SOURCE ON-RESISTANCE
ID, DRAIN CURRENT (A)
6.0V
4
3
3.5V
2
1
3.0V
2.4
VGS = 3.5V
2.2
2
1.8
1.6
4.0V
4.5V
1.4
5.0V
1.2
6.0V
10V
1
0.8
0
0
0.5
1
1.5
0
2
1
2
Figure 1. On-Region Characteristics.
5
0.25
ID = 1.4A
VGS = 10V
ID = 0.7A
RDS(ON), ON-RESISTANCE (OHM)
RDS(ON), NORMALIZED
DRAIN-SOURCE ON-RESISTANCE
4
Figure 2. On-Resistance Variation with
Drain Current and Gate Voltage.
1.6
1.4
1.2
1
0.8
0.225
0.2
0.175
TA = 125oC
0.15
0.125
0.1
TA = 25oC
0.075
0.6
-50
-25
0
25
50
75
100
125
3
150
4
5
o
6
7
8
9
10
VGS, GATE TO SOURCE VOLTAGE (V)
TJ, JUNCTION TEMPERATURE ( C)
Figure 3. On-Resistance Variation with
Temperature.
Figure 4. On-Resistance Variation with
Gate-to-Source Voltage.
10
5
IS, REVERSE DRAIN CURRENT (A)
VDS = 5V
ID, DRAIN CURRENT (A)
3
ID, DRAIN CURRENT (A)
VDS, DRAIN TO SOURCE VOLTAGE (V)
4
3
2
TA = 125oC
1
25oC
-55oC
0
VGS = 0V
1
TA = 125oC
0.1
25oC
0.01
-55oC
0.001
0.0001
2
2.5
3
3.5
4
0
VGS, GATE TO SOURCE VOLTAGE (V)
Figure 5. Transfer Characteristics.
0.2
0.4
0.6
0.8
1
1.2
VSD, BODY DIODE FORWARD VOLTAGE (V)
Figure 6. Body Diode Forward Voltage Variation
with Source Current and Temperature.
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NDS351AN
Typical Characteristics
10
200
VGS, GATE-SOURCE VOLTAGE (V)
ID =1.4A
VDS = 10V
180
15V
8
CAPACITANCE (pF)
20V
6
4
140
120
100
2
80
60
COSS
40
20
CRSS
0
0
0
0.5
1
1.5
2
2.5
0
3
5
Qg, GATE CHARGE (nC)
15
20
25
30
Figure 8. Capacitance Characteristics.
100
5
P(pk), PEAK TRANSIENT POWER (W)
ID, DRAIN CURRENT (A)
10
VDS, DRAIN TO SOURCE VOLTAGE (V)
Figure 7. Gate Charge Characteristics.
100µs
10
RDS(ON) LIMIT
1ms
10ms
100ms
1
1s
VGS = 10V
SINGLE PULSE
RθJA = 270oC/W
0.1
DC
TA = 25oC
0.01
0.1
1
10
100
SINGLE PULSE
RθJA = 270°C/W
TA = 25°C
4
3
2
1
0
0.01
0.1
1
VDS, DRAIN-SOURCE VOLTAGE (V)
10
100
1000
t1, TIME (sec)
Figure 9. Maximum Safe Operating Area.
r(t), NORMALIZED EFFECTIVE TRANSIENT
THERMAL RESISTANCE
f = 1 MHz
VGS = 0 V
CISS
160
Figure 10. Single Pulse Maximum
Power Dissipation.
1
D = 0.5
RθJA(t) = r(t) * RθJA
0.2
RθJA = 270 C/W
o
0.1
0.1
P(pk)
0.05
t1
0.02
0.01
t2
TJ - TA = P * RθJA(t)
Duty Cycle, D = t1 / t2
0.01
SINGLE PULSE
0.001
0.0001
0.001
0.01
0.1
1
10
t1, TIME (sec)
Figure 11. Transient Thermal Response Curve.
Thermal characterization performed using the conditions described in Note 1b.
Transient thermal response will change depending on the circuit board design.
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