RFP14N05

RFD14N05, RFD14N05SM, RFP14N05 Data Sheet January 2002 14A, 50V, 0.100 Ohm, N-Channel Power MOSFETs These are N-channel power MOSFETs manufactured using the MegaFET process. This process, which uses feature sizes approaching those of LSI integrated circuits, gives optimum utilization of silicon, resulting in outstanding performance. They were designed for use in applications such as switching regulators, switching converters, motor drivers and relay drivers. These transistors can be operated directly from integrated circuits. Formerly developmental type TA09770. Features • 14A, 50V • rDS(ON) = 0.100Ω • Temperature Compensating PSPICE ® Model • Peak Current vs Pulse Width Curve • UIS Rating Curve • 175o C Operating Temperature • Related Literature - TB334 “Guidelines for Soldering Surface Mount Components to PC Boards” Ordering Information PART NUMBER RFD14N05 RFD1 4N05SM RFP14N05 PACKAGE TO-251AA TO-252AA TO-220AB BRAND D14N05 D14N05 RFP14N05 G Symbol D NOTE: When ordering, use the entire part number. Add the suffix 9A to obtain the TO-252AA variant in the tape and reel, i.e., RFD14N05SM9A. S Packaging JEDEC TO-251AA SOURCE DRAIN GATE DRAIN (FLANGE) GATE SOURCE JEDEC TO-252AA DRAIN (FLANGE) JEDEC TO-220AB SOURCE DRAIN GATE DRAIN (FLANGE) ©2002 Fairchild Semiconductor Corporation RFD14N05, RFD14N05SM, RFP14N05 Rev. B1 RFD14N05, RFD14N05SM, RFP14N05 Absolute Maximum Ratings T C = 2 5 oC, Unless Otherwise Specified R FD14N05, RFD14N05SM, RFP14N05 50 50 ± 20 14 Refer to Peak Current Curve Refer to UIS Curve 48 0.32 -55 to 175 300 260 UNITS V V V A Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V DSS Drain to Gate Voltage (R G S = 2 0k Ω ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V DGR Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V GS Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E AS Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P D Derate above 25o C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T J, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .T L Package Body for 10s, See Techbrief 334. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T pkg W W/ oC oC oC oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress on ly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. T J = 2 5 o C to 150oC. Electrical Specifications P ARAMETER Drain to Source Breakdown Voltage Gate Threshold Voltage Zero Gate Voltage Drain Current TC = 2 5 oC, Unless Otherwise Specified SYMBOL BV DSS V GS(TH) IDSS TEST CONDITIONS ID = 2 50 µA, VGS = 0 V (Figure 9) V GS = VDS, ID = 2 50 µA V DS = R ated BVDSS , VG S = 0 V V DS = 0 .8 x Rated BV DSS, VGS = 0V, T C = 1 50 oC V GS = ±2 0V ID = 1 4A, V GS = 1 0V, (Figure 11) V DD = 2 5V, ID ≈ 1 4A, V GS = 1 0V, RG S = 2 5 Ω, R L = 1 .7 Ω (Figure 13) MIN 50 2 V GS = 0 V to 20V V GS = 0 V to 10V V GS = 0 V to 2V V DD = 4 0V, ID = 1 4A, RL = 2 .86 Ω Ig(REF) = 0 .4mA (Figure 13) TO-251 and TO-252 TO-220 TYP 14 26 45 17 570 185 50 MAX 4 25 250 ± 100 0.100 60 100 40 25 1.5 3.125 100 80 UNITS V V µA µA nA Ω ns ns ns ns ns ns nC nC nC pF pF pF oC/W oC/W oC/W Gate to Source Leakage Current Drain to Source On Resistance (Note 2) Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time Total Gate Charge Gate Charge at 5V Threshold Gate Charge Input Capacitance Output Capacitance Reverse Transfer Capacitance Thermal Resistance Junction to Case Thermal Resistance Junction to Ambient IGSS r DS(ON) tON td(ON) tr td(OFF) tf tOFF Qg(TOT) Qg(10) Qg(TH) CISS C OSS C RSS R θ JC R θ JA R θ JA V DS = 2 5V, V G S = 0 V, f = 1MHz (Figure 12) Source to Drain Diode Specifications PARAMETER Source to Drain Diode Voltage (Note 2) Diode Reverse Recovery Time NOTES: 2. Pulse Test: Pulse Width ≤ 3 00ms, Duty Cycle ≤ 2 %. 3. Repetitive Rating: Pulse Width limited by max junction temperature. See Transient Thermal Impedance Curve (Figure 3) and Peak Current Capability Curve (Figure 5). SYMBOL V SD trr ISD = 1 4A ISD = 1 4A, dI SD/dt = 100A/ µs TEST CONDITIONS MIN TYP MAX 1.5 125 UNITS V ns ©2002 Fairchild Semiconductor Corporation RFD14N05, RFD14N05SM, RFP14N05 Rev. B1 RFD14N05, RFD14N05SM, RFP14N05 Typical Performance Curves 1.2 P OW ER D I SSI PA TI ON M U L TI PL IE R Unless Otherwise Specified 16 1.0 I D, D R AI N C U RR EN T ( A) 0 25 50 75 100 125 150 175 12 0.8 0.6 8 0.4 0.2 4 0 TC , CASE TEMPERATURE ( o C) 0 25 50 75 100 125 T C, CASE TEMPERATURE (oC) 150 175 F IGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE 1 T H ER MA L I M PED A NC E Zθ J C, NO RM A LI Z ED 0.5 0.2 0.1 0.1 0.05 0.02 0.01 t1 t2 NOTES: DUTY FACTOR: D = t1 /t2 PEAK T J = P DM x ZθJA x R θ JA + TA 10 -3 10-2 10 -1 t, RECTANGULAR PULSE DURATION (s) 100 10 1 PDM SINGLE PULSE 0.01 10-5 1 0-4 FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE IDM , PEA K C UR R EN T C A PA BI L IT Y (A ) 100 TJ = MAX RATED SINGLE PULSE TC = 25o C VGS = 20V 100 VGS = 10V FOR TEMPERATURES ABOVE 25 oC DERATE PEAK CURRENT AS FOLLOWS: I=I 25  ID, D R A IN CU R RE NT (A ) 100µ s 10 OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON)  175 – T C --------------------- 150   1ms 10ms 1 1 10 VDS , DRAIN TO SOURCE VOLTAGE (V) DC 100ms 100 TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION 10 10 -5 10 -4 1 0-3 10-2 10-1 t, PULSE WIDTH (s) 100 101 FIGURE 4. FORWARD BIAS SAFE OPERATING AREA FIGURE 5. PEAK CURRENT CAPABILITY ©2002 Fairchild Semiconductor Corporation RFD14N05, RFD14N05SM, RFP14N05 Rev. B1 RFD14N05, RFD14N05SM, RFP14N05 Typical Performance Curves 50 I AS, A VA L AN C H E C U R RE NT (A) Unless Otherwise Specified (Continued) 35 VGS = 2 0V 30 ID, D R A IN C U R RE NT (A) 25 20 15 10 5 0 VGS = 5V VGS = 4.5V 0 2 4 6 VDS, DRAIN TO SOURCE VOLTAGE (V) 8 PULSE DURATION = 80 µs DUTY CYCLE = 0.5% MAX VGS = 6V VGS = 10V VGS = 8V TC = 25o C VGS = 7V STARTING TJ = 25o C 10 STARTING T J = 150oC If R = 0 tAV = (L)(IAS )/(1.3*RATED BVDSS - VDD) If R ≠ 0 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS -V DD) +1] 1 0.01 0.1 1 tAV, TIME IN AVALANCHE (ms) 10 NOTE: Refer to Fairchild Application Notes AN9321 and AN9322. FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING FIGURE 7. SATURATION CHARACTERISTICS ID S( ON) , D R A IN TO SO UR C E CU R RE NT (A) 35 30 25 20 15 10 5 0 0 -55 oC 175 oC NO RM A L IZ ED D R A IN TO SO UR C E B R EA KD OW N V OL TA GE PULSE DURATION = 80µ s DUTY CYCLE = 0.5% MAX V DD = 15V 2.0 -25oC ID = 250µ A 1.5 1.0 0.5 2 4 6 8 VGS , GATE TO SOURCE VOLTAGE (V) 10 0 -80 -40 0 40 80 120 160 TJ , JUNCTION TEMPERATURE ( oC) 200 FIGURE 8. TRANSFER CHARACTERISTICS FIGURE 9. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE 2.0 N OR MA L IZ ED DR A IN TO SO UR C E ON RE SIS TA N CE VGS = VDS , ID = 250µA V GS ( TH) , NO RM A L IZ ED G AT E T H RE SH OL D VOL T AG E 1.5 2.5 2.0 PULSE DURATION = 80µ s DUTY CYCLE = 0.5% MAX VGS = 10V, ID = 14A 1.5 1.0 1.0 0.5 0.5 0 -80 -40 0 40 80 120 160 TJ , JUNCTION TEMPERATURE (oC) 200 0 -80 -40 0 40 80 120 160 TJ , JUNCTION TEMPERATURE (oC) 200 FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE FIGURE 11. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE ©2002 Fairchild Semiconductor Corporation RFD14N05, RFD14N05SM, RFP14N05 Rev. B1 RFD14N05, RFD14N05SM, RFP14N05 Typical Performance Curves 700 C ISS 600 C , C AP AC I TA N C E ( pF ) 500 400 C OSS 300 200 100 0 0 5 10 15 20 VDS , DRAIN TO SOURCE VOLTAGE (V) 25 C RSS Unless Otherwise Specified (Continued) VD S , D R AI N T O SOU R CE VO LT A GE (V) V GS , GA TE T O SOU R CE VO LT A GE (V) 60 VDD = BV DSS 45 V DD = B VDSS 7.5 10 VGS = 0 V, f = 1MHz C ISS = CGS + C GD C RSS = C G D C OSS ≈ C DS + CG D 30 0.75 BV DSS 0.50 BV DSS 0.25 BV DSS R L = 3.57Ω I G(REF) = 0 .4mA V GS = 1 0V I G ( REF ) 2 0---------------------I G ( ACT ) I G ( REF ) 8 0---------------------I G ( ACT ) 5.0 15 2.5 0 t, TIME (µ s) 0 NOTE: Refer to Fairchild Application Notes AN7254 and AN7260, FIGURE 13. NORMALIZED SWITCHING WAVEFORMS FOR CONSTANT CURRENT GATE DRIVE FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE Test Circuits and Waveforms VDS BV DSS L VARY t P TO OBTAIN REQUIRED PEAK IAS VGS DUT tP RG IAS VDD tP VDS VDD + 0V I AS 0.01Ω 0 tAV F IGURE 14. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 15. UNCLAMPED ENERGY WAVEFORMS tON V DS VDS VGS RL + tOFF t d(OFF) tr tf 90% td(ON) 90% DUT R GS - VDD 0 10% 10% 90% VGS 0 10% 50% PULSE WIDTH 50% VGS FIGURE 16. SWITCHING TIME TEST CIRCUIT FIGURE 17. RESISTIVE SWITCHING WAVEFORMS ©2002 Fairchild Semiconductor Corporation RFD14N05, RFD14N05SM, RFP14N05 Rev. B1 RFD14N05, RFD14N05SM, RFP14N05 Test Circuits and Waveforms ( Continued) VDS RL VDD VDS Qg(TOT) VGS = 20V V GS + Qg(10) VDD VGS VGS = 2V 0 Qg(TH) IG(REF) 0 VGS = 10V DUT I G(REF) FIGURE 18. GATE CHARGE TEST CIRCUIT FIGURE 19.GATE CHARGE WAVEFORMS ©2002 Fairchild Semiconductor Corporation RFD14N05, RFD14N05SM, RFP14N05 Rev. B1 RFD14N05, RFD14N05SM, RFP14N05 PSPICE Electrical Model .SUBCKT RFP14N05 2 1 3 ; CA 12 8 8.84e-10 CB 15 14 9.34e-10 CIN 6 8 5.2e-10 10 rev 9/12/94 DPLCAP 5 LDRAIN RSCL1 DRAIN 2 DBODY 7 5 DBDMOD DBREAK 5 11 DBKMOD DPLCAP 10 5 DPLCAPMOD EBREAK 11 7 17 18 62.87 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 6 8 1 EVTO 20 6 18 8 1 IT 8 17 1 LDRAIN 2 5 1e-9 LGATE 1 9 4.34e-9 LSOURCE 3 7 3.79e-9 MOS1 16 6 8 8 MOSMOD M = 0.99 MOS2 16 21 8 8 MOSMOD M = 0.01 12 GATE 1 LGATE 9 20 RGATE RSCL2 ESG + EVTO + 18 8 RIN CIN 6 8 VTO 6 + 16 + 51 5 ESCL 51 50 RDRAIN DBREAK 11 EBREAK + 17 18 DBODY - 21 MOS1 MOS2 - 8 RSOURCE 7 LSOURCE 3 SOURCE S1A 13 8 S1B CA + EGS 6 8 S2A 14 13 S2B 13 CB + EDS 5 8 14 IT VBAT + 15 17 RBREAK 18 RVTO 19 RBREAK 17 18 RBKMOD 1 RDRAIN 50 16 RDSMOD 2.2e-3 RGATE 9 20 5.64 RIN 6 8 1e9 RSCL1 5 51 RSCLMOD 1e-6 RSCL2 5 50 1e3 RSOURCE 8 7 RDSMOD 42.3e-3 RVTO 18 19 RVTOMOD 1 S1A S1B S2A S2B 6 12 13 8 S1AMOD 13 12 13 8 S1BMOD 6 15 14 13 S2AMOD 13 15 14 13 S2BMOD - - VBAT 8 19 DC 1 VTO 21 6 0.82 ESCL 51 50 VALUE = {(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)*1e6/50,6))} .MODEL .MODEL .MODEL .MODEL .MODEL .MODEL .MODEL .MODEL .MODEL .MODEL .MODEL .MODEL DBDMOD D (IS = 1.5e-13 RS = 10.9e-3 TRS1 = 2.3e-3 TRS2 = -1.75e-5 CJO = 6.84e-10 TT = 4.2e-8) DBKMOD D (RS = 4.15e-1 TRS1 = 3.73e-3 TRS2 = -3.21e-5) DPLCAPMOD D (CJO = 26.2e-11 IS = 1e-30 N = 10) MOSMOD NMOS (VTO = 3.91 KP = 12.68 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u) RBKMOD RES (TC1 = 7.73e-4 TC2 = 2.12e-6) RDSMOD RES (TC1 = 5.0e-3 TC2 = 2.53e-5) RSCLMOD RES (TC1 = 2.05e-3 TC2 = 1.35e-5) RVTOMOD RES (TC1 = -4.44e-3 TC2 = -6.45e-6) S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -5.29 VOFF= -3.29) S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -3.29 VOFF= -5.29) S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -2.25 VOFF= 2.75) S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 2.75 VOFF= -2.25) .ENDS NOTE: For further discussion of the PSPICE model, consult A N ew PSPICE Sub-circuit for the Power MOSFET Featuring Global Temperature Options ; written by William J. Hepp and C. Frank Wheatley. ©2002 Fairchild Semiconductor Corporation RFD14N05, RFD14N05SM, RFP14N05 Rev. B1 TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACEx™ FACT™ ActiveArray™ FACT Quiet Series™ Bottomless™ FAST CoolFET™ FASTr™ CROSSVOLT™ FRFET™ DOME™ GlobalOptoisolator™ EcoSPARK™ GTO™ E2CMOSTM HiSeC™ EnSignaTM I2C™ Across the board. Around the world.™ The Power Franchise™ Programmable Active Droop™ DISCLAIMER ImpliedDisconnect™ PACMAN™ POP™ ISOPLANAR™ Power247™ LittleFET™ PowerTrench MicroFET™ QFET MicroPak™ QS™ MICROWIRE™ QT Optoelectronics™ MSX™ Quiet Series™ MSXPro™ RapidConfigure™ OCX™ RapidConnect™ OCXPro™ SILENT SWITCHER OPTOLOGIC SMART START™ OPTOPLANAR™ SPM™ Stealth™ SuperSOT™-3 SuperSOT™-6 SuperSOT™-8 SyncFET™ TinyLogic TruTranslation™ UHC™ UltraFET VCX™ FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. 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PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Advance Information Product Status Formative or In Design First Production Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Preliminary No Identification Needed Full Production Obsolete Not In Production Rev. I3