SG5841J_08

SG5841J — Highly Integrated Green-Mode PWM Controller September 2008 SG5841J — Highly Integrated Green-Mode PWM Controller Features Green-Mode PWM Controller Low Startup Current : 14µA Low Operating Current: 4mA Programmable PWM Frequency with Hopping Peak-Current-Mode Control Cycle-by-Cycle Current Limiting Synchronized Slope Compensation Leading-Edge Blanking (LEB) Constant Output Power Limit Totem Pole Output with Soft Driving VDD Over-Voltage Clamping Programmable Over-Temperature Protection (OTP) Internal Open-Loop Protection VDD Under-Voltage Lockout (UVLO) GATE Output Maximum Voltage Clamp:18V Description The highly integrated SG5841/J series of PWM controllers provides several features to enhance the performance of flyback converters. To minimize standby power consumption, a proprietary green-mode function provides off-time modulation to continuously decrease the switching frequency at lightload conditions. This green-mode function enables the power supply to meet international power conservation requirements. To further reduce power consumption, SG5841/J is manufactured using the BiCMOS process. This allows a low startup current, around 14µA, and an operating current of only 4mA. As a result, a large startup resistance can be used. The built-in synchronized slope compensation achieves stable peak-current-mode control. The proprietary internal sawtooth power-limiter ensures a constant output power limit over a wide range of AC input voltages, from 90VAC to 264VAC. SG5841/J provides many protections. In addition to cycle-by-cycle current limiting, the internal open-loop protection circuit ensures safety should an open-loop or output-short-circuit failure occur. PWM output is disabled until VDD drops below the UVLO lower limit, then the controller restarts. An external NTC thermistor can be applied for over-temperature protection. SG5841/J is available in an 8-pin DIP or SOP package. Applications General-purpose, switch-mode, power supplies and flyback power converters, including: Power Adapters Open-Frame SMPS Ordering Information Part Number SG5841JSZ SG5841JSY SG5841JDZ SG5841SZ SG5841SY SG5841DZ Operating Temperature Range -40 to +125°C -40 to +125°C -40 to +125°C -40 to +125°C -40 to +125°C -40 to +125°C Frequency Hopping Yes Yes Yes No No No Eco Status RoHS Green RoHS RoHS Green RoHS Package 8-Pin Small Outline Package (SOP) 8-Pin Small Outline Package (SOP) 8-Pin Dual Inline Package (DIP) 8-Pin Small Outline Package (SOP) 8-Pin Small Outline Package (SOP) 8-Pin Dual Inline Package (DIP) For Fairchild’s definition of “green” Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html. © 2006 Fairchild Semiconductor Corporation SG5841J • Rev. 1.3.3 www.fairchildsemi.com SG5841J — Highly Integrated Green-Mode PWM Controller Typical Application Figure 1. Application Diagram Block Diagram Figure 2. Block Diagram © 2006 Fairchild Semiconductor Corporation SG5841J • Rev. 1.3.3 www.fairchildsemi.com 2 SG5841J — Highly Integrated Green-Mode PWM Controller Marking Information SG5841HTP XXXX XXXXYWW H: J = with Frequency Hopping Null = without Frequency Hopping T: D = DIP, S = SOP P: Z = Lead Free Null = regular package XX XXXXXX : Wafer Lot Y: Year; WW : Week V: Assembly Location ZXYTT 5841/J TPM F: Fairchild Logo Z:Plant Code X:1 Digit Year Code Y:1 Digit Week Code TT:2 Digit Die Run Code T: Package Type (D:DIP, S:SOP) P:Y = Green Package M:Manufacturing Flow Code Figure 3. Top Mark © 2006 Fairchild Semiconductor Corporation SG5841J • Rev. 1.3.3 www.fairchildsemi.com 3 SG5841J — Highly Integrated Green-Mode PWM Controller Pin Configuration GND FB VIN RI GATE VDD SENSE RT Figure 4. Pin Configuration Pin Definitions Pin # 1 2 Name GND FB Function Ground Feedback Ground. Description The signal from the external compensation circuit is fed into this pin. The PWM duty cycle is determined in response to the signal from this pin and the currentsense signal from pin 6. If FB voltage exceeds the threshold, the internal protection circuit disables PWM output after a predetermined delay time. 3 VIN For startup, this pin is pulled HIGH to the rectified line input via a resistor. Since Startup Input the startup current requirement is very small, a large startup resistance is used to minimize power loss. Reference Setting A resistor connected from the RI to GND provides a constant current source. This determines the center PWM frequency. Increasing the resistance reduces PWM frequency. Using a 26KΩ resistor results in a 65KHz center PWM frequency. 4 RI 5 RT For over-temperature protection. An external NTC thermistor is connected from Temperature this pin to the GND pin. The impedance of the NTC decreases at high temperatures. Once the voltage of the RT pin drops below a fixed limit, PWM Detection output is disabled. Current Sense Power Supply Driver Output Current sense. The sensed voltage is used for peak-current-mode control and cycle-by-cycle current limiting. Power supply. If VDD exceeds a threshold, the internal protection circuit disables PWM output. The totem-pole output driver for the power MOSFET, which is internally clamped below 18V. 6 7 8 SENSE VDD GATE © 2006 Fairchild Semiconductor Corporation SG5841J • Rev. 1.3.3 www.fairchildsemi.com 4 SG5841J — Highly Integrated Green-Mode PWM Controller Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. All voltage values, except differential voltages, are given with respect to GND pin. Symbol VDD VIN VFB VSENSE VRT VRI PD ΘJA ΘJC TJ TSTG TL ESD Supply Voltage Input Terminal Parameter Min. Max. 30 30 Unit V V V V V V mW °C/W °C/W °C °C °C kV V Input Voltage to FB Pin Input Voltage to SENSE Pin Input Voltage to RT Pin Input Voltage to RI Pin Power Dissipation (TA < 50°C ) Thermal Resistance (Junction-to-Air) Thermal Resistance (Junction-to-Case) Operating Junction Temperature Storage Temperature Range Lead Temperature (Wave Soldering or Infrared, 10 Seconds) Human Body Model, JESD22-A114 Charged Device Model, JESD22-C101 DIP SOP DIP SOP DIP SOP -0.3 -0.3 -0.3 -0.3 7.0 7.0 7.0 7.0 800 400 82.5 141 59.7 80.8 -40 -55 +125 +150 260 3 250 Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol TA Parameter Operating Ambient Temperatures Min. -20 Max. +85 Unit °C © 2006 Fairchild Semiconductor Corporation SG5841J • Rev. 1.3.3 www.fairchildsemi.com 5 SG5841J — Highly Integrated Green-Mode PWM Controller Electrical Characteristics VDD = 15V, TA = 25°C, unless otherwise noted. Symbol VDD Section VDD-OP VDD-ON VDD-OFF IDD-ST IDD-OP VDD-CLAMP tD-VDDCLAMP Parameter Continuously Operating Voltage Start Threshold Voltage Minimum Operating Voltage Startup Current Operating Supply Current VDD Over-Voltage-Clamping Level VDD Over-Voltage-Clamping Debounce Time RI Operating Range Maximum RI Value for Protection Minimum RI Value for Protection Normal PWM Frequency Center Frequency Hopping Range Conditions Min. Typ. Max. 24.7 Units V V V µA mA V 15 9 VDD=VDD-ON–0.16V VDD=15V, RI=26KΩ, GATE=OPEN 28 RI=26KΩ 50 16 10 14 4 29 100 17 11 30 5 200 µs RI Section RINOR RIMAX RIMIN 15.5 230 10 RI=26KΩ RI=26KΩ (SG5841J only) RI=26KΩ (SG5841J only) RI=26KΩ VDD=11.5V to 24.7V TA=-20 to +85°C 62 ±3.7 3.9 18 36.0 KΩ KΩ KΩ Oscillator Section 65 ±4.2 4.4 22 68 ±4.7 4.9 25 5 5 fOSC tHOP fOSC-G fDV fDT KHz ms KHz % % Hopping Period Green-Mode Frequency Frequency Variation vs. VDD Deviation Frequency Variation vs. Temperature Deviation FB Input to Current Comparator Attenuation Input Impedance FB Output High Voltage FB Open-Loop Trigger Level Delay Time of FB Pin Open-Loop Protection Green-Mode Entry FB Voltage Green-Mode Ending FB Voltage Feedback Input Section AV ZFB VFB-OPEN VFB-OLP tD-OLP VFB-N VFB-G 1/3.75 4 FB pin open 5 4.2 RI=26KΩ RI=26KΩ RI=26KΩ 26 1.9 6 4.5 29 2.1 VFB-N-0.5 4.8 32 2.3 1/3.20 1/2.75 7 V/V KΩ V V ms V V fOSC fOSC -GREEN Figure 5. PWM Frequency © 2006 Fairchild Semiconductor Corporation SG5841J • Rev. 1.3.3 www.fairchildsemi.com 6 SG5841J — Highly Integrated Green-Mode PWM Controller Electrical Characteristics (Continued) VDD = 15V, TA = 25°C, unless otherwise noted. Symbol ZSENSE VSTHFL VSTHVA tPD tLEB Parameter Input Impedance Current Limit Flatten Threshold Voltage Current Limit Valley Threshold Voltage Propagation Delay to GATE Output Leading-Edge Blanking Time Conditions Min. Typ. 12 Max. Unit KΩ Current-Sense Section 0.85 VSTHFL–VSTHVA RI=26KΩ RI=26KΩ 200 0.90 0.22 150 270 0.95 V V 200 350 ns ns GATE Section DCYMAX VGATE-L VGATE-H tr tf IO VGATECLAMP Maximum Duty Cycle Output Voltage Low Output Voltage High Rising Time Falling Time Peak Output Current Gate Output Clamping Voltage VDD=15V, IO=50mA VDD=12.5V, IO=50mA VDD=15V, CL=1nF VDD=15V, CL=1nF VDD=15V, GATE=6V VDD=24.7V 60 7.5 150 30 230 65 70 1.5 % V V ns ns mA 250 50 350 90 18 19 V RT Section IRT VRTTH VRT-RLS tD-OTP Output Current of RT Pin Trigger Voltage for OverTemperature Protection OTP Release Voltage Over-Temperature Debounce RI=26KΩ 60 RI=26KΩ 92 0.585 100 0.620 VRTTH +0.03 100 140 108 0.655 µA V V µs © 2006 Fairchild Semiconductor Corporation SG5841J • Rev. 1.3.3 www.fairchildsemi.com 7 SG5841J — Highly Integrated Green-Mode PWM Controller Typical Performance Characteristics 30 26 5. 0 4. 5 IDD-OP (mA) IDD-ST (µA) 22 18 14 10 -40 - 25 10 5 20 35 50 65 80 95 110 125 4. 0 3. 5 3. 0 2. 5 - 40 -25 -10 5 20 35 50 65 80 95 110 125 Temperature (°C) Temperature (°C) Figure 6. Startup Current (IDD-ST) vs. Temperature Figure 7. Operating Supply Current (IDD-OP) vs. Temperature 15 17. 0 12 9 16. 5 IDD-OP (mA) VDD-ON (V) 16. 0 6 3 15. 5 0 11 13 15 17 19 21 23 25 27 29 15. 0 - 40 -25 -10 5 20 35 50 65 80 95 110 125 VDD Voltage (V) Temperature (°C) Figure 8. Operating Current (IDD-OP) vs. VDD Voltage Figure 9. Start Threshold Voltage (VDD-ON) vs. Temperature 11. 0 68 67 66 10. 5 VDD-OFF (V) 10. 0 fOSC (KHz) - 40 -25 -10 5 20 35 50 65 80 95 110 125 65 64 63 9. 5 9. 0 62 -40 -25 -10 5 20 35 50 65 80 95 110 125 Temperature (°C) Temperature (°C) Figure 10. Minimum Operating Voltage (VDD-ON) vs. Temperature Figure 11. PWM Frequency (fOSC) vs. Temperature © 2006 Fairchild Semiconductor Corporation SG5841J • Rev. 1.3.3 www.fairchildsemi.com 8 SG5841J — Highly Integrated Green-Mode PWM Controller Typical Performance Characteristics (Continued) 70 68 DCY MAX (%) 66 64 62 60 -40 -25 -10 5 20 35 50 65 80 95 110 125 Temperature (°C) Figure 12. Maximum Duty Cycle (DCYMAX) vs. Temperature 0.66 0.65 0.64 V (RTTH) (V) 0.63 0.62 0.61 0.60 0.59 0 .58 -40 -25 -10 5 20 35 50 65 80 95 110 12 5 Temperature (°C) Figure 13. Trigger Voltage for Over-Temperature Protection VRTTH vs. Temperature 108 104 IRT (µA) 100 96 92 -40 - 25 -10 5 20 35 50 65 80 95 110 125 Temperature (°C) Figure 14. Output Current of RT Pin (IRT) vs. Temperature © 2006 Fairchild Semiconductor Corporation SG5841J • Rev. 1.3.3 www.fairchildsemi.com 9 SG5841J — Highly Integrated Green-Mode PWM Controller Functional Description Startup Current Typical startup current is only 14µA, which allows a high-resistance and low-wattage startup resistor to minimize power loss. For an AC/DC adapter with universal input range, a 1.5MΩ, 0.25W startup resistor and a 10µF/25V VDD hold-up capacitor are enough for this application. Leading-Edge Blanking (LEB) Each time the power MOSFET is switched on, a turn-on spike occurs at the sense-resistor. To avoid premature termination of the switching pulse, a leading-edge blanking time is built in. During this blanking period, the current-limit comparator is disabled and cannot switch off the gate drive. Operating Current Operating current is around 4mA. The low operating current enables better efficiency and reduces the requirement of VDD hold-up capacitance. Under-Voltage Lockout (UVLO) The turn-on and turn-off thresholds are fixed internally at 16V and 10V. During startup, the hold-up capacitor must be charged to 16V through the startup resistor to enable the IC. The hold-up capacitor continues to supply VDD before the energy can be delivered from auxiliary winding of the main transformer. VDD must not drop below 10V during this startup process. This UVLO hysteresis window ensures that hold-up capacitor is adequate to supply VDD during startup. Green-Mode Operation The proprietary green-mode function provides off-time modulation to continuously decrease the PWM frequency under light-load conditions. To avoid acoustic noise problems, the minimum PWM frequency is set above 22KHz. Green mode dramatically reduces power consumption under light-load and zero-load conditions. Power supplies using a SG5841/J controller can meet restrictive international regulations regarding standby power consumption. Gate Output / Soft Driving The SG5841/J BiCMOS output stage is a fast totempole gate driver. Cross conduction has been avoided to minimize heat dissipation, increase efficiency, and enhance reliability. The output driver is clamped by an internal 18V Zener diode to protect power MOSFET transistors against undesirable gate over-voltage. A soft driving waveform is implemented to minimize EMI. Oscillator Operation A resistor connected from the RI pin to the GND pin generates a constant current source for the SG5841/J controller. This current is used to determine the center PWM frequency. Increasing the resistance reduces PWM frequency. Using a 26KΩ resistor, RI, results in a corresponding 65KHz PWM frequency. The relationship between RI and the switching frequency is: Built-in Slope Compensation The sensed voltage across the current-sense resistor is used for peak-current-mode control and pulse-by-pulse current limiting. Built-in slope compensation improves stability or prevents sub-harmonic oscillation. SG5841/J inserts a synchronized, positive-going ramp at every switching cycle. fPWM = 1690 (KHz) RI (KΩ) (1) The range of the PWM oscillation frequency is designed as 47KHz ~ 109KHz. SG5841J also integrates a frequency hopping function internally. The frequency variation ranges from around 62KHz to 68KHz for a center frequency of 65KHz. The frequency-hopping function helps reduce EMI emission of a power supply with minimum line filters. Constant Output Power Limit W hen the SENSE voltage across the sense resistor, RS, reaches the threshold voltage, around 0.85V, the output GATE drive is turned off after delay, tPD. This delay introduces additional current, proportional to tPD • VIN / LP. The delay is nearly constant, regardless of the input voltage VIN. Higher input voltage results in larger additional current and the output power limit is higher than under low-input line voltage. To compensate this variation for a wide AC input range, a sawtooth powerlimiter (saw limiter) is designed to solve the unequal power-limit problem. The saw limiter is designed as a positive ramp signal (Vlimit_ramp) and fed to the inverting input of the OCP comparator. This results in a lower current limit at high-line inputs than at low-line inputs. Current Sensing / PWM Current Limiting Peak-current-mode control is utilized in to regulate output voltage and provide pulse-by-pulse current limiting. The switch current is detected by a sense resistor into the SENSE pin. The PWM duty cycle is determined by this current-sense signal and the feedback voltage. When the voltage on the SENSE pin reaches around VCOMP = (VFB–1.0)/3.2, a switch cycle is terminated immediately. VCOMP is internally clamped to a variable voltage around 0.85V for output power limit. VDD Over-Voltage Clamping VDD over-voltage clamping prevents damage due to abnormal conditions. If VDD voltage is over the VDD overvoltage clamping voltage (VDD-CLAMP) and lasts for tDVDDCLAMP, the PWM pulses are disabled until the VDD drops below the VDD over-voltage clamping voltage. © 2006 Fairchild Semiconductor Corporation SG5841J • Rev. 1.3.3 www.fairchildsemi.com 10 SG5841J — Highly Integrated Green-Mode PWM Controller Thermal Protection An NTC thermistor RNTC in series with a resistor RA can be connected from the RT pin to ground. A constant current IRT is output from pin RT. The voltage on the RT pin can be expressed as VRT = IRT × (RNTC + RA), in which IRT = 2 x (1.3V / RI). At high ambient temperature, RNTC is smaller, such that VRT decreases. When VRT is less than 0.62V, the PWM is completely turned off. When VDD goes below the turn-off threshold (e.g. 10V) the controller totally shuts down. VDD is charged up to the turn-on threshold voltage of 16V through the startup resistor until PWM output is restarted. This protection remains activated as long as the overloading condition persists. This prevents the power supply from overheating due to overloading conditions. Limited Power Control The FB voltage increases every time the output of the power supply is shorted or overloaded. If the FB voltage remains higher than a built-in threshold for longer than tD-OLP, PWM output is turned off. As PWM output is turned off, the supply voltage VDD begins decreasing. t D - OLP (ms) Noise Immunity Noise on the current-sense or control signal may cause significant pulse-width jitter, particularly in the continuous-conduction mode. Slope compensation helps alleviate this problem. Good placement and layout practices should be followed. Avoiding long PCB traces and component leads, locating compensation and filter components near SG5841/J, and increasing power MOS gate resistance improve performance. = 1 . 115 × RI(K Ω ) (2) © 2006 Fairchild Semiconductor Corporation SG5841J • Rev. 1.3.3 www.fairchildsemi.com 11 SG5841J — Highly Integrated Green-Mode PWM Controller Reference Circuit 2 CN1 1 2 3 F1 2 4 L1 VZ1 Q1 1 2 4 C1 R2 C4 1 3 1 3 TR 1 3 L2 C2 4 2 1 + R5 C3 1 R3 2 2 D3 + C8 R6 C6 R4 C7 + T1 3 2 1 L3 2 1 Vo+ D1 R1 BD1 C5 1 1 1 D2 2 2 D4 2 1 2 3 4 R9 GND FB VIN RI SG5841/J GATE VDD SENSE RT 8 7 6 5 R16 1 R12 3 1 U1 Q2 R11 R10 C11 THER2 C9 2 + R8 1 4 U2 C12 R13 3 K2 C10 R14 R15 A 1 U3 R VO+ Figure 15. Reference Circuit Reference Q2 R1, R2 R3 R4 R5, R7 R6 R8 R9 R10 R11 R12 R13 R14 R15 R16 THER2 T1 U1 U2 U3 VZ1 MOS 7A/600V R 1MΩ 1/4W R 100KW 1/2W R 47Ω 1/4W R 750KΩ 1/4W R 2KΩ 1/8W R 0.3Ω 2W R 33KΩ 1/8W R 4.7KΩ 1/8W 1% R 470Ω 1/8W R 0Ω 1/8W R 4.7KΩ 1/8W R 154KΩ 1/8W R 39KΩ 1/8W R 100Ω 1/8W Thermistor TTC104 Transformer (600µH-PQ2620) IC SG5841/J IC PC817 IC TL431 VZ 9G BOM Reference BD1 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 D1 D2 D3 D4 F1 L1 L2 L3 Q1 BD 4A/600V XC 0.68µF/300V XC 0.1µF/300V CC 0.01µF/500V EC 120µ/400V YC 222p/250V CC 1000pF/100V EC 1000µF/25V EC 470µF/25V EC 10µF/50V CC 222pF/50V CC 470pF/50V CC 102pF/50V (Option) LED Diode BYV95C TVS P6KE16A Diode FR103 FUSE 4A/250V Choke (900µH) Choke (10mH) Inductor (2µH) Diode 20A/100V Component Component © 2006 Fairchild Semiconductor Corporation SG5841J • Rev. 1.3.3 2 R7 www.fairchildsemi.com 12 SG5841J — Highly Integrated Green-Mode PWM Controller Physical Dimensions 5.00 4.80 3.81 8 5 A 0.65 B 6.20 5.80 4.00 3.80 1 4 1.75 5.60 PIN ONE INDICATOR (0.33) 1.27 0.25 M CBA 1.27 LAND PATTERN RECOMMENDATION 0.25 0.10 1.75 MAX C 0.10 0.51 0.33 0.50 x 45° 0.25 C SEE DETAIL A 0.25 0.19 OPTION A - BEVEL EDGE R0.10 R0.10 GAGE PLANE 0.36 OPTION B - NO BEVEL EDGE NOTES: UNLESS OTHERWISE SPECIFIED A) THIS PACKAGE CONFORMS TO JEDEC MS-012, VARIATION AA, ISSUE C, B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE MOLD FLASH OR BURRS. D) LANDPATTERN STANDARD: SOIC127P600X175-8M. E) DRAWING FILENAME: M08AREV13 8° 0° 0.90 0.406 SEATING PLANE (1.04) DETAIL A SCALE: 2:1 Figure 16. 8-Pin Small Outline Package (SOP) Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. © 2006 Fairchild Semiconductor Corporation SG5841J • Rev. 1.3.3 www.fairchildsemi.com 13 SG5841J — Highly Integrated Green-Mode PWM Controller Physical Dimensions (Continued) 9.83 9.00 6.67 6.096 8.255 7.61 5.08 MAX 3.683 3.20 7.62 0.33 MIN (0.56) 2.54 3.60 3.00 0.56 0.355 1.65 1.27 7.62 0.356 0.20 9.957 7.87 NOTES: UNLESS OTHERWISE SPECIFIED A) THIS PACKAGE CONFORMS TO JEDEC MS-001 VARIATION BA B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH, AND TIE BAR EXTRUSIONS. D) DIMENSIONS AND TOLERANCES PER ASME Y14.5M-1994 E) DRAWING FILENAME AND REVSION: MKT-N08FREV2. Figure 17. 8-Pin Dual Inline Package (DIP) Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. © 2006 Fairchild Semiconductor Corporation SG5841J • Rev. 1.3.3 www.fairchildsemi.com 14 SG5841J — Highly Integrated Green-Mode PWM Controller © 2006 Fairchild Semiconductor Corporation SG5841J • Rev. 1.3.3 www.fairchildsemi.com 15