FD2000

August 2010 FD2000 (LCD Display Driver) USER’S MANUAL REVISION 1.0 FD2000 Rev1.0 CONTENTS 1. OVERVIEW ............................................................................................................................................................ 4 2. FEATURES ............................................................................................................................................................. 4 3. BLOCK DIAGRAM .................................................................................................................................................. 5 4. PIN ASSIGNMENTS............................................................................................................................................... 6 4.1. 80-MQFP-1420 ................................................................................................................................................ 6 4.2. 80-LQFP-1212 ................................................................................................................................................. 7 5. PIN DESCRIPTIONS .............................................................................................................................................. 8 6. BLOCK FUNCTIONS.............................................................................................................................................. 9 6.1. AC (Address counter)....................................................................................................................................... 9 6.2. DCRAM (Data control RAM) ............................................................................................................................ 9 6.3. ADRAM (Additional data RaM) ...................................................................................................................... 10 6.4. CGROM (Character generator ROM) ............................................................................................................ 11 6.5. CGRAM (Character generator RAM) ............................................................................................................. 11 7. RESET FUNCTION ............................................................................................................................................. 12 8. SERIAL DATA TRANSFER FORMAT ................................................................................................................. 13 9. INSTRUCTION TABLE ......................................................................................................................................... 14 10. DETAILED INSTRUCTION DESCRIPTIONS .................................................................................................... 15 10.1. Set display technique ― Sets the display technique ................................................................................... 15 10.2. Display on/off control ― Turns the display on or off .................................................................................... 15 10.3. Display shift ― Shifts the display ................................................................................................................. 16 10.4. Set AC address ― Specifies the DCRAM and ADRAM address for AC ..................................................... 17 10.5. DCRAM data write ― Specifies the DCRAM address and stores data at that address .............................. 17 10.6. ADRAM data write ― Specifies the ADRAM address and stores data at that address .............................. 19 10.7. CGRAM data write ― Specifies the CGRAM address and stores data at that address ............................. 21 11. NOTES ON THE POWER ON AND POWER OFF SEQUENCES .................................................................... 22 12. LCD DRIVE TECHNIQUE .................................................................................................................................. 23 12.1. 1/8 duty, 1/4 bias drive technique ................................................................................................................ 23 12.2. 1/9 duty, 1/4 bias drive technique ................................................................................................................ 24 12.3. 1/10 duty, 1/4 bias drive technique .............................................................................................................. 25 13. SAMPLE APPLICATION CIRCUIT ..................................................................................................................... 26 13.1. 1/8 duty, 1/4 bias drive (For use with normal panels) .................................................................................. 26 13.2. 1/8 duty, 1/4 bias drive (For use with large panels) ..................................................................................... 26 13.3. 1/9 duty, 1/4 bias drive (For use with normal panels) .................................................................................. 27 13.4. 1/9 duty, 1/4 bias drive (For use with large panels) ..................................................................................... 27 13.5. 1/10 duty, 1/4 bias drive (For use with normal panels) ................................................................................ 28 13.6. 1/10 duty, 1/4 bias drive (For use with large panels) ................................................................................... 28 2/ 37 FD2000 Rev1.0 14. SAMPLE CORRESPONDENCE BETWEEN INSTRUCTIONS AND THE DISPLAY ........................................ 29 15. FD2000 CHARACTER FONT (STANDARD) ..................................................................................................... 31 16. ELECTRICAL CHARACTERISTICS .................................................................................................................. 32 16.1. Absolute maximum ratings ........................................................................................................................... 32 16.2. Allowable operating ranges .......................................................................................................................... 33 16.3. Electrical characteristics in the allowable operating ranges ........................................................................ 34 17. PACKAGE DIMENSIONS................................................................................................................................... 36 17.1. 80-MQFP-1420 ............................................................................................................................................ 36 17.2. 80-LQFP-1212 ............................................................................................................................................. 37 3/ 37 FD2000 1. OVERVIEW Rev1.0 The FD2000 is 1/8 to 1/10 duty dot matrix LCD display controller/drivers that supports the display of characters, numbers, and symbols. In addition to generating dot matrix LCD drive signals based on data transferred serially from a microcontroller, the FD2000 also provide on-chip character display ROM and RAM to allow display systems to be implemented easily. 2. FEATURES • Controls and drives a 5 x 7, 5 x 8, or 5 x 9 dot matrix LCD. • Supports accessory display segment drive (up to 60 segments) • Display technique 1/8 duty 1/4 bias drive (5 x 7 dots) 1/9 duty 1/4 bias drive (5 x 8 dots) 1/10 duty 1/4 bias drive (5 x 9 dots) • Display digits 12 digits x 1 line (5 x 7 dots) 11 digits x 1 line (5 x 8 or 5 x 9 dots) • Display control memory CGROM: 240 characters (5 x 7, 5 x 8, or 5 x 9 dots) CGRAM: 16 characters (5 x 7, 5 x 8, or 5 x 9 dots) ADRAM: 12 x 5 bits DCRAM: 48 x 8 bits • Instruction function Display on/off control Display shift function • Provides a backup function based on low power modes • Serial data input support • Independent LCD drive block power supply VLCD • Provides a RESETB pin for LSI internal initialization • RC oscillator circuit 4/ 37 FD2000 3. BLOCK DIAGRAM Rev1.0 5/ 37 FD2000 4. PIN ASSIGNMENTS 4.1. 80-MQFP-1420 Rev1.0 COM4 COM3 COM2 COM1 VDD VLCD VLCD1 VLCD2 VLCD3 VSS OSCO OSCI RESETB CE CL DI 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 S40 S39 S38 S37 S36 S35 S34 S33 S32 S31 S30 S29 S28 S27 S26 S25 FD2000 (80-MQFP-1420) 6/ 37 FD2000 4.2. 80-LQFP-1212 S3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 58 59 60 COM7 COM8 S60/COM9 S59/COM10 S58 S57 S56 S55 S54 S53 S52 S51 S50 S49 S48 S47 S46 S45 S44 S43 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 Rev1.0 7/ 37 FD2000 5. PIN DESCRIPTIONS Pin Names S1-S58 Pin No. 1-58 (79,80, 1-56) 59(57) 60(58) 68-61 (66-59) 76(74) 75(73) 78(76) 79(77) 80(78) 77(75) Reset signal input. • W hen RESETB is low (VSS): • Display off S1 to S58 = “L” (VSS). S59/COM10 and S60/COM9 = “L” (VSS). COM1 to COM8 = “L” (VSS). • Serial data transfer is disabled. • The OSCI/OSCO pin oscillator is stopped. • W hen RESETB is high (VDD): • Display on after a “display on/off control” (display on state setting) instruction is executed. • Serial data transfers are enabled. • The OSCI/OSCO pin oscillator operates. VLCD1 VLCD2 VLCD3 VDD VLCD VSS 71(69) 72(70) 73(71) 69(67) 70(68) 74(72) Used for applying the LCD drive 3/4 bias voltage externally. Used for applying the LCD drive 2/4 bias voltage externally. Used for applying the LCD drive 1/4 bias voltage externally. Logic block power supply connection. Provide a voltage of between 2.7 and 6.0 V. LCD driver block power supply connection. Provide a voltage of between 4.5 and 10.0 V. Power supply connection. Connect to ground. I I I L I Common driver outputs. Oscillator connections. An oscillator circuit is formed by connecting an external resistor and capacitor at these pins. Serial data transfer inputs. These pins are connected to the microcontroller. Chip enable Synchronization clock Transfer data H O I O I I I Pin Description Segment driver outputs. The S59/COM10 and S60/COM9 pins can be used as common driver outputs under the “set display technique” instruction. Active I/O Rev1.0 Handling when unused - O Open S59/COM10 S60/COM9 COM1-COM8 OSCI OSCO CE CL DI RESETB Open GND Open GND GND Open Open Open - NOTE: Parentheses indicate pin number for 80-LQFP-1212 package. 8/ 37 FD2000 6. BLOCK FUNCTIONS 6.1. AC (ADDRESS COUNTER) AC is a counter that provides the addresses used for DCRAM and ADRAM. The address is automatically modified internally, and the LCD display state is retained. Rev1.0 6.2. DCRAM (DATA CONTROL RAM) DCRAM is RAM that is used to store display data expressed as 8-bit character codes. (These character codes are converted to 5 x 7, 5 x 8, or 5 x 9 dot matrix character patterns using CGROM or CGRAM.) DCRAM has a capacity of 48 x 8 bits, and can hold 48 characters. The table below lists the correspondence between the 6-bit DCRAM address loaded into AC and the display position on the LCD panel. − W hen the DCRAM address loaded into AC is 00H. Display digit DCRAM address(HEX) 1 00 2 01 3 02 4 03 5 04 6 05 7 06 8 07 9 08 10 09 11 0A 12 0B However, when the display shift is performed by specifying MDATA, the DCRAM address shifts as shown below. Display digit DCRAM address(HEX) Display digit DCRAM address(HEX) 1 01 1 2F 2 02 2 00 3 03 3 01 4 04 4 02 5 05 5 03 6 06 6 04 7 07 7 05 8 08 8 06 9 09 9 07 10 0A 10 08 11 0B 11 09 12 0C 12 0A (Right shift) (Left shift) NOTE: The DCRAM addresses are expressed in hexadecimal. LSB DA0 ← MSB DA5 DCRAM address DA1 DA2 DA3 → DA4 HEX ← HEX → − Example: W hen the DCRAM address is 2EH. LSB DA0 0 DA1 1 DA2 1 DA3 1 DA4 0 MSB DA5 1 NOTE: 5 x 7 dots ... 12-digit display 5 x 8 dots ... 12-digit display 5 x 9 dots ... 12-digit display 5 x 7 dots 4 x 8 dots 3 x 9 dots 9/ 37 FD2000 6.3. ADRAM (ADDITIONAL DATA RAM) Rev1.0 ADRAM is RAM used to store the ADATA display data. ADRAM has a capacity of 12 x 5 bits, and the stored display data is displayed directly without the use of CGROM or CGRAM. The table below lists the correspondence between the 4-bit ADRAM address loaded into AC and the display position on the LCD panel. − W hen the ADRAM address loaded into AC is 0H. (Number of digit displayed: 12) Display digit ADRAM address(HEX) 1 0 2 1 3 2 4 3 5 4 6 5 7 6 8 7 9 8 10 9 11 A 12 B However, when the display shift is performed by specifying ADATA, the ADRAM address shifts as shown below. Display digit ADRAM address(HEX) Display digit ADRAM address(HEX) 1 1 1 B 2 2 2 0 3 3 3 1 4 4 4 2 5 5 5 3 6 6 6 4 7 7 7 5 8 8 8 6 9 9 9 7 10 A 10 8 11 B 11 9 12 0 12 A (Right shift) (Left shift) NOTE: The ADRAM addresses are expressed in hexadecimal. LSB RA0 ← MSB RA3 → ADRAM address RA1 RA2 HEX − Example: W hen the ADRAM address is AH. LSB RA0 0 RA1 1 RA2 0 MSB RA3 1 NOTE: 5 x 7 dots ... 12-digit display 5 dots 5 x 8 dots ... 12-digit display 4 dots 5 x 9 dots ... 12-digit display 3 dots 10/ 37 FD2000 6.4. CGROM (CHARACTER GENERATOR ROM) Rev1.0 CGROM is ROM used to generate the 240 kinds of 5 x 7, 5 x 8, or 5 x 9 dot matrix character patterns from the 8bit character codes. CGROM has a capacity of 240 x 45 bits. When a character code is written to DCRAM, the character pattern stored in CGROM corresponding to the character code is displayed at the position on the LCD corresponding to the DCRAM address loaded into AC. 6.5. CGRAM (CHARACTER GENERATOR RAM) CGRAM is RAM to which user programs can freely write arbitrary character patterns. Up to 16 kinds of 5 x 7, 5 x 8, or 5 x 9 dot matrix character patterns can be stored. CGRAM has a capacity of 16 x 45 bits. 11/ 37 FD2000 7. RESET FUNCTION Rev1.0 The FD2000 is reset when a low level is applied to the RESETB pin at power on and, in normal mode. On a reset the FD2000 create a display with all LCD panels turned off. However, after a reset applications must set the contents of DCRAM, ADRAM, and CGRAM before turning on display with a “display on/off control” instruction since the contents of these memories are undefined. That is, applications must execute the following instructions. − Set display technique − DCRAM data write − ADRAM data write (If ADRAM is used.) − CGRAM data write (If CGRAM is used.) − Set AC address After executing the above instructions, applications must turn on the display with a “display on/off control” instruction. Note that when applications turn off in the normal mode, applications must turn off the display with a “display on/off control” instruction. (See the detailed instruction descriptions.) 12/ 37 FD2000 8. SERIAL DATA TRANSFER FORMAT − W hen CL is stopped at the low level Rev1.0 − W hen CL is stopped at the high level − Address: 47H − D0 to D63: Instruction data The data is acquired on the rising edge of the CL signal and latched on the falling edge of the CE signal. When transferring instruction data from the microcontroller, applications must assure that the time from the transfer of one set of instruction data until the next instruction data transfer is significantly longer than the instruction execution time. 13/ 37 9. INSTRUCTION TABLE D40 D41 D42 D43 D44 D45 D46 DT1 DT2 DG1 DG2 DG3 DG4 DG5 DG6 DG7 DG8 DG9 DG10 DG11 DG12 M DA0 DA1 DA2 DA3 DA4 DA5 AC0 AC1 AC2 AC3 AC4 AC5 AC6 AC7 DA0 DA1 DA2 DA3 DA4 DA5 AD1 AD2 AD3 AD4 AD5 X X X CA0 CA1 CA2 CA3 CA4 CA5 CA6 CA7 X X X X 0 X X X RA0 RA1 RA2 RA3 X X X X IM X X X 0 1 1 X X IM X X X 0 1 0 1 1 X X RA0 RA1 RA2 RA3 0 1 0 0 1 0 1 A R/L X 0 0 1 1 X X X X M A SC BU 0 0 1 0 0us/27us 27us 27us 27us 27us 27us NOTE4 FD2000 Instruction X X 0 0 0 1 0uS D0 D1 … D39 D47 D48 D49 D50 D51 D52 D53 D54 D55 D56 D57 D58 D59 D60 D61 D62 D63 Execution time NOTE3 Set display technique Display on/off control Display shift Set AC address DCRAM data write NOTE1 ADRAM data write NOTE2 CGRAM data write CD1 CD2 … CD40 CD41 CD42 CD43 CD44 CD45 X: don’t care NOTES: 1. The data format differs when the “DCRAM data write” instruction is executed in the increment mode (IM = 1). (See detailed instruction descriptions .) 2. The data format differs when the “ADRAM data write” instruction is executed in the increment mode (IM = 1). (See detailed instruction descriptions.) 3. The execution times listed here apply when fosc = 300 kHz. The execution times differ when the oscillator frequency fosc differs. Example: When fosc = 210 kHz 300 27 μs x —— = 39 μs 210 4. When the power saving mode (BU = 1) is set, the execution time is 27 μs (when fosc = 300 kHz). Rev1.0 14/ 37 FD2000 10. DETAILED INSTRUCTION DESCRIPTIONS 10.1. SET DISPLAY TECHNIQUE ― Sets the display technique Code D56 DT1 D57 DT2 D58 X D59 X D60 0 D61 0 D62 0 D63 1 Rev1.0 X: don’t care 10.1.1. DT1, DT2: Setting the display technique DT1 0 1 0 DT2 0 0 1 Display technique 1/8 duty, 1/4 bias drive 1/9 duty, 1/4 bias drive 1/10 duty, 1/4 bias drive S60 COM9 COM9 Output pins S60/COM9 S59/COM10 S59 S59 COM10 10.2. DISPLAY ON/OFF CONTROL ― Turns the display on or off Code D40 D41 D42 D43 D44 D45 D46 D47 D48 D49 D50 D51 D52 D53 D54 D55 D56 D57 D58 D59 D60 D61 D62 X X X X M A SC BU 0 0 1 D63 0 DG1 DG2 DG3 DG4 DG5 DG6 DG7 DG8 DG9 DG10 DG11 DG12 X: don’t care 10.2.1. M, A: Specifies the data to be turned on or off M 0 0 1 1 A 0 1 0 1 Display operating state Both MDATA and ADATA are turned off (The display is forcibly turned off regardless of the DG1 to DG12 data.) Only ADATA is turned on (The ADATA of display digits specified by the DG1 to DG12 data are turned on.) Only MDATA is turned on (The MDATA of display digits specified by the DG1 to DG12 data are turned on.) Both MDATA and ADATA are turned on (The MDATA and ADATA of display digits specified by the DG1 to DG12 data are turned on.) 15/ 37 FD2000 10.2.2. DG1 to DG12: Specifies the display digit Display digit Display digit data 1 DG1 2 DG2 3 DG3 4 DG4 5 DG5 6 DG6 7 DG7 8 DG8 9 DG9 10 DG10 11 DG11 12 DG12 Rev1.0 For example, if DG1 to DG6 are 1, and DG7 to DG12 are 0, then display digits 1 to 6 will be turned on, and display digits 7 to 12 will be turned off (blanked). 10.2.3. SC: Controls the common and segment output pins SC 0 Common and segment output pin states Output of LCD drive waveforms 1 Fixed at the VSS level (all segments off) NOTE: When SC is 1, the S1 to S60 and COM1 to COM10 output pins are set to the VSS level, regardless of the M, A, and DG1 to DG12 data. 10.2.4. BU: Controls the normal mode and power saving mode BU 0 Normal mode Power saving mode (In this mode, the OSCI and OSCO pins oscillator is stopped, and the common and segment pins are set to the VSS level. In this mode, instructions other than the “display on/off control” instruction cannot be executed. Thus applications must set the LSI to normal mode before executing any of the other instructions.) Mode 1 10.3. DISPLAY SHIFT ― Shifts the display Code D56 M D57 A D58 R/L D59 X D60 0 D61 0 D62 1 D63 1 X: don’t care 10.3.1. M, A: Specifies the data to be shifted M 0 0 1 1 A 0 1 0 1 Shift operating state Neither MDATA nor ADATA is shifted Only ADATA is shifted Only MDATA is shifted Both MDATA and ADATA are shifted 10.3.2. R/L: Shift direction specification R/L 0 1 Shift direction Left shift Right shift 16/ 37 FD2000 10.4. SET AC ADDRESS ― Specifies the DCRAM and ADRAM address for AC Code D48 DA0 D49 DA1 D50 DA2 D51 DA3 D52 DA4 D53 DA5 D54 X D55 X D56 RA0 D57 RA1 D58 RA2 D59 RA3 D60 0 D61 1 D62 0 D63 0 Rev1.0 X: don’t care 10.4.1. DA0 to DA5: DCRAM address DA0 LSB DA1 DA2 DA3 DA4 DA5 MSB 10.4.2. RA0 to RA3: ADRAM address RA0 LSB RA1 RA2 RA3 MSB This instruction loads the 6-bit DCRAM address DA0 to DA5 and the 4-bit ADRAM address RA0 to RA3 into the AC. 10.5. DCRAM DATA WRITE ― Specifies the DCRAM address and stores data at that address Code D40 D41 D42 D43 D44 D45 D46 D47 D48 D49 D50 D51 D52 D53 D54 D55 D56 D57 D58 D59 D60 D61 D62 D63 AC0 AC1 AC2 AC3 AC4 AC5 AC6 AC7 DA0 DA1 DA2 DA3 DA4 DA5 X X IM X X X 0 1 0 1 X: don’t care 10.5.1. DA0 to DA5: DCRAM address DA0 LSB DA1 DA2 DA3 DA4 DA5 MSB 10.5.2. AC0 to AC7: DCRAM data (character code) AC0 LSB AC1 AC2 AC3 AC4 AC5 AC6 AC7 MSB This instruction writes the 8 bits of data AC0 to AC7 to DCRAM. This data is a character code, and is converted to a 5 x 7, 5 x 8, or 5 x 9 dot matrix display data using CGROM or CGRAM. 10.5.3. IM: Setting the method of writing data to DCRAM IM 0 1 DCRAM data write method Normal DCRAM data write (Specifies the DCRAM address and writes the DCRAM data.) Increment mode DCRAM data write (Increments the DCRAM address by +1 each time data is written to DCRAM.) 17/ 37 FD2000 − DCRAM data write method when IM = 0 Rev1.0 − DCRAM data write method when IM = 1 (Instructions other than the “DCRAM data write” instruction cannot be executed.) 10.5.4. Data format at (1) (24 bits) Code D40 D41 D42 D43 D44 D45 D46 D47 D48 D49 D50 D51 D52 D53 D54 D55 D56 D57 D58 D59 D60 D61 D62 D63 AC0 AC1 AC2 AC3 AC4 AC5 AC6 AC7 DA0 DA1 DA2 DA3 DA4 DA5 X X IM X X X 0 1 0 1 X: don’t care 10.5.5. Data format at (2) (8 bits) Code D56 D57 D58 D59 D60 D61 D62 D63 AC0 AC1 AC2 AC3 AC4 AC5 AC6 AC7 10.5.6. Data format at (3) (16 bits) Code D48 D49 D50 D51 D52 D53 D54 D55 D56 D57 D58 D59 D60 D61 D62 D63 AC0 AC1 AC2 AC3 AC4 AC5 AC6 AC7 0 X X X 0 1 0 1 X: don’t care 18/ 37 FD2000 Rev1.0 10.6. ADRAM DATA WRITE ― Specifies the ADRAM address and stores data at that address Code D40 D41 D42 D43 D44 D45 D46 D47 D48 D49 D50 D51 D52 D53 D54 D55 D56 D57 D58 D59 D60 D61 D62 D63 AD1 AD2 AD3 AD4 AD5 X X X RA0 RA1 RA2 RA3 X X X X IM X X X 0 1 1 0 X: don’t care 10.6.1. RA0 to RA3: ADRAM address RA0 LSB RA1 RA2 RA3 MSB 10.6.2. AD1 to AD5: ADATA display data In addition to the 5 x 7, 5 x 8, or 5 x 9 dot matrix display data (MDATA), this LSI supports direct display of the five accessory display segments provided in each digit as ADATA. This display function does not use CGROM or CGRAM. The figure below shows the correspondence between the data and the display. When ADn = 1 (where n is an integer between 1 and 5) the segment corresponding to that data will be turned on. 10.6.3. IM: Setting the method of writing data to ADRAM IM 0 1 ADRAM data write method Normal ADRAM data write (Specifies the ADRAM address and writes the ADRAM data.) Increment mode ADRAM data write (Increments the ADRAM address by +1 each time data is written to ADRAM.) − ADRAM data write method when IM = 0 19/ 37 FD2000 Rev1.0 − ADRAM data write method when IM = 1 (Instructions other than the “ADRAM data write” instruction cannot be used.) 10.6.4. Data format at (4) (24 bits) Code D40 D41 D42 D43 D44 D45 D46 D47 D48 D49 D50 D51 D52 D53 D54 D55 D56 D57 D58 D59 D60 D61 D62 D63 AD1 AD2 AD3 AD4 AD5 X X X RA0 RA1 RA2 RA3 X X X X IM X X X 0 1 1 0 X: don’t care 10.6.5. Data format at (5) (8 bits) Code D56 D57 D58 D59 D60 D61 D62 D63 AD1 AD2 AD3 AD4 AD5 X X X X: don’t care 10.6.6. Data format at (6) (16 bits) Code D48 D49 D50 D51 D52 D53 D54 D55 D56 D57 D58 D59 D60 D61 D62 D63 AD1 AD2 AD3 AD4 AD5 X X X 0 X X X 0 1 1 0 X: don’t care 20/ 37 FD2000 Rev1.0 10.7. CGRAM DATA WRITE ― Specifies the CGRAM address and stores data at that address Code D0 CD1 D1 CD2 D2 CD3 D3 CD4 D4 CD5 D5 CD6 D6 CD7 D7 CD8 D8 CD9 D9 CD10 D10 CD11 D11 CD12 D12 CD13 D13 CD14 D14 CD15 D15 CD16 Code D16 CD17 D17 CD18 D18 CD19 D19 CD20 D20 C21 D21 CD22 D22 CD23 D23 CD24 D24 CD25 D25 CD26 D26 CD27 D27 CD28 D28 CD29 D29 CD30 D30 CD31 D31 CD32 Code D32 CD33 D33 CD34 D34 CD35 D35 CD36 D36 CD37 D37 CD38 D38 CD39 D39 CD40 D40 CD41 D41 CD42 D42 CD43 D43 CD44 D44 CD45 D45 X D46 X D47 X Code D48 CA0 D49 CA1 D50 CA2 D51 CA3 D52 CA4 D53 CA5 D54 CA6 D55 CA7 D56 X D57 X D58 X D59 X D60 0 D61 1 D62 1 D63 1 X: don’t care 10.7.1. CA0 to CA7: CGRAM address CA0 LSB CA1 CA2 CA3 CA4 CA5 CA6 CA7 MSB 10.7.2. CD1 to CD45: CGRAM data (5 x 7, 5 x 8, or 5 x 9 dot matrix display data) The bit CDn (where n is an integer between 1 and 45) corresponds to the 5 x 7, 5 x 8, or 5 x 9 dot matrix display data. The figure below shows that correspondence. The dots for which the corresponding data CDn is 1 will be turned on. CD1 CD6 CD11 CD16 CD21 CD26 CD31 CD36 CD41 CD2 CD7 CD12 CD17 CD22 CD27 CD32 CD37 CD42 CD3 CD8 CD13 CD18 CD23 CD28 CD33 CD38 CD43 CD4 CD9 CD14 CD19 CD24 CD29 CD34 CD39 CD44 CD5 CD10 CD15 CD20 CD25 CD30 CD35 CD40 CD45 NOTES: 1. CD1 to CD35: 5 x 7 dot matrix display data 2. CD1 to CD40: 5 x 8 dot matrix display data 3. CD1 to CD45: 5 x 9 dot matrix display data 21/ 37 FD2000 11. NOTES ON THE POWER ON AND POWER OFF SEQUENCES At power on: Logic block power supply (VDD) on → LCD driver block power supply (VLCD) on At power off: LCD driver block power supply (VLCD) off → Logic block power supply (VDD) off Rev1.0 However, if the logic and LCD driver block use a shared power supply, then the power supplies can be turned on and off at the same time. 22/ 37 FD2000 12. LCD DRIVE TECHNIQUE 12.1. 1/8 DUTY, 1/4 BIAS DRIVE TECHNIQUE Rev1.0 COM1 COM2 VLCD VLCD1 VLCD2 VLCD3 VSS VLCD VLCD1 VLCD2 VLCD3 VSS COM8 VLCD VLCD1 VLCD2 VLCD3 VSS VLCD VLCD1 VLCD2 VLCD3 VSS VLCD VLCD1 VLCD2 VLCD3 VSS VLCD VLCD1 VLCD2 VLCD3 VSS VLCD VLCD1 VLCD2 VLCD3 VSS 384T 3072T 1 fosc LCD driver output when all LCD segments corresponding to COM1 to COM8 are turned off. LCD driver output when only LCD segments corresponding to COM1 are turned on. LCD driver output when only LCD segments corresponding to COM2 are turned on. LCD driver output when all LCD segments corresponding to COM1 to COM8 are turned on. T= 23/ 37 FD2000 12.2. 1/9 DUTY, 1/4 BIAS DRIVE TECHNIQUE Rev1.0 COM1 COM2 VLCD VLCD1 VLCD2 VLCD3 VSS VLCD VLCD1 VLCD2 VLCD3 VSS COM9 VLCD VLCD1 VLCD2 VLCD3 VSS VLCD VLCD1 VLCD2 VLCD3 VSS VLCD VLCD1 VLCD2 VLCD3 VSS VLCD VLCD1 VLCD2 VLCD3 VSS VLCD VLCD1 VLCD2 VLCD3 VSS 384T 3456T 1 fosc LCD driver output when all LCD segments corresponding to COM1 to COM9 are turned off. LCD driver output when only LCD segments corresponding to COM1 are turned on. LCD driver output when only LCD segments corresponding to COM2 are turned on. LCD driver output when all LCD segments corresponding to COM1 to COM9 are turned on. T= 24/ 37 FD2000 12.3. 1/10 DUTY, 1/4 BIAS DRIVE TECHNIQUE Rev1.0 COM1 COM2 VLCD VLCD1 VLCD2 VLCD3 VSS VLCD VLCD1 VLCD2 VLCD3 VSS COM10 VLCD VLCD1 VLCD2 VLCD3 VSS VLCD VLCD1 VLCD2 VLCD3 VSS VLCD VLCD1 VLCD2 VLCD3 VSS VLCD VLCD1 VLCD2 VLCD3 VSS VLCD VLCD1 VLCD2 VLCD3 VSS 384T 3840T 1 fosc LCD driver output when all LCD segments corresponding to COM1 to COM10 are turned off. LCD driver output when only LCD segments corresponding to COM1 are turned on. LCD driver output when only LCD segments corresponding to COM2 are turned on. LCD driver output when all LCD segments corresponding to COM1 to COM10 are turned on. T= 25/ 37 FD2000 13. SAMPLE APPLICATION CIRCUIT 13.1. 1/8 DUTY, 1/4 BIAS DRIVE (FOR USE WITH NORMAL PANELS) Rev1.0 13.2. 1/8 DUTY, 1/4 BIAS DRIVE (FOR USE WITH LARGE PANELS) 26/ 37 FD2000 13.3. 1/9 DUTY, 1/4 BIAS DRIVE (FOR USE WITH NORMAL PANELS) Rev1.0 13.4. 1/9 DUTY, 1/4 BIAS DRIVE (FOR USE WITH LARGE PANELS) 27/ 37 FD2000 13.5. 1/10 DUTY, 1/4 BIAS DRIVE (FOR USE WITH NORMAL PANELS) Rev1.0 13.6. 1/10 DUTY, 1/4 BIAS DRIVE (FOR USE WITH LARGE PANELS) 28/ 37 FD2000 Rev1.0 14. SAMPLE CORRESPONDENCE BETWEEN INSTRUCTIONS AND THE DISPLAY LSB No. D40 to D43 Instruction (Hex) D44 to D47 D48 to D51 D52 to D55 D56 to D59 MSB D60 to D63 Display Operation 1 Power application (Initialization with the RESETB pin.) Initializes the IC. The display is in the off state. 2 Set display technique 0 8 Sets to 1/8 duty 1/4 bias display drive technique 3 DCRAM data write (increment mode) 0 2 0 0 1 A Writes the display data “ ” to DCRAM address 00H 4 DCRAM data write (increment mode) 6 4 Writes the display data “F” to DCRAM address 01H 5 DCRAM data write (increment mode) 9 4 Writes the display data “I” to DCRAM address 02H 6 DCRAM data write (increment mode) E 4 Writes the display data “N” to DCRAM address 03H 7 DCRAM data write (increment mode) 5 4 Writes the display data “E” to DCRAM address 04H 8 DCRAM data write (increment mode) 3 4 Writes the display data “C” to DCRAM address 05H 9 DCRAM data write (increment mode) 8 4 Writes the display data “H” to DCRAM address 06H 10 DCRAM data write (increment mode) 9 4 Writes the display data “I” to DCRAM address 07H 11 DCRAM data write (increment mode) 0 5 Writes the display data “P” to DCRAM address 08H 12 DCRAM data write (increment mode) 3 5 Writes the display data “S” to DCRAM address 09H 13 DCRAM data write (increment mode) 0 2 Writes the display data “ ” to DCRAM address 0AH 14 DCRAM data write (increment mode) 0 2 Writes the display data “ ” to DCRAM address 0BH 15 DCRAM data write (increment mode) 6 4 Writes the display data “F” to DCRAM address 0CH 16 DCRAM data write (increment mode) 4 4 Writes the display data “D” to DCRAM address 0DH 17 DCRAM data write (increment mode) 2 3 Writes the display data “2” to DCRAM address 0EH 18 DCRAM data write (increment mode) 0 3 Writes the display data “0” to DCRAM address 0FH 19 DCRAM data write (increment mode) 0 3 Writes the display data “0” to DCRAM address 10H 29/ 37 FD2000 Continued from preceding page. LSB No. D40 to D43 Instruction (Hex) D44 to D47 D48 to D51 D52 to D55 D56 to D59 0 MSB D60 to D63 3 Rev1.0 Display Operation 20 21 22 23 24 25 26 27 28 29 30 31 32 33 DCRAM data write (increment mode) DCRAM data write (increment mode) 0 2 0 A Set AC address Writes the display data “0” to DCRAM address 11H Writes the display data “ ” to DCRAM address 12H Loads the DCRAM address 00H and the ADRAM address 0H into AC F I NECH I PS F I NECH I PS I NECH I PS NECH I PS ECH I PS CH I PS HIPS IPS F FD FD2 FD20 FD200 FD2000 FD2000 Turns on the LCD for all digits (12 digits) in MDATA Shifts the display (MDATA only) to the left Shifts the display (MDATA only) to the left Shifts the display (MDATA only) to the left Shifts the display (MDATA only) to the left Shifts the display (MDATA only) to the left Shifts the display (MDATA only) to the left Shifts the display (MDATA only) to the left Set to power saving mode, turns off the LCD for all digits IPS FD2000 Turns on the LCD for all digits (12 digits) in MDATA Loads the DCRAM address 00H and the ADRAM address 0H into AC X: don’t care 0 F F F 0 X 0 1 1 2 4 C C C C C C C 4 4 2 Display on/off control Display shift Display shift 1 Display shift 1 Display shift 1 Display shift 1 Display shift 1 Display shift 1 Display on/off control 0 F 0 F 0 F 0 X X 0 8 1 0 Display on/off control Set AC address F I NECH I PS NOTE: This example above assumes the use of 12 digits 5 ´ 7 dot matrix LCD. CGRAM and ADRAM are not used. 30/ 37 FD2000 15. FD2000 CHARACTER FONT (STANDARD) Rev1.0 31/ 37 FD2000 16. ELECTRICAL CHARACTERISTICS 16.1. ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, VSS=0V) Parameter Maximum supply voltage Symbol VDD max VLCD max VIN1 Input voltage VIN2 VIN3 Output voltage VOUT1 VOUT2 Output current Allowable power dissipation Operating temperature Storage temperature IOUT1 IOUT2 Pd max Topr Tstg VDD VLCD CE, CL, DI, RESETB OSCI VLCD1, VLCD2, VLCD3 OSCO S1 to S60, COM1 to COM10 S1 to S60 COM1 to COM10 Ta = 85°C Conditions Ratings –0.3 to +7.0 –0.3 to +11.0 –0.3 to +7.0 –0.3 to VDD + 0.3 –0.3 to VLCD + 0.3 –0.3 to VDD + 0.3 –0.3 to VLCD + 0.3 300 3 200 –40 to +85 –55 to +125 Rev1.0 Unit V V V V V V V uA mA mW °C °C 32/ 37 FD2000 16.2. ALLOWABLE OPERATING RANGES (TA = –40 to 85°C, VSS = 0 V) Parameter Symbol Conditions Min Operating Voltage VDD VLCD VLCD1 Input voltage VLCD2 VLCD3 Input high level voltage VIH1 VIH2 Input low level voltage Recommended external resistance Recommended external capacitance Guaranteed oscillation range Data setup time Data hold time CE wait time CE setup time CE hold time High level clock pulse width Low level clock pulse width Minimum reset pulse width VIL1 VIL2 ROSC COSC fOSC tds tdh tcp tcs tch tøH tøL tWRES VDD VLCD VLCD1 VLCD2 VLCD3 CE, CL, DI, RESETB OSCI CE, CL, DI, RESETB OSCI OSCI, OSCO OSCI, OSCO OSC CL, DI CL, DI CE, CL CE, CL CE, CL CL CL RESETB 2.7 4.5 0.8 VDD 0.7 VDD 0 0 150 160 160 160 160 160 160 160 1 Ratings T yp 3/4 VLCD 2/4 VLCD 1/4 VLCD 33 220 300 Max 6.0 10.0 VLCD VLCD VLCD 6.0 VDD 0.2 VDD 0.3 VDD 600 - Rev1.0 Unit V V V V V V V V V kΩ pF kHz ns ns ns ns ns ns ns μs 33/ 37 FD2000 Rev1.0 16.3. ELECTRICAL CHARACTERISTICS IN THE ALLOWABLE OPERATING RANGES Parameter Symbol Conditions Min Hysteresis Input high level current Input low level current VH IIH IIL VOH1 Output high level voltage VOH2 VOH3 VOL1 Output low level voltage VOL2 VOL3 VMID1 Output middle level NOTE1 voltage VMID2 VMID3 Oscillator frequency fOSC IDD1 IDD2 Supply current ILCD1 ILCD2 CE, CL, DI, RESETB CE, CL, DI, RESETB, OSCI: VI = 6.0 V CE, CL, DI, RESETB, OSCI: VI = 0 V S1 to S60: IO = –20 μA COM1 to COM10: IO = –100 μA OSCO: IO = –500 μA S1 to S60: IO = 20 μA COM1 to COM10: IO = 100 μA OSCO: IO = 500 μA S1 to S60: IO ±20 μA COM1 to COM10: IO = ±100 μA COM1 to COM10: IO = ±100 μA OSCI, OSCO: ROSC = 33 kΩ , COSC = 220 pF VDD: power saving mode VDD: VDD = 6.0 V, output open, fOSC = 300 kHz VLCD: power saving mode VLCD: VLCD = 10.0 V, output open, fOSC = 300 kHz – – – 5.0 VLCD – 0.6 VLCD – 0.6 VDD – 1.0 – – – 2/4 VLCD – 0.6 3/4 VLCD – 0.6 1/4 VLCD – 0.6 Ratings T yp 0.1 VDD – – – – – – – – – – – 300 – 450 – 200 Max – 5.0 – – – – 0.6 0.6 1.0 2/4 VLCD + 0.6 3/4 VLCD + 0.6 1/4 VLCD + 0.6 390 5 900 5 400 Unit V μA μA V V V V V V V V V kHz μA μA μA μA 210 – – – – NOTE: Excluding the bias voltage generation divider resistor built into the VLCD1, VLCD2, and VLCD3. 34/ 37 FD2000 − Voltage Divider Resistor Circuit for Bias Rev1.0 − W hen CL is stopped at the low level − W hen CL is stopped at the high level 35/ 37 FD2000 D D1 A3 COMMON DIMENSIONS ( UNITS OF MEASURE= MILLIMETER ) A2 A1 17.1. 80-MQFP-1420 A 17. PACKAGE DIMENSIONS 2 TOP E-MARK ø2.0±0.1 0.2MAX DEPTH 2 BTM E-MARK ø3.0±0.1 0.1±0.05 DEPTH θ1 θ2 INDEX ø1.2±0.1 0.4±0.1 DEPTH MIN ─ 0.10 2.65 1.20 0.32 0.32 0.14 0.14 23.00 19.90 17.00 13.90 0.70 MAX 3.30 0.40 2.85 1.40 0.42 0.38 0.20 0.16 23.40 20.10 17.40 14.10 0.90 e 0.20 b 0.68 1.08 AA b WITH PLATING b1 BASE METAL G1E or G1D SYMBOL A A1 A2 A3 b b1 c c1 D D1 E E1 e G1D G1E L L1 L2 θ θ1 θ2 0° 11° 3° 8° 15° 7° NOM ─ ─ 2.75 1.30 ─ 0.35 ─ 0.15 23.20 20.00 17.20 14.00 0.80 21.30REF 15.30REF 0.88 1.60REF 0.25BSC 2° 13° 5° NOTES:1.ALL DIMENSIONS REFER TO EIAJ STANDARD ED 7311A 80 ─ 001 ─ PB DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. 2.THE LEADFRAME BASE METAL IS Cu. SECTION A─A θ L (L1) Rev1.0 36/ 37 FD2000 D D1 A2 A3 A1 A 17.2. 80-LQFP-1212 COMMON DIMENSIONS ( UNITS OF MEASURE= MILLIMETER ) TOP ─ E ─ MARK 2 ─ ø1.80±0.10x0.10±0.05D E E1 BTM ─ E ─ MARK 2 ─ ø1.80±0.10x0.10±0.05D INDEX ø1.20±0.10 0.20±0.10 DEPTH 0.08 MIN ─ 0.05 1.35 0.59 0.18 0.17 0.13 0.12 13.80 11.90 13.80 11.90 0.40 0.45 MAX 1.60 0.15 1.45 0.69 0.27 0.23 0.18 0.134 14.20 12.10 14.20 12.10 0.60 0.75 e b 0. 08 AA WITH PLATING BASE METAL θ2 b b1 c c1 SYMBOL A A1 A2 A3 b b1 c c1 D D1 E E1 e L L1 L2 R1 L2 θ θ1 θ2 θ3 0.08 0.08 0° 0° 11° 11° ─ 0.20 7° ─ 13° 13° NOM ─ ─ 1.40 0.64 ─ 0.20 ─ 0.127 14.00 12.00 14.00 12.00 0.50 0.60 1.00REF 0.25BSC ─ ─ 3.5° ─ 12° 12° θ1 NOTES: ALL DIMENSIONS REFER TO JEDEC STANDARD MS ─ 026 BDD DO NOT INCLUDE MOLD SECTION A─A FLASH OR PROTRUSIONS. R 1 + R2 L2 L θ3 θ (L1) Rev1.0 37/ 37