MPC18730EPR2

Freescale Semiconductor Advance Information Document Number: MPC18730 Rev. 4.0, 8/2006 Power Management IC with Five Regulated Outputs Programmed Through 3-Wire Serial Interface The MPC18730 Power Management IC (PMIC) regulates five independent output voltages from either a single cell Li-Ion (2.7 V to 4.2 V input range) or from a single cell Ni-MH or dry cell (0.9 V to 2.2 V input range). The PMIC includes 2 DC-DC converters and 3 low drop out (LDO) linear regulators. The output voltage for each of the 5 output voltages is set independently through a 3-wire serial interface. The serial interface also configures the PMIC's versatile start-up control system, which includes multiple wakeup, sleep, standby, and reset modes to minimize power consumption for portable equipment. In single cell Li-Ion applications two DC-DC converters are configured as buck (step-down) regulators. In single cell Ni-MH or dry cell applications, one DC-DC converter is configured as a boost (step-up) regulator, and the other as buck-boost regulator. The DCDC converters' output voltages have set ranges 1.613 V to 3.2 V at up to 120 mA, and 0.805 V to 1.5 V up to 100 mA. Features • • • • • • • Operates from single cell Li-Ion, Ni-MH, or Alkaline 2 DC-DC Converters 3 Low Drop Regulators Serial Interface Sets Output Voltages 4 Wake Inputs Low Current Standby Mode Pb-Free Packaging Designated by Suffix Code EP VB VBATT VO VREF PGOOD1 VGATE_EXT VO 18730 POWER MANAGEMENT IC EP SUFFIX (PB-FREE) 98ARL10571D 64-PIN QFN ORDERING INFORMATION Device MPC18730EP/R2 Temperature Range (TA) -10°C to 65°C Package 64 QFN MPC18730 VOUT1 VO1_SENSE SW1 VOUT2 VO2_SENSE SW2 SREGI1 SREGO1 SREGI2 SREGO2 SREGI3 SREGO3 VGATE SWGATE VB Programmable 1.613 V to 3.2 V Programmable 0.805 V to 1.5 V PGOOD2 MCU { Programmable 0.865 V to 2.8 V Programmable 0.011 V to 2.8 V Programmable 2.08 V to 2.8 V CONTROL LOGIC INPUTS GND GNDGATE Figure 1. MPC18730 Simplified Application Diagram * This document contains certain information on a new product. Specifications and information herein are subject to change without notice. © Freescale Semiconductor, Inc., 2006. All rights reserved. INTERNAL BLOCK DIAGRAM INTERNAL BLOCK DIAGRAM HVB LVB Driver VMODE VMODE VO1_SENSE PGOOD1(Int) VO1_SENSE PGOOD1(Int) BANDGAP REFERENCE CLEAR VGATE PGOOD1(Int) POWER PGOOD1(Int) VO1_SENSE SWITCH1 REF1 VGATE Step-UpDown DC/DC Converter CH1 VBATT VBATT LVB V_STDBY VOUT1 VREF VREF LSWO VO1_SENSE PGOOD1 RESET Block 1 PGOOD1_DELAY RESET1_TH EAIN1 EAOUT1 VO1_SENSE VIN1 SW1 PGND1 VGATE VOUT2 VO2_SENSE_IN VO2_SENSE HG REF2 Step-UpDown DC/DC Converter CH2 LG VIN2 DMAX1 VO1_SENSE PGOOD2 RESET Block 2 PGOOD2_DELAY EAOUT2 EAIN2 PGOOD2(Int) VGATE PGOOD2(Int) POWER SWITCH2 SW2 DMAX2 VGATE REF3 SREGC1 Series Pass Regulator1 VGATE SREGC2 REF4 V_STDBY SREGC3 VO1_SENSE VBATT WAKE1B WAKE2B WAKE3B WAKE4B SEQ_SELECT DATA STRB SCKIN CLEAR SLEEP EXT_CLOCK GND VGATESEL1 VGATESEL2 WATCHDOG REF DAC REF5 VGATE Series Pass Regulator3 VBATT EXT_CLOCK Series Pass Regulator2 PGND2 SREGI1 SREGO1 SREGI2 SREGO2 SREG2G SREGI3 SREGO3 CH_PUMP PGOOD1(Int) CPoff PGOOD2 VBATT VGATE CONTROL (Int) SEQ_SELECT Control VO1_SENSE Logic Step-Up VG_SELECT DC/DC VGATE_DUTY Convertor REF2 REF1 REF4 REF5 On VREF VGATE EXT gate On Buffer VGATE SWGATE GNDGATE REF3 VGATE_EXT Figure 2. MPC18730 Simplified Internal Block Diagram 18730 2 Analog Integrated Circuit Device Data Freescale Semiconductor PIN CONNECTIONS PIN CONNECTIONS SEQ_SELECT EXT_CLOCK WATCHDOG SREG2G SREGO1 SREGO2 SREGC1 SREGI1 SREGI2 SLEEP SCKIN VREF STRB DATA GND CLEAR WAKE4B WAKE3B WAKE2B WAKE1B LSWO LVB HVB V_STDBY VO1_SENSE VOUT1 VIN1 SW1 SW1 PGND1 PGND1 1 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 2 48 3 4 5 6 7 8 9 10 11 12 13 14 15 16 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 17 VGATESEL2 DMAX1 VBATT PGOOD1_DELAY VGATESEL1 RESET1_TH PGOOD1 EAOUT1 CH_PUMP SWGATE GNDGATE EAOUT2 DMAX2 EAIN1 VGATE EAIN2 49 SREGC2 SREGI3 SREGO3 SREGC3 VGATE_EXT LG HG VO2_SENSE VO2_SENSE_IN VOUT2 VIN2 SW2 SW2 PGND2 PGND2 PGOOD2 47 46 45 44 43 42 41 TOP VIEW 40 39 38 37 36 35 34 33 PGOOD2_DELAY Figure 3. MPC18730 Pin Connections Table 1. MPC18730 Pin Definitions A functional description of each pin can be found in the Functional Pin Description section beginning on page 14. Pin Number 1 2 3 4 5 6 Pin Name CLEAR WAKE4B WAKE3B WAKE2B WAKE1B LSWO Pin Function Input Input Input Input Input Output Formal Name Clear Wake Signal 4 Wake Signal 3 Wake Signal 2 Wake Signal 1 Low-Side Switch Output Definition Start-up Signal Input Latch/Clear Start-up Signal Input 4 Start-up Signal Input 3 Start-up Signal Input 2 Start-up Signal Input 1 Low-Side Switch Output Pin 18730 Analog Integrated Circuit Device Data Freescale Semiconductor 3 PIN CONNECTIONS Table 1. MPC18730 Pin Definitions (continued) A functional description of each pin can be found in the Functional Pin Description section beginning on page 14. Pin Number 7 8 9 10 11 12 13 14 15 16 17 Pin Name LVB HVB V_STDBY VO1_SENSE VOUT1 VIN1 SW1 SW1 PGND1 PGND1 PGOOD1 Pin Function Input Input Output Input Output Output Power Power Ground Ground Output Formal Name Low Voltage Battery High Voltage Battery Standby Voltage Voltage Input 1 Voltage Output 1 Voltage Output 1 Switching 1 Switching 1 Power Ground 1 Power Ground 1 Inverted Reset Output 1 18 PGOOD1_DELAY Input Reset Delay Capacitor 1 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 RESET1_TH DMAX1 EAOUT1 EAIN1 CH_PUMP VGATE SWGATE GNDGATE VBATT VGATESEL2 VGATESEL1 EAIN2 EAOUT2 DMAX2 PGOOD2_DELAY Output Power Output Input Power Output Power Ground Power Output Output Input Output Power Input Reset1 Adjustment Duty Control Reference Feedback 1 Input Minus 1 Charge Pump Capacitor Gate Voltage Switching Power Ground 3 Battery Voltage VGATE Select 2 VGATE Select 1 Input Minus Reference Feedback 2 Duty Control Reset Delay Capacitor 1 34 PGOOD2 Output Inverted Reset Output 2 35 36 PGND2 PGND2 Ground Ground Power Ground 2 Power Ground 2 Switching Power Supply Circuit 2 Power GND Switching Power Supply Circuit 2 Power GND Reset Circuit 2 Reset Signal Output Switching Power Supply Circuit 1 Reset Voltage Reference Output Switching Power Supply Circuit 1 Maximum Duty Setting Switching Power Supply Circuit 1 Error Amp Output Switching Power Supply Circuit 1 Error Amp Inverse Input VGATE Power Supply Circuit Charge Pump Capacitor Connection VGATE Power Supply Circuit Voltage Output, Pre-Diver Circuit Power Supply VGATE Power Supply Circuit Coil Connection VGATE Power Supply Circuit Power GND VB Power Supply Connection VG Power Supply Circuit Output Voltage Setting 2 VGATE Power Supply Circuit Output Voltage Setting 1 Switching Power Supply Circuit 2 Error Amp Inverting Input Switching Power Supply Circuit 2 Error Amp Output Switching Power Supply Circuit 2 Maximum Duty Setting Reset Circuit 2 Reset Signal Delay Capacitor Connection Reset Circuit 1 Reset Signal Delaying Capacitor Connection Definition VB Power Supply Connection for Ni_mh VB Power Supply Connection for Li_ion V_STDBY Voltage Output Switching Power Supply Circuit 1, VO1_SENSE Voltage Input, VO1_SENSE Power Supply Power Switch 1 Output Switching Power Supply Circuit 1 Output Switching Power Supply Circuit 1 Coil Connection Switching Power Supply Circuit 1 Coil Connection Switching Power Supply Circuit 1 Power GND Switching Power Supply Circuit 1 Power GND Reset Circuit 1 Reset Signal Output 18730 4 Analog Integrated Circuit Device Data Freescale Semiconductor PIN CONNECTIONS Table 1. MPC18730 Pin Definitions (continued) A functional description of each pin can be found in the Functional Pin Description section beginning on page 14. Pin Number 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Pin Name SW2 SW2 VIN2 VOUT2 VO2_SENSE_IN VO2_SENSE HG LG VGATE_EXT SREGC3 SREGO3 SREGI3 SREGC2 SREG2G SREGO2 SREGI2 SREGC1 SREGO1 SREGI1 GND VREF DATA STRB SCKIN WATCHDOG SEQ_SELECT EXT_CLOCK SLEEP Pin Function Power Power Output Output Input Input Output Output Output Power Output Power Power Output Output Power Power Output Power Ground Output Input Input Input Input Input Input Input Formal Name Switching Switching Voltage Output Voltage Output Voltage Input Voltage Input Definition Switching Power Supply Circuit 2 Coil Connection Switching Power Supply Circuit 2 Coil Connection Switching Power Supply Circuit 2 Output Power Switch 2 Output Power Switch 2 Voltage Input Switching Power Supply Circuit 2 VO2_SENSE Voltage Input Step Down Top FET 2 Switching Power Supply Circuit 2 Step down Top side FET Gate Output for Ni_mh Step Down Bottom FET 2 Gate Switch Switching Power Supply Circuit 2 Step down Bottom side FRT Gate Output for Ni_mh External Transistor Gate Signal Output Regulator Capacitor 3 Series Pass Power Supply Circuit 3 External Feedback Connection Regulator Output 3 Regulator Input 3 Series Pass Power Supply Circuit 3 Output Series Pass Power Supply Circuit 3 Power Supply Regulator Capacitor 2 Series Pass Power Supply Circuit 2 External Feedback Connection Regulator Gate Output 2 Regulator Output 2 Regulator Input 2 Series Pass Power Supply Circuit 2 External Transistor Gate Signal Output Series Pass Power Supply Circuit 2 Output Series Pass Power Supply Circuit 2 Power Supply Regulator Capacitor 1 Series Pass Power Supply Circuit 1 External Feedback Connection Regulator Output 1 Regulator Input 1 Ground Reference Voltage Data Signal Strobe Serial Clock Watch Dog Timer Sequence Input Clock Input Sleep Signal Series Pass Power Supply Circuit 1 Output Series Pass Power Supply Circuit 1 Power Supply GND Reference Voltage Output Serial Interface Data Signal Input Serial Interface Strobe Signal Input Serial Interface Clock Signal Input Watchdog Timer Capacitor Connection Start-Up Sequence Setting Input External Synchronous Clock Signal Input Sleep Signal Input 18730 Analog Integrated Circuit Device Data Freescale Semiconductor 5 ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS Table 2. Maximum Ratings All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device. Ratings ELECTRICAL RATINGS Power Supply Voltage Analog Signal Input Logic Signal Input WAKE1~4B CLEAR, SLEEP, EXT_CLOCK, SCKIN, DATA, STRB VGATESEL1,2 Output Power Current VOUT1 Power Supply Circuit VOUT2 Power Supply Circuit SREG1 Power Supply Circuit SREG2 Power Supply Circuit SREG3 Power Supply Circuit VGATE Power Supply Circuit PGOOD1 Power Supply Circuit Open-Drain Output Apply Voltage PGOOD1 LSWO ESD Voltage (3) (2) (1) Symbol Value Unit VBATT VINAN VILRSTB VILGC VILGSEL -0.5 to 5.0 -0.5 to VO1+0.5 V V V -0.5 to V_STDBY+0.5 -0.5 to VO1_SENSE+0.5 -0.5 to VBATT+0.5 mA IOVO1 IOVO2 IOREG1 IOREG2 IOREG3 IOVG IOPGOOD1 120 100 80 100 80 8 -20 V VIODR VIODV -0.5 to 3.3 -0.5 to 3.3 V ± 1500 ± 200 ± 750 Human Body Model (HBM) Machine Model (MM) Charge Device Model (CDM) THERMAL RATINGS Operating Temperature Ambient Junction Storage Temperature Thermal Resistance (4) VESD1 VESD2 VCDM °C TA TJ TSTG RθJA TSOLDER -10 to 65 150 -50 to 150 69 °C °C/W °C Junction to Ambient Lead Soldering Temperature(5) 260 Notes 1. VREF, DMAX1, DMAX2, SREGC1, SREGC2, SREGC3 and RESET1_TH. 2. Includes the series pass power supply circuit output current 3. ESD testing is performed in accordance with the Human Body Model (HBM) (CZAP = 100 pF, RZAP = 1500 Ω), the Machine Model (MM) (CZAP = 200 pF, RZAP = 0 Ω), and the Charge Device Model (CDM), Robotic (CZAP = 4.0pF). 4. 5. Device mounted on a 2s2p test board, in accordance with JEDEC JESD51-6 and JESD51-7. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. 18730 6 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS STATIC STATIC Table 3. Static Electrical Characteristics Characteristics noted under conditions VBATT = 1.2 V, VO1_SENSE = 2.4 V, VGATE= 6.0 V, fCLK = 176.4 kHz unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 27°C under nominal conditions unless otherwise noted. Characteristic GENERAL VB Power Supply Voltage Power Supply Voltage 1 Power Supply Voltage 2 Series Regulator Input Voltage Start-Up Voltage Analog Signal Input (9) Logic Signal Input WAKE1~4B CLEAR, SLEEP, EXT_CLOCK, DATA, STRB and SCKIN VGATESEL1, 2 Output Power Current VOUT1 Power Supply Circuit (10) VOUT2 Power Supply Circuit (10) SREG1 Power Supply Circuit SREG2 Power Supply Circuit SREG3 Power Supply Circuit VGATE Power Supply Circuit PGOOD Supply Current in Stand-by mode VB Supply Current (VB = 1.2 V for Ni_MH) (HVB = 3.5 V for Li-Ion) Supply Current in Operating mode VB Supply Current (VB = 1.2 V for Ni_MH) (HVB = 3.5 V for Li-Ion) Reference Power Supply Circuit Output Voltage Output Current Switching Power Supply 1 VOUT1 Output Voltage (Io = 0~100 mA) Notes 6. 7. 8. 9. 10. When applying voltage from an external source. 0.3 V when VGATE is 4.5 V. Provide 2 V or higher for the voltage difference (VGATE - VO1_SENSE). VREF, DMAX1, DMAX2, SREGC1, SREGC2, SREGC3 and RESET1_TH. Includes the series pass power supply circuit output current. VREF IOREF VOUT1 1.255 -0.3 2.3 1.275 2.4 1.295 0.3 2.5 V mA V IBNi IBLi 9.0 7.0 18 14 IBSNi IBSLi 5.0 8.0 10 12 mA IOVOUT1 IOVOUT2 IOSREG1 IOSREG2 IOSREG3 IOVG IOPGOOD 0 0 5.0 6.0 5.0 -5.0 100 80 60 80 60 6.0 0 µA VILRSTB VILGC VILGSEL 0 0 0 V_STDBY VO1_SENSE VBATT mA (6), (7) Symbol Min Typ Max Unit V VLVB VHVB VSREGI VBST VIANA 0.9 2.7 VSREG+0.2 0.9 0 (8) 1.2 3.5 VSREG+0.3 - 2.2 4.2 VSREG+0.4 VO1_SENSE V V V V 18730 Analog Integrated Circuit Device Data Freescale Semiconductor 7 ELECTRICAL CHARACTERISTICS STATIC Table 3. Static Electrical Characteristics (continued) Characteristics noted under conditions VBATT = 1.2 V, VO1_SENSE = 2.4 V, VGATE= 6.0 V, fCLK = 176.4 kHz unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 27°C under nominal conditions unless otherwise noted. Characteristic Switching Power Supply 2 VOUT2 Output Voltage (Io = 0~80 mA) HG Output Voltage (11) (Isource = 400 µA) (Isink = 400 µA) LG Output Voltage (11) (Isource = 400 µA) (Isink = 400 µA) Series Pass Power Supply Circuit SREG1 Control Voltage (Io = 5~60 mA) (12) SREG1-Error AMP Input offset voltage (13) Symbol Min Typ Max Unit V VOUT2 VDW2TH VDW2TL VDW2BH VDW2BL 1.05 5.2 0 5.2 0 1.15 - 1.25 VGATE 0.3 VGATE 0.3 VSREG1 SR1OFST VSREG2 SR2OFST VSREG3 SR3OFST SREG2GH SREG2GL 2.7 -13.5 2.7 -17 2.7 -11 5.0 0 2.8 2.8 2.8 - 2.9 24.5 2.9 17 2.9 23 VGATE 0.5 V mV V mV V mV V V SREG2 Control Voltage (Io = 6~80 mA) (12) SREG2-Error AMP Input offset voltage (14) SREG3 Control Voltage (Io = 5~60 mA) (12) SREG3-Error AMP Input offset voltage (15) SREG2G Output Voltage (16) (Isource = 2.5 µA) (Isink = 2.5 µA) Power Switch On Resistance VOUT1 Circuit VOUT2 Circuit VGATE Power Supply Circuit (Io = 0~6 mA) (Io = 0~6 mA) (17) (18) W RVOUT1 RVOUT2 VGATE_00 VGATE_10 VO1_SENSE1LH VO1_SENSE_1LL VGH VLVB 0.4 0.4 0.6 0.6 V 5.5 4.6 VB x 0.85 0 1.75 6.0 5.0 6.5 5.4 VB 0.4 10.5 2.45 V CH_PUMP Output Voltage (Isource = 2.5 mA) (Isink = 2.5 mA) VGH Voltage (Certified value) V_STDBY Output Voltage for Li_ion (Io = 300 µA) (19) Notes 11. Connect a transistor with gate capacity of 200 pF or smaller to HG and LG 12. If a capacitor with capacitance of 22 µF is connected to SREGO, use a phase compensation capacitor between SREGO and SREGC when the load is 5 mA (6 mA for SREG2) or lower. The output voltage values shown in the table assume that external resistance is connected as follows: SREGI1 = 3.0 V to 3.3 V, 65.14KΩ between SREGO1 and SREGC1, 34.86KΩ between SREGC1 and GND. SREGI2 = 3.0 V to 3.3 V, 54.46KΩ between SREGO2 and SREGC2, 45.54KΩ between SREGC2 and GND. SREGI3 = 3.0 V to 3.3 V, 73.84KΩ between SREGO3 and SREGC3, 26.16KΩ between SREGC3 and GND. 13. Calculated by the right formula for input offset: SR1OFST = (Vref x 0.77) - (SREGO1 ÷ (100k ÷ 34.86k)) 14. Calculated by the right formula for input offset: SR2OFST = (Vref x 1) - (SREGO1 ÷ (100k ÷ 45.54k)) 15. Calculated by the right formula for input offset: SR3OFST = (Vref x 0.58) - (SREGO1 ÷ (100k ÷ 26.16k)) 16. Connect a transistor with gate capacity of 300 pF or smaller to REG2G. 17. When VGATESEL1 is Low and VGATESEL2 is Low, I/O = 3 mA or higher is certified by specification. 18. When VGATESEL1 is High and VGATESEL2 is Low, I/O = 3 mA or higher is certified by specification. 19. When HVB is 4.2 V and the load from V_STDBY is 0.5 µA or higher. 18730 8 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS STATIC Table 3. Static Electrical Characteristics (continued) Characteristics noted under conditions VBATT = 1.2 V, VO1_SENSE = 2.4 V, VGATE= 6.0 V, fCLK = 176.4 kHz unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 27°C under nominal conditions unless otherwise noted. Characteristic Reset Circuit Reset Voltage 1 Reset Voltage 2 Hysteresis Voltage 1 (@RST1) Hysteresis Voltage 2 (@RST2) PGOOD (VPGOOD = 2.4 V) (Isink = 2 mA) PGOOD_DELAY (Isink = 100 µA) High Level Threshold Voltage Low Level Threshold Voltage PGOOD_DELAY Pull-Up Resistance V_STDBY Output Resistance Output Resistance (VO1_SENSE) Output Resistance (VBATT) LSWO Output Resistance Output Resistance VGATE_EXT VGATE_EXT Output Voltage (Isource = 100 µA) (Isink = 100 µA) Logic Input "H" Level Input Voltage (20) "L" Level Input Voltage "H" Level Input Voltage (20) (21) Symbol Min Typ Max Unit VRST1 VRST2 VHYRS1 VHYRS2 IPGOOD1,2 VPGOOD1,2 VOLCR1,2 VIHCR1,2 VILCR1,2 RPUPRC1,2 RVO1_SENSE RVB RLSWO 0.85 x VO1_SENSE 0.80 x VO1_SENSE 40 50 0 0 0 1.25 0.75 50 0.88 x 0.91 x VO1_SENSE VO1_SENSE 0.85 x 0.90 x VO1_SENSE VO1_SENSE 78 75 1.42 1.00 100 115 100 10 0.5 0.7 1.65 1.15 150 V V mV mV µA V V V V KΩ W - 30 200 42 45 400 50 W V VOHEXTG VOLEXTG VGATE x 0.9 0 VGATE VGATE x 0.1 VIHVS VILVS VIH VIL VIHVB VILVB IIH IIL RPUP RPDW V_STDBY - 0.2 1.5 VB - 0.2 -1.0 -1.0 410 330 590 480 0.2 0.4 0.2 1.0 1.0 770 625 V V V V V V µA µA KΩ KΩ "L" Level Input Voltage (21) "H" Level Input Voltage (22) "L" Level Input Voltage (22) "H" Level Input Current (20), (22) "L" Level Input Current (22), (23) Pull Up Resistance (24) Pull Down Resistance (25) Notes 20. 21. 22. 23. 24. 25. Applied to WAKEB1 ~ 4 and SEQ_SELECT. Applied to CLEAR, SLEEP, EXT_CLOCK, DATA, STRB and SCKIN. Applied to VGATESEL1 and 2. Applied to WAKEB1 ~ 3, CLEAR, SLEEP, EXT_CLOCK, DATA, STRB, SCKIN and SEQ_SELECT. Applied to WAKEB4. Applied to CLEAR, SLEEP, EXT_CLOCK, DATA, STRB and SCKIN. 18730 Analog Integrated Circuit Device Data Freescale Semiconductor 9 ELECTRICAL CHARACTERISTICS DYNAMIC DYNAMIC Table 4. Dynamic Electrical Characteristics Characteristics noted under conditions VBATT = 1.2 V, VO1_SENSE = 2.4 V, VGATE = 6.0 V, fCLK = 176.4 kHz unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 27°C under nominal conditions unless otherwise noted. Characteristic OSCILLATOR Internal Oscillation Frequency MICRO CONTROLLER INTERFACE Clock Signal Input (26) Serial Interface (Refer to Figure 5, Serial Interface Timing Diagrams) DATA Set Up Time DATA Hold Time SCKIN Clock Frequency SCKIN 'H' Pulse Width SCKIN 'L' Pulse Width SCKIN Hold Time STRB Set Up Time STRB Pulse Width Notes 26. Duty 50%. ts th fsck twckh twckl thck tssb twsb 20 20 50 50 50 50 50 6.0 nsec nsec MHz nsec nsec nsec nsec nsec fCLK 176.4 kHz fICK 150 200 250 kHz Symbol Min Typ Max Unit 18730 10 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS TIMING DIAGRAMS WAKE1~4(int) EXT_CLOCK INT VO1_SENSE EXT (Serial setting) V_STDBY VBATT VBATT VBATT VBATT VGATE VGATE VBATT VO1_SENSE VBATT PGOOD1(Int) PGOOD_DELAY set value PGOOD1 VO1_SENSE VO1_SENSE VO1_SENSE VBATT VO1_SENSE VBATT VOUT1 VO2_SENSE VO2_SENSE VO2_SENSE VOUT2 VO1_SENSE PGOOD_DELAY set value PGOOD2(Int) VO1_SENSE PGOOD1 SEQ_SELECT setting SREG1~3 DATA DATA STRB SEQ_SELECT setting CLEAR SLEEP Standby Mode Start-Up *1: When using Ni_mh. High-Z when using Li_ion. Operation Mode Standby Mode Figure 4. Power Supply Start-Up Timing Diagram 18730 Analog Integrated Circuit Device Data Freescale Semiconductor 11 ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS tSSB SCKIN tS DATA tWCKH tWCKL tHCK tH A3 A2 D0 tWSB STRB Figure 5. Serial Interface Timing Diagrams Table 5. Serial Interface Functions Register Name Address 0 CLEAR, SLEEP 1 2 3 4 5 6 7 Power Mode Clock Select VO1_SENSE VO2_SENSE SREG1 SREG2 SREG3 1000 0001 0010 0011 0100 0101 0110 0111 CLEAR PSW1 Ext / Int MSB MSB MSB MSB MSB SLEEP PSW2 DATA1 Reserved PGOOD1 Reserved VOUT2 Reserved SREG1 Reserved SREG2 DATA2 Reserved SREG3 Reserved PGOOD2 VG_Duty[0] S_Off_VO1_SENSE S_Off_VO2_SENSE Reserved LSB LSB CP Off EXTG On Half Freq RSTB sleep S_Off_VGATE VG_Duty[3] VG_Duty[2] VG_Duty[1] VO1_SENSE Output Voltage VO2_SENSE Output Voltage SREG1 Output Voltage SREG2 Output Voltage SREG3 Output Voltage LSB LSB LSB Twelve bits immediately before start-up of STRB are always effective. Upon power on, the internal power on reset works to initialize the registers. Serial data is fetched in the Table 6. Block Operation INPUT WAKE (Int) L H H H H H PGOOD1 (Int) X L H H H H PGOOD1 X L L L H H PGOOD2(Int) X L L L H H SEQ_SELECT X L L H L H order of Add_[3], Add_[2], ..., Add_[0], DATA1_[3], DATA1_[2], ...., DATA2_[0]. OUTPUT VGATE O O O O O VO1_SENSE O O O O O VO2_SENSE O O VOUT1,2 O O REG 1,2,3 O O O O : Operation, - : Stop, X : Don’t care 18730 12 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS Table 7. Start-Up Sequence Settings SEQ_SELE CT V_STDBY GND CLEAR/ SLEEP PGOOD2(Ext) PGOOD1(Ext) Series Regulators PGOOD2(Int) PGOOD1(Int) 18730 Analog Integrated Circuit Device Data Freescale Semiconductor 13 FUNCTIONAL DESCRIPTION INTRODUCTION FUNCTIONAL DESCRIPTION INTRODUCTION The 18730 power management integrated circuit provides five independent output voltages for the micro controller from either a single cell Li-Ion or from a single cell Ni-MH or dry cell. The PMIC includes two DC to DC converters and three low drop out linear regulators. The output voltage for each of the five output voltages is set independently through a 3-wire serial interface. The PMIC has multiple wakeup, sleep, and reset modes to minimize power consumption for portable equipment. In single cell Li-Ion applications two DC-DC converters are configured as buck regulators. In single cell Ni-MH or dry cell applications, one DC-DC converter is configured as a boost regulator, and the other as buck-boost regulator. FUNCTIONAL PIN DESCRIPTION CLEAR PIN (CLEAR) This Clear input signal makes clear internal latches for WAKE signal holding. The WAKE control circuit can not receive another WAKE input until the latch is cleared by this Clear input. Channel-1 or Channel-2 DC/DC converter as ‘VO1_SENSEor VO2_SENSE. VOLTAGE OUTPUT PINS (VOUT1, VOUT2) Output ‘VO1_SENSE or ‘VO2_SENSE’ voltage controlled internal power switch. WAKE SIGNAL PINS (WAKE1B, WAKE2B, WAKE3B, WAKE4B) ... ACTIVE LOW Any one WAKE input signal of these four WAKE inputs awakes this device from sleep mode. The WAKE signals can be made with external low side mechanical switch and resistance that is pulled up to VSTB rail. POWER INPUT PINS (VIN1, VIN2) The power input pins (VIN1, VIN2) are drain pins on the top side FET of the DC/DC converter switcher. They are the power input for the buck converter and output for the boost converter. LOW-SIDE SWITCH OUTPUT PIN (LSWO) Low-Side switch output that is turned on with ‘CLEAR’ signal. It can be used for external key input latches clear. SWITCHING PINS (SW1, SW2) Switching Pins (SW1, SW2) are the output of the half bridge and connect to the external inductance. LOW VOLTAGE BATTERY PIN (LVB) This input pin is used for temporarily power supply while wake up for 1cell Ni-MH battery or 1 cell dry cell battery (= Low Voltage Battery) use. It has to be connected to VB rail. When Li-Ion battery is used, the pin has to be open. POWER GROUND PINS (PGND1, PGND2, GNDGATE) Ground level node for DC/DC converter and Charge Pump portion. HIGH VOLTAGE BATTERY PIN (HVB) This input pin is used for temporarily power supply while wake up for Li-Ion battery (= High Voltage Battery) use. It has to be connected to the VB rail. When a Ni-MH battery is used, the pin has to be connected to ground level. INVERTED RESET OUTPUT PINS (PGOOD1, PGOOD2) Reset signal output for external MPU or the something controller. PGOOD1 keeps ‘Low’ level while the VO1_SENSE voltage is less than internal reference voltage. PGOOD2 follows to VO2_SENSE voltage. STANDBY VOLTAGE PIN (V_STDBY) Standby Voltage is made from LVB or HVB that depends on which battery is used. This voltage is used for internal logic and analog circuit at standby (sleep) mode temporarily before ‘VO1_SENSE’ voltage is established. RESET DELAY CAPACITOR PINS (PGOOD1_DELAY, PGOOD2_DELAY) The capacitor connected to this pin decides delay time to negate the Reset signal from exceeding the reference voltage level. VOLTAGE INPUT PINS (VO1_SENSE, VO2_SENSE) This power supply input pin named ‘VO1_SENS or VO2_SENSE’ is for internal logic and analog circuits and for input of ‘VOUT1’ output via power switch. Input for ‘VOUT2’ is ‘VO2_SENSE_IN’ pin. It is supplied from the output of RESET 1 ADJUSTMENT PIN (RESET1_TH) Used to adjust the reset level with external resistance which is connected to VO1_SENSE for PGOOD1. 18730 14 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION DUTY CONTROL PINS (DMAX1, DMAX2) Connected external voltage to this pin via capacitance can control the duty of DC/DC converter switching. Use of the pin for this is not recommended. REGULATOR CONTROL PINS (SREGC1, SREGC2, SREGC3) Feed back pin for each series regulators. This pin voltage is compared with internal reference voltage. Input the feed back voltage that divided SREGO voltage by resistances. REFERENCE FEEDBACK PINS (EAOUT1, EAOUT2) Output node of internal error amp. for DC/DC converter 1 and 2. Used for phase compensation. REGULATOR OUTPUT PINS (SREGO1, SREGO2, SREGO3) Series regulator output pins. All output voltages can be variable with internal DAC via serial I/F. INPUT MINUS PINS (EAIN1, EAIN2) Minus input of internal error amp. for DC/DC converter 1 and 2. Used for phase compensation. REGULATOR INPUT PINS (SREGI1, SREGI2, SREGI3) Series regulator power input pins. To be connected to battery voltage in general. CHARGE PUMP CAPACITOR PIN (CH_PUMP) In case of use higher voltage than VGATE externally, connect capacitance and diodes between VGATE. The charge pump structure can output VGATE + VB - 2 x VF voltage. There is no meaning for Ni-MH or dry cell battery, because the VB voltage is almost same as 2 x VF voltage. Recommend to use for Li-Ion battery use. GROUND PIN (GND) Ground pin for logic and analog circuit portion (not power portion). Recommend to connect to clean ground which separated with power ground line. GATE VOLTAGE PIN (VGATE) Output pin of boost converter for gate drive voltage. The output voltage is decided by VGSEL input. REFERENCE VOLTAGE PIN (VREF) Output of internal reference voltage. It can be used externally. Output current capacity is less than 300 µA. SWITCHING FOR GATE VOLTAGE PIN (SWGATE) Switching pin for VGATE boost converter. Connect to external inductance. DATA INPUT PIN (DATA) Serial data input pin for the serial interface. The last 12 bits received before the strobe signal’s low to high transition are latched. BATTERY VOLTAGE PIN (VBATT) Power supply input that connects to Ni-MH or Dry cell or Li-Ion battery. STROBE PIN (STRB) Strobe signal input pin for serial interface. It latches the 12 bits of data input to the internal control registers. VGATE SELECT PINS (VGATESEL1, VGATESEL2) VGATE output voltage is decided with these two bits input. SERIAL CLOCK PIN (SCKIN) Clock input pin for serial interface. Input data are taken in to I/F with this clock. VOLTAGE INPUT FOR POWER SWITCH 2 PIN (VO2_SENSE_IN) Input of VOUT2 output via power switch. Connect to VO2_SENSE pin externally. WATCH DOG TIMER PIN (WATCHDOG) Watch dog timer prevent unstable wake up (flips between wake-up and failure). If there is no ‘CLEAR’ input after any WAKEnB input before this WATCHDOG is expired, this device moves to ‘SLEEP’ mode to prevent wake failure hanging-up situation. STEP DOWN FET GATE DRIVE PINS (HG, LG) Gate drive output pins for external FETs to use DC/DC converter 2 as Buck / Boost converter. GATE SWITCH PIN (VGATE_EXT) Gate drive output pin for external low side switch. It can be used for power switch turning On/OFF for remote controller part. SEQUENCE SELECT PIN (SEQ_SELECT) Select judgement Reset channel for wake-up complete with this input. If this input level is V_STDBY voltage, this device judges the wake-up completion with Reset2 (DC/ DC2). If it is Ground, judge with Reset1 (DC/DC1). See Table 7, on page 13. 18730 Analog Integrated Circuit Device Data Freescale Semiconductor 15 FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION CLOCK INPUT PIN (EXT_CLOCK) Clock input pin for internal switching part. This device has a oscillator internally, but can use this input clock for internal switching frequency. It is selected by Clock select bit. See Table 19, on page 25. SLEEP MODE PIN (SLEEP) The sleep input signal puts the device in sleep mode. All output voltages are down, and internal current consumption will be minimum. 18730 16 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES START-UP CONTROL INPUT (SYSTEM CONTROL) The latch is set at the rising edge of any WAKE1B-4B input pin, and WAKE(int) goes High. WAKE1~4B inputs consist of OR logic. At this time, the input pin which went Low keeps latched until CLEAR goes High. After the latch is reset by CLEAR, WAKE(int) goes Low when SLEEP goes High. The latch is also cleared and WAKE(int) goes Low when SLEEP goes High before the latch is cleared by CLEAR. In this case, CLEAR keeps negated while PGOOD1, 2(Ext) is Low. SLEEP keeps negated while PGOOD1, 2(Ext) is Low or CLEAR is High. The period of time for which CLEAR and SLEEP are negated can be set by the SEQ_SELECT pin. Refer to Truth Table 5, on page 12 for the correspondence between the SEQ_SELECT pin settings and negation period. If SLEEP goes High to place the chip into the standby mode while any of the WAKEB pins is Low, the chip can be awakened again. This may happen if, when an WAKEB pin and LSWO are connected, SLEEP goes High earlier than the period of time (*1) specified by the external component of the WAKEB pin. Also, if the period of time after WAKE(int) goes High until CLEAR goes High from Low is longer than the time specified by WATCHDOG, internal sleep will start up to place the chip into the standby mode. (*1: It is 30 µsec when a capacitor is not connected as the external component.) WAKEB CLEAR Time specified by WATCHDOG WATCHDOG WAKE(Int) Figure 6. Start-Up Timing Diagram STANDBY POWER SUPPLY CIRCUIT LSWO CLEAR VBATT VBATT HVB VO1_SENSE Standby Power PGOOD1(Int) Supply Control PGOOD1 LVB V_STDBY V_STDBY When using Li_ion, leave LVB open, and shortcircuit HVB and VBATT. Short-circuit VBATT and LVB, and connect a Schottky diode between VBATT and V_STDBY only when using Ni_mh. Figure 7. Standby Power Supply Circuit Diagram When PGOOD1(int) is Low, output LVB voltage to LSWO is open. When PGOOD1(int) is High and CLEAR is V_STDBY pin. When PGOOD1(int) is High, output High, LSWO output voltage turns GND. When PGOOD1(int) VO1_SENSE voltage to V_STDBY pin. When CLEAR is Low, is Low and PGOOD1 is High, discharge the external 18730 Analog Integrated Circuit Device Data Freescale Semiconductor 17 FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES capacitor which is connected to V_STDBY. When using Ni_mh, short-circuit VBATT and LVB to external components and HVB to GND. When using Li_ion, short-circuit HVB to VBATT, and leave LVB open. When using Ni_MH, the VB voltage is output from V_STDBY in Standby mode. When using Li-Ion, 50% of the VBATT voltage is output to V_STDBY pin in Standby Mode. Table 8. HVB and LVB Connection MODE Li_ion Ni_mh HVB VBATT(27) GND LVB open VBATT(27) Notes 27. Externally connect to VBATT. Table 9. V_STDBY and LSWO Operation INPUT WAKE(Int) L H H H PGOOD2(Int) X L H H CLEAR X X L H OUTPUT V_STDBY VBATT VBATT VO1_SENSE VO1_SENSE LSWO Z Z Z L Z : High Impedance, X : Don’t care RESET CIRCUIT PGOOD1_DELAY, PGOOD2_DELAY VO1_SENSE, VO2_SENSE VGATE VO1_SENSE PGOOD1, 2 RESET1_TH (PGOOD1 side only) VO1_SENSE Reset Control PGOOD1, 2B(Int) PGOOD1_DELAY, PGOOD2_DELAY BANDGAP REFERENCE Figure 8. Reset Circuit Block Diagram When the VO1_SENSE or VO2_SENSE voltage is higher than the reference value, PGOOD1 or 2B goes High. When PGOOD1(int) is Low and PGOOD1 is High, SLEEP(int) is forced to place the chip into the standby mode. Connect a capacitor between RESET1_TH and PGOOD_DELAY. The capacitor is not necessary if a resistor of 330KΩ or less is inserted between RESET1_TH and VO1_SENSE for reset adjustment Connect the capacitor between RESET1_TH and PGOOD as directed below. When SEQ_SELECT is Low:Between RESET1_TH and PGOOD1_DELAY When SEQ_SELECT is High:Between RESET1_TH and PGOOD2_DELAY Use a capacitor with approximately half of the capacitance between PGOOD_DELAY and GND 18730 18 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES PGOOD1(Int) PGOOD1 SLEEP(Int) Figure 9. Reset Timing Diagram POWER SUPPLY VO1_SENSE, VO2_SENSE: NI_MH The VBATT voltage rises and is output to VIN1. When PGOOD2(int) is High, the power switch turns ON to output the VO1_SENSE voltage to VOUT1. Capacitance value which is connected to VO1_SENSE should be higher than the capacitor connected to VOUT1. Table 10. Output Voltage of VO1_SENSE Address: 0011(28) B7 L L L L L L L H H H H H H H H B6 L L L L L L H L L L L L L H H B5 L L L L L H L L L L L L H L H B4 L L L L H L L L L L L H L L H B3 L L L H L L L L L L H L L L H B2 L L H L L L L L L H L L L L H The VBATT voltage rises or falls and is output to VIN2. When PGOOD2(int) is High, the power switch turns ON to output the VO2_SENSE_IN voltage to VOUT2. If you turn DDC2 OFF using the register, the power switch 2 also turns OFF. Capacitance value which is connected to VO2_SENSE_IN should be higher than the capacitor connected to VOUT2. B1 L H L L L L L L H L L L L L H S_Off_VO1_SENSE X X X X X X X X X X X X X X X VO1_SENSE [V](29) 1.613 1.625 1.638 1.663 1.713 1.813 2.013 2.413 2.425 2.438 2.463 2.513 2.613 2.813 3.200 Notes 28. All combinations of input are not included. 29. Operation is not guaranteed when VO1_SENSE input voltage is 1.8 V or lower. By connecting a diode between VIN1 and VO1_SENSE, VIN1 can output voltage higher (with the voltage difference Vf) than VO1_SENSE. 18730 Analog Integrated Circuit Device Data Freescale Semiconductor 19 FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES Table 11. Output Voltage of VO2_SENSE Address: 0100(33) B7 L L L L L L L H H H H H H H H B6 L L L L L L H L L L L L L H H B5 L L L L L H L L L L L L H L H B4 L L L L H L L L L L L H L L H B3 L L L H L L L L L L H L L L H B2 L L H L L L L L L H L L L L H B1 L H L L L L L L H L L L L L H S_Off_VO2_SENSE X X X X X X X X X X X X X X X VO2_SENSE [V] 0.805 0.811 0.816 0.827 0.849 0.893 0.980 1.155 1.161 1.166 1.177 1.199 1.243 1.330 1.500 Notes 30. All combinations of input are not included POWER SUPPLY VO1_SENSE, VO2_SENSE: LI-ION The VBATT voltage falls and is output to VO1_SENSE. When using Li_ion, duty limit due to DMAX1 is not applied to the switch. When PGOOD2(int) is High, the power switch turns ON to output the VO1_SENSE voltage to VOUT1. Capacitance value which is connected to VO1_SENSE should be higher than the capacitor connected to VOUT1. The VBATT voltage falls using only the internal transistor and is output to VO2_SENSE. When using Li_ion, duty limit due to DMAX2 is not applied to the switch, and HG and LG are Low. When PGOOD2(int) is High, the power switch turns Table 12. Output Voltage of SREG1 Address: 0101(31) B7 L L L L L L B6 L L L L L L B5 L L L L L H B4 L L L L H L B3 L L L H L L ON to output the VO2_SENSE_IN voltage to VOUT2. If you turn DDC2 OFF using the register, the power switch 2 also turns OFF. Capacitance value which is connected to VO2_SENSE_IN should be higher than the capacitor connected to VOUT2. SERIES PASS POWER SUPPLY The series pass outputs the SREGI1 voltage to SREGO1, the SREGI2 voltage to SREGO2, and the SREGI3 voltage to SREGO3. If you use MOSFET as the external component in this case, connect the gate to SREG2G. B2 L L H L L L B1 L H L L L L Reserved H H H H H H SREG1 [V](33) 0.865 0.880 0.895 0.926 0.986 1.107 18730 20 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES Table 12. Output Voltage of SREG1 Address: 0101(31) B7 L H H H H H H H H B6 H L L L L L L H H B5 L L L L L L H L H B4 L L L L L H L L H B3 L L L L H L L L H B2 L L L H L L L L H B1 L L H L L L L L H Reserved H H H H H H H H H SREG1 [V](33) 1.349 1.833 1.848 1.863 1.893 1.954 2.075 2.317 2.800 Notes 31. All combinations of input are not included. 32. The SREG1 and 3 output voltages are determined by the combination of external resistances connected to SREGC1 and 3 (65.14KΩ between SREGO1 and SREGC1, 34.86KΩ between SREGC1 and GND, 73.84KΩ between SREGO3 and SREGC3, and 26.16KΩ between SREGC3 and GND). Table 13. Output Voltage of SREG2 Address: 0110(33) B7 L L L L L L L L H H H H H H H H H B6 L L L L L L L H L L L L L L L H H B5 L L L L L L H L L L L L L L H L H B4 L L L L L H L L L L L L L H L L H B3 L L L L H L L L L L L L H L L L H B2 L L L H L L L L L L L H L L L L H B1 L L H L L L L L L L H L L L L L H B0 L H L L L L L L L H L L L L L L H SREG2 [V] 0.011 0.022 0.033 0.055 0.098 0.186 0.361 0.711 1.411 1.422 1.433 1.455 1.498 1.586 1.761 2.111 2.800 Notes 33. All combinations of input are not included. Table 14. Output Voltage of SREG3 Address: 0111(34) B7 L B6 L B5 L B4 L B3 L B2 L CP Off X EXTG On X SREG3 [V](35) 2.080 18730 Analog Integrated Circuit Device Data Freescale Semiconductor 21 FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES Table 14. Output Voltage of SREG3 Address: 0111(34) B7 L L L L L H H H H H H H B6 L L L L H L L L L L H H B5 L L L H L L L L L H L H B4 L L H L L L L L H L L H B3 L H L L L L L H L L L H B2 H L L L L L H L L L L H CP Off X X X X X X X X X X X X EXTG On X X X X X X X X X X X X SREG3 [V](35) 2.091 2.102 2.125 2.170 2.260 2.440 2.451 2.462 2.485 2.530 2.620 2.800 Notes 34. All combinations of input are not included. 35. The SREG1 and 3 output voltages are determined by the combination of external resistances connected to SREGC1 and 3 (65.14KΩ between SREGO1 and SREGC1, 34.86KΩ between SREGC1 and GND, 73.84KΩ between SREGO3 and SREGC3, and 26.16KΩ between SREGC3 and GND). VG GENERATOR VBATT VGATE VGATE Start Up VGATE VGATE Step-Up Pre Driver SWGATE VBATT GNDGATE VG_select VG_duty Figure 10. Circuit when using a Step-Up Converter When WAKE (int) goes High from Low, the start-up circuit raises the VB voltage and outputs it to VGATE, then outputs the VGATE voltage when PGOOD1 (int) goes High. The charge pump circuit can be used for both Ni_mh and Li_ion by setting the necessary registers. The charge pump circuit is disabled by default. The VGATE voltage can be set in the range of 6 V to 4.5 V according to the combination of VGATESEL1 and 2 pin connections. Refer to Table 16, VGATE Voltage Settings and VGATESEL1 and 2 Pin Connection on page 23 for the VG voltage settings. When using a charge pump, please refer to Figure 11. 18730 22 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES VBATT CH_PUMP VGH VBATT VGATE Start Up VGATE VGATE Step-Up Pre Driver SWGATE VBATT CPoff VGATE VGATE GNDGATE VGATE_SELECT VG_duty Figure 11. Circuit When Using a Charge Pump Table 15. VGATE Duty Settings Address : 0010 Ext/Int X X X X X X X X X Half Freq X X X X X X X X X RSTB sleep X X X X X X X X X S_Off_VG X X X X X X X X X VG_Duty[3] L L L L H H H H H VG_Duty[2] L L L H L L L H H VG_Duty[1] L L H L L L H L H VG_Duty[0] L H L L L H L L H Duty 90 % 86 % 82 % 74 % 58 % 54 % 50 % 42 % 30 % Table 16. VGATE Voltage Settings and VGATESEL1 and 2 Pin Connection VGATESEL1 GND GND VBATT VBATT VGATESEL2 GND VBATT GND VBATT VGATE [V] 6.0 5.5 5.0 4.5 18730 Analog Integrated Circuit Device Data Freescale Semiconductor 23 FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS LOGIC COMMANDS AND REGISTERS REGISTER MAPPINGS Table 17. CLEAR and SLEEP Control Register 1000 Bit Name Default 3 CLEAR 0 2 SLEEP 0 Data1 1 Reserved 0 0 Reserved 0 3 Reserved 0 2 Reserved 0 Data2 1 Reserved 0 0 Reserved 0 CLEAR: CLEAR Control 1 = CLEAR is high 0 = CLEAR is low SLEEP: SLEEP Control 1 = SLEEP is high 0 = SLEEP is low Reserved: Freescale defined register *1 1 = Forbidden 0 = Required Reserved: Freescale defined register *1 1 = Forbidden 0 = Required Reserved: Freescale defined register *1 1 = Forbidden 0 = Required Table 18. Power Mode Register 0001 Bit Name Default 3 PSW1 1 2 PSW2 1 Data1 1 PGOOD1 0 0 VOUT2 1 Reserved : Freescale defined register *1 1 = Forbidden 0 = Required Reserved : Freescale defined register *1 1 = Forbidden 0 = Required Reserved: Freescale defined register *1 1 = Forbidden 0 = Required Note: Do NOT change Reserved Register from default value. *1: Data write to this address (1000) is allowed for the most significant two bits only. The least significant 6 bits are only used for the factory test. When writing data, always write 0 to these six bits. Data2 3 SREG1 1 2 SREG2 1 1 SREG3 1 0 PGOOD2 0 PSW1: VOUT1 Power Switch control 1 = Power Switch on 0 = Power Switch off PSW2: VOUT2 Power Switch control 1 = Power Switch on 0 = Power Switch off PGOOD1: PGOOD1 Mask *1 1 = PGOOD1 mask on 0 = PGOOD1 mask off VO2_SENSE: DC/DC Converter Channel 2 output Control *2 1 = DDC2 on 0 = DDC2 off SREG1: Series Pass Regulator Channel1 output Control 1 = Regulator on 0 = Regulator off SREG2: Series Pass Regulator Channel2 output Control *3 1 = Regulator off 0 = Regulator on SREG3: Series Pass Regulator Channel3 output Control 1 = Regulator on 0 = Regulator off PGOOD2: PGOOD2 Mask *1 1 = PGOOD2 mask on 0 = PGOOD2 mask off *1: When switching the output voltage of VO1_SENSE (2), write 1 to the PGOOD1 (2) Mask bit in advance to fix the rest output to High for preventing erroneous operation. *2: When turning DDC2 OFF, set the PGOOD2 bit to High to Mask PGOOD2. If you turn DDC2 OFF, the power switch 2 also turns OFF. 18730 24 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS Table 19. Clock Select Register 0010 Bit Name Default 3 Ext/Int 0 2 Half Freq 0 Data1 1 RSTB sleep 1 0 S_Off_VG 0 3 VG_Duty [3] 0 2 VG_Duty[2] 0 Data2 1 VG_Duty[1] 0 0 VG_Duty[0] 0 Ext / Int: Clock Select control 1 1 = External Clock 0 = Internal Clock 2FS: Clock Select control 2 1 = 2FS on 0 = 2FS off RSTB Sleep: RSTB Sleep Monitor *1 1 = RSTB SLEEP Monitor off 0 = RSTB SLEEP Monitor on S_Off_VG: VG Top side transistor off 1 = Synchronous Rectification Off 0 = Synchronous Rectification On VG_Duty[3]: VG Duty Control MSB 1 = VG Duty[3] is high 0 = VG Duty[3] is low Table 20. VO1_SENSE Output Voltage Register 0011 Bit Name Default 3 VO1_SENSE [6] 1 2 VO1_SENSE [5] 0 Data1 1 VO1_SENSE [4] 0 0 VG_Duty[2]: VG Duty Control Bit 2 1 = VG Duty[2] is high 0 = VG Duty[2] is low VG_Duty[1]: VG Duty Control Bit1 1 = VG Duty[1] is high 0 = VG Duty[1] is low VG_Duty[0]: VG Duty Control LSB 1 = VG Duty[0] is high 0 = VG Duty[0] is low VG is controlled by PFM method. This register can change the duty by 16 steps. Refer to Table 15, VGATE Duty Settings on page 23 for the correspondence between the VG Duty maximum values and register settings. Data2 3 VO1_SENSE [2] 0 2 VO1_SENSE [1] 0 1 VO1_SENSE [0] 0 0 S_Off_VO1_SENSE 0 VO1_SENSE [3] 0 VO1_SENSE[6]: Reference DAC MSB 1 = VO1_SENSE[6] on 0 = VO1_SENSE[6] off VO1_SENSE[5]: Reference DAC Bit5 1 = VO1_SENSE5] on 0 = VO1_SENSE[5] off VO1_SENSE[4]: Reference DAC Bit4 1 = VO1_SENSE[4] on 0 = VO1_SENSE[4] off VO1_SENSE[3]: Reference DAC Bit3 1 = VO1_SENSE[3] on 0 = VO1_SENSE[3] off VO1_SENSE[2]: Reference DAC Bit2 1 = VO1_SENSE[2] on 0 = VO1_SENSE[2] off VO1_SENSE[1]: Reference DAC Bit1 1 = VO1_SENSE[1] on 0 = VO1_SENSE[1] off VO1_SENSE[0] on 0 = VO1_SENSE[0] off S_Off_VO1_SENSE: DDC1 Top side (Ni_mh) / Bottom side (Li_ion) transistor off 1 = Synchronous Rectification Off 0 = Synchronous Rectification On Refer to Table 10, Output Voltage of VO1_SENSE on page 19 for the correspondence between the output voltage and register settings. 18730 Analog Integrated Circuit Device Data Freescale Semiconductor 25 FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS Table 21. VO2_SENSE Output Voltage Register 0100 Bit Name Default 3 VO2_SENSE [6] 1 2 VO2_SENSE [5] 0 Data1 1 VO2_SENSE [4] 0 0 VO2_SENSE [3] 0 3 VO2_SENSE [2] 0 2 VO2_SENSE [1] 0 Data2 1 VO2_SENSE [0] 0 0 S_Off_VO2_SENSE 0 VO2_SENSE[6]: Reference DAC MSB 1 = VO2_SENSE[6] on 0 = VO2_SENSE[6] off VO2_SENSE[5]: Reference DAC Bit5 1 = VO2_SENSE[5] on 0 = VO2_SENSE[5] off VO2_SENSE[4]: Reference DAC Bit4 1 = VO2_SENSE[4] on 0 = VO2_SENSE[4] off VO2_SENSE[3]: Reference DAC Bit3 1 = VO2_SENSE[3] on 0 = VO2_SENSE[3] off VO2_SENSE[2]: Reference DAC Bit2 1 = VO2_SENSE[2] on 0 = VO2_SENSE[2] off Table 22. Regulator1 Output Voltage Register 0101 Bit Name Default 3 SREG1_V[6] 1 2 SREG1_V[5] 1 Data1 1 SREG1_V[4] 1 0 VO2_SENSE[1]: Reference DAC Bit1 1 = VO2_SENSE[1] on 0 = VO2_SENSE[1] off VO2_SENSE [0]: Reference DAC LSB 1 = VO2_SENSE [0] on 0 = VO2_SENSE [0] off S_Off_VO2_SENSE: DDC2 Top side & LG (Ni_mh) / Bottom side (Li_ion) transistor off 1 = Synchronous Rectification Off 0 = Synchronous Rectification On Refer to Table 11, Output Voltage of VO2_SENSE on page 20 for the correspondence between the output voltage and register settings. Data2 3 SREG1_V[2] 1 2 SREG1_V[1] 1 1 SREG1_V[0] 1 0 Reserved 1 SREG1_V[3] 1 SREG1_V[6]: Reference DAC MSB 1 = SREG1_V[6] on 0 = SREG1_V[6] off SREG1_V[5]: Reference DAC Bit5 1 = SREG1_V[5] on 0 = SREG1_V[5] off SREG1_V[4]: Reference DAC Bit4 1 = SREG1_V[4] on 0 = SREG1_V[4] off SREG1_V[3]: Reference DAC Bit3 1 = SREG1_V[3] on 0 = SREG1_V[3] off SREG1_V[2] : Reference DAC Bit2 1 = SREG1_V[2] on 0 = SREG1_V[2] off SREG1 [1]: Reference DAC Bit1 1 = SREG1_V[1] on 0 = SREG1_V[1] off SREG1_V[0]: Reference DAC LSB 1 = SREG1_V[0] on 0 = SREG1_V[0] off Reserved : Blank register bit (Freescale Pre-Defined Register) 1 = Preferred 0 = Forbidden Note: Do NOT change Reserved Register from default value. Refer to Table 12, Output Voltage of SREG1 on page 20 for the correspondence between the output voltage and register settings. 18730 26 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS Table 23. Regulator2 Output Voltage Register 0110 Bit Name Default 3 SREG2_V[7] 1 2 SREG2_V[6] 1 Data1 1 SREG2_V[5] 1 0 SREG2_V[4] 1 3 SREG2_V[3] 1 2 SREG2_V[2] 1 Data2 1 SREG2_V[1] 1 0 SREG2_V[0] 1 SREG2_V[7]: Reference DAC MSB 1 = SREG2_V[7] on 0 = SREG2_V[7] off SREG2_V[6]: Reference DAC Bit6 1 = SREG2_V[6] on 0 = SREG2_V[6] off SREG2_V[5]: Reference DAC Bit5 1 = SREG2_V[5] on 0 = SREG2_V[5] off SREG2_V[4]: Reference DAC Bit4 1 = SREG2_V[4] on 0 = SREG2_V[4] off SREG2_V[3]: Reference DAC Bit3 1 = SREG2_V[3] on 0 = SREG2_V[3] off SREG2_V[2]: Reference DAC Bit2 1 = SREG2_V[2] on 0 = SREG2_V[2] off SREG2_V[1]: Reference DAC Bit1 1 = SREG2_V[1] on 0 = SREG2_V[1] off SREG2_V[0]: Reference DAC LSB 1 = SREG2_V[0] on 0 = SREG2_V[0] off Refer to Table 13, Output Voltage of SREG2 on page 21 for the correspondence between the output voltage and register settings. Table 24. Regulator3 Output Voltage Register 0111 Bit Name Default 3 SREG3_V[5] 1 2 SREG3_V[4] 1 Data1 1 SREG3_V[3] 1 0 SREG3_V[2] 1 3 SREG3_V[1] 1 2 SREG3_V[0] 1 Data2 1 CP Off 1 0 EXTG On 1 SREG3_V[5]: Reference DAC MSB 1 = SREG3_V[5] on 0 = SREG3_V[5] off SREG3_V[4]: Reference DAC Bit4 1 = SREG3_V[4] on 0 = SREG3_V[4] off SREG3_V[3]: Reference DAC Bit3 1 = SREG3_V[3] on 0 = SREG3_V[3] off SREG3_V[2] : Reference DAC Bit2 1 = SREG3_V[2] on 0 = SREG3_V[2] off SREG3_V[1] : Reference DAC Bit1 1 = SREG3_V[1] on 0 = SREG3_V[1] off SREG3_V[0]: Reference DAC LSB 1 = SREG3_V[0] on 0 = SREG3_V[0] off CP Off: Charge Pump Control 1 = Charge Pump off 0 = Charge Pump on EXTG On: VGATE_EXT Control * 1 = VGATE_EXT is low (GND level) 0 = VGATE_EXT is high (VG level) EXTG On Register is assumed to use Pch FET as external MOSFET. If Nch FET will be used, Control logic should be inverted. Refer to Table 14, Output Voltage of SREG3 on page 21 for the correspondence between the output voltage and register settings. 18730 Analog Integrated Circuit Device Data Freescale Semiconductor 27 TYPICAL APPLICATIONS TYPICAL APPLICATIONS HVB LVB Driver VREF PGOOD1(Int) CLEAR LSWO VO1_SENSE VO1_SENSE PGOOD1 PGOOD1_DELAY VO1_SENSE RESET1_TH EAIN1 EAOUT1 VMODE VMODE PGOOD1(Int) VO1_SENSE VO1_SENSE BANDGAP REFERENCE VGATE POWER VO1_SENSE VGATE SWITCH1 PGOOD1(Int) REF1 PGOOD1(Int) VBATT VBATT VBATT LVB V_STDBY VOUT1 VREF VO1_SENSE VIN1 RESET Block 1 Step-UpDown DC/DC Converter CH1 PGND1 VBATT SW1 PGOOD1_DELAY or PGOOD2_DELAY VREF DMAX1 VO1_SENSE VGATE PGOOD2(Int) VGATE SWITCH2 POWER VOUT2 VO2_SENSE_IN VO2_SENSE VBATT VO1_SENSE PGOOD2(Int) PGOOD2 PGOOD2_DELAY EAOUT2 EAIN2 VREF DMAX2 VGATE SREGO1 REF3 SREGC1 SREGO2 SREGC2 SREGO3 SREGC3 V_STDBY WAKE1B WAKE2B WAKE3B RESET Block 2 HG REF2 LG Step-UpDown DC/DC Converter CH2 VIN2 SW2 PGND2 SREGI1 Series Pass Regulator1 SREGO1 VGATE SREG12 REF4 Series Pass Regulator2 VGATE SREGO2 SREG2G SREGI3 SREGO3 VO1_SENSE VBATT REF5 Series Pass Regulator3 VBATT EXT_CLOCK WAKE4B SEQ_SELECT DATA STRB SCKIN CLEAR SLEEP EXT_CLOCK GND VGATESEL1 VGATESEL2 WATCHDOG REF2 REF4 REF1 REF3 REF5 CONTROL PGOOD1(Int) CH_PUMP PGOOD2 CPoff VO1_SENSE VBATT (Int) VGATE VGATE SEQ_SELECT VG_select VG_duty Control Logic VBATT Step-Up SWGATE DC/DC Convertor GNDGATE VGATE On REF DAC VREF EXT gate On Buffer VGATE_EXT Figure 12. MPC18730 Typical Application Diagram (Ni-MH Battery) 18730 28 Analog Integrated Circuit Device Data Freescale Semiconductor TYPICAL APPLICATIONS VBATT HVB LVB Driver VREF PGOOD1(Int) VMODE VBATT VBATT LVB VBATT VREF LSWO VO1_SENSE CLEAR VO1_SENSE PGOOD1 PGOOD1_DELAY VO1_SENSE RESET1_TH EAIN1 EAOUT1 VMODE PGOOD1(Int) VO1_SENSE VO1_SENSE BANDGAP REFERENCE VGATE V_STDBY VOUT1 PGOOD1(Int) PGOOD1(Int) VO1_SENSE POWER SWITCH1 VGATE RESET Block 1 REF1 VO1_SENSE VBATT VIN1 SW1 Step-UpDown DC/DC Converter CH1 PGND1 PGOOD1_DELAY or PGOOD2_DELAY VGATE DMAX1 VO1_SENSE POWER PGOOD2(Int) VGATE SWITCH2 VOUT2 VO2_SENSE_IN VO2_SENSE VO1_SENSE PGOOD2(Int) PGOOD2 PGOOD2_DELAY EAOUT2 EAIN2 RESET Block 2 REF2 Step-UpDown DC/DC Converter CH2 HG LG VBATT VIN2 SW2 DMAX2 VGATE SREGO1 REF3 SREGC1 SREGO2 SREGC2 SREGO3 SREGC3 V_STDBY WAKE1B WAKE2B WAKE3B PGND2 SREGI1 Series Pass Regulator1 SREGO1 VGATE SREG12 REF4 Series Pass Regulator2 VGATE SREGO2 SREG2G SREGI3 SREGO3 VO1_SENSE VBATT REF5 Series Pass Regulator3 EXT_CLOCK VBATT WAKE4B SEQ_SELECT DATA STRB SCKIN CLEAR SLEEP EXT_CLOCK GND VGATESEL1 VGATESEL2 WATCHDOG REF2 REF4 REF3 REF5 REF1 CONTROL PGOOD1(Int) CH_PUMP VGH PGOOD2 CPoff VGATE VBATT (Int) SEQ_SELECT VO1_SENSE VG_select VG_duty Step-Up DC/DC Convertor VGATE VGATE VBATT SWGATE GNDGATE VGATE_EXT Control Logic On REF DAC VREF EXT gate On Buffer Figure 13. MPC18730 Typical Application Diagram (Li-Ion Battery) 18730 Analog Integrated Circuit Device Data Freescale Semiconductor 29 PACKAGING PACKAGE DIMENSIONS PACKAGING PACKAGE DIMENSIONS For the most current package revision, visit www.freescale.com and perform a keyword search using the “98A” listed below. EP (Pb-FREE) SUFFIX 64-PIN 0.5 mm pitch PLASTIC PACKAGE 98ARL10571D ISSUE B 18730 30 Analog Integrated Circuit Device Data Freescale Semiconductor PACKAGING PACKAGE DIMENSIONS EP (Pb-FREE) SUFFIX 64-PIN 0.5 mm pitch PLASTIC PACKAGE 98ARL10571D ISSUE B 18730 Analog Integrated Circuit Device Data Freescale Semiconductor 31 PACKAGING PACKAGE DIMENSIONS EP (Pb-FREE) SUFFIX 64-PIN 0.5 mm pitch PLASTIC PACKAGE 98ARL10571D ISSUE B 18730 32 Analog Integrated Circuit Device Data Freescale Semiconductor PACKAGING PACKAGE DIMENSIONS EP (Pb-FREE) SUFFIX 64-PIN 0.5 mm pitch PLASTIC PACKAGE 98ARL10571D ISSUE B 18730 Analog Integrated Circuit Device Data Freescale Semiconductor 33 REVISION HISTORY REVISION HISTORY REVISION 3.0 4.0 DATE 04/2006 8/2006 DESCRIPTION OF CHANGES • Changed 34 of 64 Pin names to align with Application Note, AN3247 Rev 1.0. • Minor changes to correct errors and inconsistencies. • Updated form and style. 18730 34 Analog Integrated Circuit Device Data Freescale Semiconductor How to Reach Us: Home Page: www.freescale.com E-mail: support@freescale.com USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. 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Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc., 2006. All rights reserved. MPC18730 Rev. 4.0 8/2006