PC33480PNA

Freescale Semiconductor Technical Data Document order number: MC33480 Rev 2.0, 1/2006 Smart Front Corner Light Switch (Triple 10 mΩ and Dual 35 mΩ) The 33480 is designed for low-voltage automotive and industrial lighting applications. Its five low RDS(ON) MOSFETs (three 10 mΩ, two 35 mΩ) can control the high sides of five separate resistive loads (bulbs). Programming, control, and diagnostics are accomplished using a 16-bit SPI interface. Each output has its own PWM control via SPI. The 33480 has highly sophisticated failure mode handling to provide high availability of the outputs. Its multiphase control and output edge shaping improves electromagnetic compatibility (EMC) behavior. The 33480 is packaged in a power-enhanced 12 x 12 nonleaded Power QFN package with exposed tabs. Features • • • • • • • • • • • Triple 10 mΩ and Dual 35 mΩ High-Side Switches 16-bit SPI Communication Interface with Daisy Chain Capability Current Sense Output with SPI-Programmable Multiplex Switch Digital Diagnosis Feature PWM Module with Multiphase Feature Fully Protected Switches Overcurrent Shutdown detection Power Net and Reverse Polarity Protection Low-Power Mode Fail Mode Functions including Autorestart feature External smart power switch control including current recopy 33480 HIGH-SIDE SWITCH Bottom View PNASUFFIX 98ARL10596D 24-TERMINAL PQFN ORDERING INFORMATION Device PC33480PNA/R2 Temperature Range (TA) -40°C to 125°C Package 24 PQFN 12 V 5.0 V 12 V 33480 VCC LIMP FLASHER IGN RSTB CLOCK CS SO SI SCLK CSNS GND OUT3 OUT4 OUT5 FETIN FETOUT Smart Switch VBAT CP OUT1 OUT2 Watchdog MCU Figure 1. 33480 Simplified Application DiagraM * This document contains information on a product under development. Freescale reserves the right to change or discontinue this product without notice. © Freescale Semiconductor, Inc., 2005. All rights reserved. INTERNAL BLOCK DIAGRAM INTERNAL BLOCK DIAGRAM VCC Vcc failure detection IUP Internal Regulator VBAT OV/UV/POR detections CP Charge Pump CS SO SI SCLK IDWN SPI 3.0 MHz PWM Module Logic Gate Drive drain/gate clamp OUT1 Overcurrent Detection Open Load Detection Overtemperature Detection CLOCK LIMP FLASHER IGN RSTB (fault management) OUT1 IDWN RDWN OUT2 OUT2 Overtemperature Prewarning OUT3 OUT3 OUT4 OUT4 OUT5 Selectable Output Current Recopy (Analog MUX) Vcc OUT5 CSNS FETIN Driver for External MOSFET FETOUT GND Figure 2. 33480 Simplified Internal Block Diagram 33480 2 Analog Integrated Circuit Device Data Freescale Semiconductor TERMINAL CONNECTIONS TERMINAL CONNECTIONS FLASHER FETOUT CLOCK RSTB SCLK LIMP VCC 13 12 11 10 CP GND 16 17 9 8 7 6 5 4 3 IGN 2 SO NC CS SI 24 14 GND 23 FETIN 1 CSNS GND 22 OUT1 Definition OUT5 18 15 VBAT 19 OUT4 20 OUT3 21 OUT2 Figure 3. 33480 Terminal Connections (Transparent Top View Of Package) Table 1. 33480 Terminal Definitions A functional description of each terminal can be found in the Functional Terminal Description section beginning on Page 17. Terminal Number 1 2 3 Terminal Name FETIN IGN RSTB Terminal Function Input Input Input Formal Name External FET Input Ignition Input (Active High) Reset This terminal is the current sense recopy of the external SMART MOSFET. This input wakes the device. It also controls the Outputs 1 and 2 in case of Fail mode activation. This terminal has a passive internal pulldown. This input wakes the device. It is also used to initialize the device configuration and fault registers through SPI. This digital terminal has a passive internal pulldown. This input wakes the device. The Fail mode can be activated by this digital input. This terminal has a passive internal pulldown. The PWM frequency and timing are generated from this digital clock input by the PWM module. This terminal has an active internal pulldown current source. The Fail mode can be activated by this digital input. This terminal has an active internal pulldown current source. No internal connection to this terminal. When this digital signal is high, SPI signals are ignored. Asserting this terminal low starts an SPI transaction. The transaction is signaled as completed when this signal returns high. This terminal has an active internal pullup current source. This digital input terminal is connected to the master microcontroller providing the required bit shift clock for SPI communication. This terminal has an active internal pulldown current source. 4 5 6 7 8 FLASHER CLOCK LIMP NC CS Input Input Input NC Input Flasher Input (Active High) Clock Input Limp Home Input (Active High) No Connect Chip Select (Active Low) 9 SCLK Input SPI Clock Input 33480 Analog Integrated Circuit Device Data Freescale Semiconductor 3 TERMINAL CONNECTIONS Table 1. 33480 Terminal Definitions (continued) A functional description of each terminal can be found in the Functional Terminal Description section beginning on Page 17. Terminal Number 10 11 12 13 14,17,23 15 16 18 22 19 20 21 24 Terminal Name SI VCC Terminal Function Input Power Output Output Ground Power Output Output Formal Name Master-Out SlaveIn Logic Supply Master-In SlaveOut External FET Gate Ground Battery Input Charge Pump Output 1 Output 5 Output 2 Output 3 Output 4 Current Sense Output Definition This data input is sampled on the positive edge of the SCLK. This terminal has an active internal pulldown current source. SPI Logic power supply. SPI data is sent to the MCU by this terminal. This data output changes on the negative edge of SCLK and when CS is high, this terminal is high impedance. This terminal controls an external SMART MOSFET by logic level. This output is also called OUT6. This terminal is the ground for the logic and analog circuitry of the device(1). Power supply terminal. This terminal is the connection for an external tank capacitor (for internal use only). Protected 35 mΩ high-side power output to the load. Protected 10 mΩ high-side power output to the load. SO FETOUT GND VBAT CP OUT1 OUT5 OUT2 OUT3 OUT4 CSNS Output Output This terminal is used to output a current proportional to OUT1:OUT5, FET in current, and it is used externally to generate a ground-referenced voltage for the microcontroller to monitor output current. OUT1:OUT5 and FET in choice is SPI programmable. Notes 1. The pins 14, 17 and 23 must be shorted on the board. 33480 4 Analog Integrated Circuit Device Data Freescale Semiconductor MAXIMUM RATINGS MAXIMUM RATINGS Table 2. Maximum Ratings All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device. Ratings ELECTRICAL RATINGS Overvoltage Test Range (all OUT[1:5] ON with nominal DC current) 2.0 Hours @ 25°C 1.0 Min @ 25°C Load Dump (400 ms) @ 25°C Reverse Polarity Voltage Range (all OUT[1:5] ON with nominal DC current) 2.0 Min @ 25°C VCC Supply Voltage OUT[1:5] Voltage Positive Negative (ground disconnected) Digital Input Current in Clamping Mode (SI, SCLK, CS, IGN, FLASHER, LIMP) SO and FETOUT Outputs Voltage FET in Input Current Outputs clamp energy using single pulse method (L=2mH; R=0; Vbat=14V @150°C initial) OUT[1,5] OUT[2:4] ESD Voltage (2) Human Body Model (HBM) Human Body Model (HBM) OUT [1:5] Charge Device Model (CDM) THERMAL RATINGS Operating Temperature Ambient Junction Peak Terminal Re-flow Temperature During Solder Mounting Storage Temperature THERMAL RESISTANCE Thermal Resistance, Junction to Case (4) RθJC 1.0 (3) Symbol Value Unit VBAT 20 27 40 VBAT - 15 VCC VOUT 40 -16 IIN VSO IFET in 5.0 - 0.3 to VCC + 0.3 10 -0.3 to 5.5 V V V V mA V mA mJ E1,5 E2,3,4 VESD ±2kV ±8kV TBD 85 300 V °C TA TJ TSOLDER TSTG - 40 to 125 - 40 to 150 260 - 55 to 150 °C °C °K/W Notes 2. ESD testing is performed in accordance with the Human Body Model (HBM) (CZAP = 100 pF, RZAP = 1500 Ω) and the Charge Device Model. 3. Terminal soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. If the qualification fails, TSOLDER will be changed for 240°C. 4. Typical value guaranteed per design. 33480 Analog Integrated Circuit Device Data Freescale Semiconductor 5 STATIC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics Characteristics noted under conditions 4.5 V ≤ VCC ≤ 5.5 V, 7.0 V ≤ VBAT ≤ 18 V, - 40°C ≤ TA ≤ 125°C, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted. Characteristic POWER INPUTS (VBAT, VCC) Battery Supply Voltage Range Full Performance & Short Circuit Extended Voltage Range (5) Battery Supply Undervoltage (UV flag is set ON) Battery Voltage Clamp (OV flaf is set ON) Battery Supply Power on Reset (If Vbat < 5.5V, Vbat = Vcc) VBAT Supply Current @ 25°C and VBAT = 12 V and VCC = 5 V Sleep State Current Normal Mode, IGN=5V, RSTB=5V, Outputs Open Digital Supply Voltage Range, Full Performance Digital Supply Undervoltage (VCC Failure) Standby Current Consumption on VCC @ 25°C and VBAT = 12 V Output OFF Supply Current Consumption on VCC and VBAT = 12 V No SPI 3.0 MHz SPI Communication LOGIC INPUT/OUTPUT (IGN, CS, CSNS, SI, SCLK, CLOCK, SO, FLASHER, RSTB, LIMP) Input High Logic Level (6) Input Low Logic Level (6) Ignition Threshold Level (IGN) Input Clamp Voltage (IGN) IIGN < 2.5 mA Input Forward Voltage (IGN) IIGN = -2.5 mA Input Active Pulldown Current for LIMP, SI, SCLK and CLOCK inputs Input Active Pullup Current (CS) Input Passive Pulldown Resistance (7) SO High-State Output Voltage IOH = 1.0 mA SO Low-State Output Voltage IOL = -1.6 mA Notes 5. In extended mode, the functionality is guaranteed but not the electrical parameters. 6. Valid for RSTB, SI, SCLK, CLOCK, FLASHER and LIMP terminals. 7. Valid for FLASHER, IGN and RSTB terminals. VSOL – 0.2 0.4 IDWN IUP RDWN VSOH 0.8 TBD – Vcc V VIGNfr - 2.0 5.0 5.0 100 – – – 200 -0.3 20.0 20.0 400 µA µA kΩ VIH VIL VIGNth VIGNcl 7.0 – 14.0 V 0.7 – 2.0 – – – – 0.3 4.0 Vcc Vcc V V IBATSLEEP IBAT VCC VCCUV – – 4.5 2.5 – 0.5 10.0 – 3.0 TBD – – 5.0 20.0 5.5 3.5 5.0 mA – – 1.0 5.0 µA mA V V µA VBATUV VBATCLAMP VBATPOR VBAT 7.0 6.0 5.0 41.0 – – – 5.3 47.0 4.2 18.0 20.0 6.0 53.0 5.0 V V V V Symbol Min Typ Max Unit IQCC ICC 33480 6 Analog Integrated Circuit Device Data Freescale Semiconductor STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics (continued) Characteristics noted under conditions 4.5 V ≤ VCC ≤ 5.5 V, 7.0 V ≤ VBAT ≤ 18 V, - 40°C ≤ TA ≤ 125°C, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted. Characteristic LOGIC INPUT/OUTPUT (IGN, CS, CSNS) (CONTINUED) SO Tri-State Leakage Current CS > 0.7 VCC Symbol Min Typ Max Unit ISOLEAK - 1.0 VCSNS 5.0 0.0 6.0 1.0 7.0 µA V Current Sense Output Clamp Voltage ICSNS