FT120 Datasheet Datasheet
Version 1.4
Document No.: FT_000646
Clearance No.: FTDI# 291
Future Technology Devices
International Ltd.
FT120
(USB Device Controller with
Parallel Bus IC)
The FT120 is a USB controller developed
independently with close consideration of the
industry classic, D12 chip. It communicates with a
microcontroller over the generic parallel interface.
The FT120 has the following advanced features:
USB 2.0 Full Speed compatible.
High performance USB device controller with
integrated SIE, endpoint buffer, transceiver
and voltage regulators.
Supports 8-bit parallel interface to external
microcontroller.
Supports DMA operation
Integrated 320 bytes of configurable endpoint
buffer
Ping-pong buffer scheme for primary endpoint
increases data transfer throughput
Multiple interrupt modes to facilitate both bulk
and isochronous transfers.
Dedicated clock output pin with programmable
clock frequency (4 – 24 MHz)
30 kHz output clock provided during suspend.
Integrated D+ pull-up resistor for USB
connection
USB connection indicator that toggles with USB
transmit and receive activities.
Supports
bus-powered
or
self-powered
applications.
Single power supply operation at 3.3V or 5V.
Internal 1.8V and 3.3V LDO regulators
Integrated power-on-reset circuit.
UHCI/OHCI/EHCI host controller compatible.
-40°C to 85°C extended operating temperature
range.
Available in Pb-free TSSOP-28 and QFN-28
packages (RoHS compliant).
Neither the whole nor any part of the information contained in, or the product described in this manual, may be adapted or reproduced
in any material or electronic form without the prior written consent of the copyright holder. This product and its documentation are
supplied on an as-is basis and no warranty as to their suitability for any particular purpose is either made or implied. Future Technology
Devices International Ltd will not accept any claim for damages howsoever arising as a result of use or failure of this produ ct. Your
statutory rights are not affected. This product or any variant of it is not intended for use in any medical appliance, device or system in
which the failure of the product might reasonably be expected to result in personal injury. This document provides preliminar y
information that may be subject to change without notice. No freedom to use patents or other intellectual property rights is implied by
the publication of this document. Future Technology Devices International Ltd, Unit 1, 2 Seaward Place, Centurion Business Park, Glasgow
G41 1HH United Kingdom. Scotland Registered Company Number: SC13664
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FT120 Datasheet Datasheet
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1 Typical Applications
Provide USB port to Microcontrollers
USB Industrial Control
Mass storage data transfers for multitude of
embedded systems applications, including
medical,
industrial
data-logger,
powermetering, and test instrumentation
Provide USB port to FPGA’s
Utilising USB to add system modularity
Isochronous support for video applications in
security,
industrial
control,
and
quality
inspections
1.1 Part Numbers
Part Number
FT120T-x
Package
TSSOP-28
Note: Packaging codes for x is:
- R: Taped and Reel, (TSSOP is 2,500pcs per reel).
- U: Tube packing, 50pcs per tube (TSSOP only)
For example: FT120T-R is 2,500pcs taped and reel packing
1.2 USB Compliant
At the time of writing this datasheet, the FT120 was in the process of completing USB compliance testing.
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FT120 Datasheet Datasheet
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2 Block Diagrams
Figure 2-1 FT120 Block Diagram
For a description of each function please refer to Section 5.
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FT120 Datasheet Datasheet
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Table of Contents
1
Typical Applications....................................................... 2
1.1
Part Numbers ............................................................................. 2
1.2
USB Compliant ........................................................................... 2
2
Block Diagrams ............................................................. 3
3
Device Pin Out and Signal Description ........................... 6
3.1
TSSOP-28 Package Pin Out ........................................................ 6
3.2
Pin Description .......................................................................... 7
4
Function Description ..................................................... 8
4.1
Functional Block Descriptions .................................................... 8
4.2
Interrupt Modes ......................................................................... 9
5
Endpoint Buffer Management ...................................... 10
6
Commands and Registers ............................................ 11
6.1
Command Summary ................................................................. 11
6.2
Initialization Commands .......................................................... 12
6.2.1
Set Address Enable ................................................................................... 12
6.2.2
Set Endpoint Enable .................................................................................. 12
6.2.3
Set Mode ................................................................................................. 12
6.2.4
Set DMA .................................................................................................. 13
6.3
Data Flow Commands .............................................................. 14
6.3.1
Read Interrupt Register ............................................................................. 14
6.3.2
Select Endpoint ......................................................................................... 14
6.3.3
Read Last Transaction Status ...................................................................... 14
6.3.4
Read Endpoint Status ................................................................................ 15
6.3.5
Read Buffer .............................................................................................. 15
6.3.6
Write Buffer .............................................................................................. 16
6.3.7
Clear Buffer .............................................................................................. 16
6.3.8
Validate Buffer .......................................................................................... 16
6.3.9
Set Endpoint Status ................................................................................... 16
6.3.10
Acknowledge Setup ................................................................................... 16
6.4
General Commands .................................................................. 17
6.4.1
Read Current Frame Number ...................................................................... 17
6.4.2
Send Resume ........................................................................................... 17
7
Reference Schematic ................................................... 18
8
Devices Characteristics and Ratings ............................ 19
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FT120 Datasheet Datasheet
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8.1
Absolute Maximum Ratings ...................................................... 19
8.2
DC Characteristics .................................................................... 19
8.3
AC Characteristics .................................................................... 20
9
Package Parameters .................................................... 23
9.1
TSSOP-28 Package Dimensions ................................................ 23
9.2
TSSOP-28 Package Markings................................................... 24
9.3
Solder Reflow Profile ............................................................... 24
10 Contact Information .................................................... 26
Appendix A – References ................................................... 27
Document References ...................................................................... 27
Acronyms and Abbreviations............................................................ 27
Appendix B - List of Figures and Tables ............................. 28
List of Figures .................................................................................. 28
List of Tables.................................................................................... 28
Appendix C - Revision History ............................................ 29
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FT120 Datasheet Datasheet
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3 Device Pin Out and Signal Description
3.1 TSSOP-28 Package Pin Out
Figure 3-1 TSSOP-28 package schematic symbol
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FT120 Datasheet Datasheet
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3.2 Pin Description
PIN No.
(TSSOP-28)
1
2
3
4
5
6
7
8
9
10
PIN
NAME
DATA0
DATA1
DATA2
DATA3
GND
DATA4
DATA5
DATA6
DATA7
ALE
11
12
13
14
15
16
17
18
19
CS_n
SUSPEND
CLKOUT
INT_n
RD_n
WR_n
DMREQ
DMACK_n
EOT_n
20
21
22
RESET_n
GL_n
OSCI
23
OSCO
24
25
26
27
VCC
USBDM
USBDP
VOUT3V3
28
A0
-
GND
TYP
E
IO
IO
IO
IO
P
IO
IO
IO
IO
I
DESCRIPTION
Data bus bit 0.
Data bus bit 1.
Data bus bit 2.
Data bus bit 3.
Ground.
Data bus bit 4.
Data bus bit 5.
Data bus bit 6.
Data bus bit 7.
Address latch enable for multiplexed address/data bus
configuration.
This pin must be pulled Low for non-multiplexed
address/data bus configuration.
I
Chip select (Active Low).
I,OD Device suspend (output) and wakeup (input).
O
Programmable output clock.
OD
Interrupt (Active Low).
I
Read enable (Active Low).
I
Write enable (Active Low).
O
DMA request.
I
DMA acknowledge (Active Low).
I
End of DMA transfer (Active Low). Also function as Vbus
sensing input for self-powered application. _n_n_n_n
I
Asynchronous reset (Active Low).
OD
USB bus activity indicator (Active Low)
I
Crystal connection input (6MHz); alternatively, a 1.8V
square wave clock can be applied.
O
Crystal connection output (6MHz) ; if the external clock
signal is connected to OSCI, then OSCO should be left
unconnected
P
Power supply (3.3V or 5V)
AIO
USB data signal minus
AIO
USB data signal plus
P
3.3V regulator output for 5V operation;
To operate the IC at 3.3 V, supply 3.3 V to both the VCC
and VOUT3V3 pins
I
Address bit for non-multiplexed address/data bus
configuration.
- A0=1 indicates command phase;
- A0=0 indicates data phase.
This pin must be pulled High for multiplexed
address/data bus configuration.
P
Ground. Die pad for QFN-28 package.
Table 3-1 FT120 Pin Description
Note: symbol used for pin TYPE:
OD
: Open Drain Output
O
: Output
IO
: Bi-directional Input and Output
I
: Plain input
AIO
: Analog Input and Output
P
: Power or ground
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FT120 Datasheet Datasheet
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4 Function Description
The FT120 is a USB device controller which interfaces with microcontrollers via a generic 8-bit parallel
bus.
4.1 Functional Block Descriptions
The following sections describe the function of each block. Please refer to the block diagram shown in
Figure 2-1.
+1.8V LDO Regulator. The +1.8V LDO regulator generates the +1.8V reference voltage for the internal
core of the IC with input capabilities from 3.3V or 5V.
+3.3V LDO Regulator. The +3.3V LDO regulator generates the +3.3V supply voltage for the USB
transceiver. An external decoupling capacitor needs to be attached to the VOUT3V3 regulator output pin.
The regulator also provides +3.3V power to the 1.5kΩ internal pull up resistor on USBDP pin. The
allowable input voltages are 5V or 3.3V. When using 3.3V as the input voltage, the VCC and VOUT3V3
pins should be tied together. This will result in the regulator being by-passed.
USB Transceiver. The USB Transceiver cell provides the USB 1.1 / USB 2.0 full-speed physical interface.
Output drivers provide +3.3V level slew rate control , while a differential input and two single ended
input receivers provide data in, Single-Ended-0 (SE0) and USB reset detection conditions respectfully. A
1.5kΩ pull up resistor on USBDP is incorporated.
DPLL. The DPLL cell locks on to the incoming NRZI USB data and generates recovered clock and data
signals.
Internal Oscillator. The Internal Oscillator cell generates a 6MHz reference clock from the 6MHz crystal.
The Oscillator also has the capability of running from an external clock applied on the OSCI pin. This
provides an input to the Clock Multiplier function.
Clock Multiplier. The 12MHz and 48MHz reference clock signals for various internal blocks can be
generated from the 6 MHz via the oscillator functions and clock multiplier circuitry.
Serial Interface Engine (SIE). The Serial Interface Engine (SIE) block performs the parallel to serial
and serial to parallel conversion of the USB data. In accordance with the USB 2.0 specification, it
performs bit stuffing/un-stuffing and CRC5/CRC16 generation. It also checks the CRC on the USB data
stream.
USB Protocol Engine. The USB Protocol Engine manages the data stream from the device USB control
endpoint. It handles the low level USB protocol requests generated by the USB host controller. The
Protocol Engine also includes a memory management unit which handles endpoint buffers.
OUT Buffer. Data sent from the USB host controller to FT120 via the USB data OUT endpoint is stored in
the OUT buffer. Data is removed from the OUT buffer to system memory under control of the parallel
interface block.
IN Buffer. Data from system memory is stored in the IN buffer. The USB host controller removes data
from the IN buffer by sending a USB request for data from the device data IN endpoint.
RESET Generator. The integrated Reset Generator cell provides a reliable power-on reset to the device
internal circuitry at power up. The RESET_n input pin allows an external device to reset the FT120.
Parallel Interface Block. The 8-bit parallel bus allows direct interface to a generic microcontroller
(MCU), supporting both multiplexed and non-multiplexed address/data bus configurations. The FT120
also supports Direct Memory Access (DMA) operation. With DMA access data can be written to the IN
buffer or read from the OUT buffer without MCU intervention. The DMA access can be done in single cycle
or burst mode.
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4.2 Interrupt Modes
The FT120 interrupt pin (INT_n) can be programmed to generate an interrupt in different modes. The
interrupt source can be any bit in the Interrupt Register, a SOF packet being received, or both. The
interrupt modes are selectable by two register bits, one is the SOF-only Interrupt Mode bit (bit 7 of Clock
Division Factor register), and the other is the Interrupt Pin Mode bit (bit 5 of DMA Configuration register).
Interrupt
mode
0
1
2
Bit SOF-only
Interrupt
Mode
0
0
1
Bit
Interrupt source
Interrupt
Pin Mode
0
Any bit in Interrupt register
1
Any bit in Interrupt register and SOF
X
SOF only
Table 4-1 Interrupt modes
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5 Endpoint Buffer Management
The FT120 has 3 physical endpoints (EP0, EP1 and EP2) or 6 logical endpoints (EPI0-EPI5). EP0 is the
control endpoint, with 16 bytes maximum packet size for both control OUT (EPI0) and control IN (EPI1)
endpoint. EP1 can be used as either a bulk endpoint or an interrupt endpoint, with 16 bytes maximum
packet size for both OUT (EPI2) and IN (EPI3) endpoints. Table 5-1 shows the endpoint type and
maximum packet size for EP0 and EP1.
Endpoint
Number
0
1
Endpoint
Endpoint
Transfer Type
Index
Direction
(EPI)
0
OUT
Control
1
IN
Control
2
OUT
Bulk/Interrupt
3
IN
Bulk/Interrupt
Table 5-1 Endpoint configuration for EP0 and EP1
Max Packet
Size
16
16
16
16
EP2 is the primary endpoint. It can be configured as either a bulk/interrupt or isochronous endpoint. The
maximum packet size allowed for EP2 depends on the mode of configuration through the Set Mode
command. Table 5-2 shows all the 4 endpoint configuration modes for EP2.
Endpoint
Configuration
Mode (EP2)
0
(default)
1
2
3
Endpoint
Index
(EPI)
4
5
4
5
4
5
Endpoint
Direction
Transfer Type
OUT
Bulk/Interrupt
IN
Bulk/Interrupt
OUT
Isochronous
IN
Isochronous
OUT
Isochronous
IN
Isochronous
Table 5-2 Endpoint configuration for EP2
Max Packet
Size
64
64
128
128
64
64
As the primary endpoint, EP2 is suitable for transmitting or receiving relatively large data. To improve the
data throughput, a pair of buffers (the ‘ping-pong’ buffer) is implemented for EP2 buffering. This allows
the concurrent operation between USB bus access and MCU or DMA local bus access. For example, for
EP2 IN endpoint (EPI5), the USB host can read data from FT120 ping buffer while the local MCU is writing
to the pong buffer at the same time. The USB host can subsequently read from FT120 pong buffer
without waiting for it to be filled. Buffer switching is handled automatically by FT120.
The EP2 buffer also supports DMA operation. The MCU needs to initialize the DMA operation through the
Set DMA command. Once DMA operation is enabled, data will be moving between the system memory
and FT120 endpoint buffer under the DMA controller. Buffer switching between ping buffer and pong
buffer is handled automatically.
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FT120 Datasheet Datasheet
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6 Commands and Registers
The FT120 supported commands are summarized in Table 6-1. These commands include initialization
commands, data flow commands and generic commands, which are described in detail in sections 6.2,
6.3 and 6.4 respectively.
6.1 Command Summary
Command Name
Set
Set
Set
Set
Address Enable
Endpoint Enable
Mode
DMA
Read Interrupt Register
Select Endpoint
Read Last Transaction Status
Read Endpoint Status
Read Buffer
Write Buffer
Set Endpoint Status
Acknowledge Setup
Clear Buffer
Validate Buffer
Read Current Frame Number
Send Resume
Target
Code (hex)
Initialization Commands
Device
D0h
Device
D8h
Device
F3h
Device
FBh
Data Flow Commands
Device
F4h
Endpoint 0 OUT
00h
Endpoint 0 IN
01h
Endpoint 1 OUT
02h
Endpoint 1 IN
03h
Endpoint 2 OUT
04h
Endpoint 2 IN
05h
Endpoint 0 OUT
40h
Endpoint 0 IN
41h
Endpoint 1 OUT
42h
Endpoint 1 IN
43h
Endpoint 2 OUT
44h
Endpoint 2 IN
45h
Endpoint 0 OUT
80h
Endpoint 0 IN
81h
Endpoint 1 OUT
82h
Endpoint 1 IN
83h
Endpoint 2 OUT
84h
Endpoint 2 IN
85h
Selected Endpoint
F0h
Selected Endpoint
F0h
Endpoint 0 OUT
40h
Endpoint 0 IN
41h
Endpoint 1 OUT
42h
Endpoint 1 IN
43h
Endpoint 2 OUT
44h
Endpoint 2 IN
45h
Selected Endpoint
F1h
Selected Endpoint
F2h
Selected Endpoint
FAh
General Commands
Device
F5h
Device
F6h
Table 6-1 FT120 command set
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Data phase
Write 1 byte
Write 1 byte
Write 2 bytes
Write/Read 1 byte
Read 2 bytes
Read 1 byte (optional)
Read 1 byte (optional)
Read 1 byte (optional)
Read 1 byte (optional)
Read 1 byte (optional)
Read 1 byte (optional)
Read 1 byte
Read 1 byte
Read 1 byte
Read 1 byte
Read 1 byte
Read 1 byte
Read 1 byte
Read 1 byte
Read 1 byte
Read 1 byte
Read 1 byte
Read 1 byte
Read multiple bytes
Write multiple bytes
Write 1 byte
Write 1 byte
Write 1 byte
Write 1 byte
Write 1 byte
Write 1 byte
None
None
None
Read 1 or 2 bytes
None
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6.2 Initialization Commands
6.2.1
Set Address Enable
Command
Data
Bit
6-0
7
: D0h
: Write 1 byte
Symbol
Address
Enable
6.2.2
Set Endpoint Enable
Command
Data
: D8h
: Write 1 byte
Bit
0
Symbol
EP_Enable
7-1
Reserved
6.2.3
2
3
4
5
7-6
Reset
0
Description
Enable EP1 and EP2 endpoints (Note EP0 is always
enabled regardless of the setting of EP_Enable bit).
Endpoints can only be enabled when the function is
enabled.
0b’0000000 Reserved, write to 0
Table 6-3 Endpoint Enable Register
Set Mode
Command
Data
Bit
0
1
Reset
Description
0b’0000000 USB assigned device address. A bus reset will reset all
address bits to 0.
0
Function enable. A bus reset will automatically enable the
function at default address 0.
Table 6-2 Address Enable Register
: F3h
: Write 2 bytes
Symbol
Reserved
No Suspend Clock
Reset
0
1
Description
Reserved, write to 0
0: CLKOUT switches to 30 KHz during USB suspend
1: CLKOUT remains unchanged during USB suspend
Note: The programmed value will not be changed by a
bus reset.
Clock Running
1
0: internal clocks stop during USB suspend
1: internal clocks continue running during USB suspend
This bit must be set to ‘0’ for bus powered application in
order to meet the USB suspend current requirement.
Note: The programmed value will not be changed by a
bus reset.
Interrupt Mode
1
0: interrupt will not generate on NAK or Error
transactions
1: interrupt will generate on NAK and Error transactions
Note: The programmed value will not be changed by a
bus reset.
DP_Pullup
0
0: Pullup resistor on USBDP pin disabled
1: Pullup resistor on USBDP pin enabled when Vbus is
present
Note: The programmed value will not be changed by a
bus reset.
Reserved
0
Reserved, write to 0
Endpoint Configuration
0b’00
Set the endpoint configuration mode for EP2.
Mode
00: Mode 0 (Non-ISO Mode)
01: Mode 1 (ISO-OUT Mode)
10: Mode 2 (ISO-IN Mode)
11: Mode 3 (ISO-IO Mode)
Table 6-4 Configuration Register (Byte 1)
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FT120 Datasheet Datasheet
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Bit
3-0
5-4
6
7
Symbol
Clock Division Factor
Description
The Clock Division Factor value (CDF) determines the
output clock frequency on the CLKOUT pin. Frequency =
48 MHz / (CDF +1), where CDF ranges 1-12 or the
allowed CLKOUT frequency is 4-24 MHz. Default CLKOUT
is 4 MHz.
When the CDF is programmed to 0b’1111, the CLKOUT
will be turned off. It is recommended to turn off the
CLKOUT if it not used, for power saving (about 3mA).
Note: The programmed value will not be changed by a
bus reset.
Reserved
0b’00
Reserved, write to 0
SET_TO_ONE
0
This bit must be set to 1
SOF-only Interrupt
0
0: normal operation
Mode
1: interrupt will generate on receiving SOF packet only,
regardless of the value of the Interrupt Pin Mode bit in
the DMA configuration register.
Table 6-5 Clock Division Factor Register (Byte 2)
6.2.4
2
3
4
5
6
7
Reset
0b’1011
Set DMA
Command
Data
Bit
1-0
Clearance No.: FTDI# 291
: FBh
: Read/Write 1 byte
Symbol
DMA Burst
Reset
0b’00
Description
Set the DMA burst size
00: Single cycle mode
01: 4 cycle burst mode
10: 8 cycle burst mode
11: 16 cycle burst mode
DMA Enable
0
Enable DMA operation
0: DMA operation is disabled
1: DMA operation is enabled
FT120 will clear this bit upon EOT_n assertion.
DMA Direction
0
This bit indicates the DMA read or write operation.
0: DMA read. Data read from FT120 OUT buffer to
system memory.
1: DMA write. Data write to FT120 IN buffer from system
memory.
Auto Reload
0
Automatically restart the DMA operation.
0: DMA needs to restart by software
1: DMA will restart automatically after the previous DMA
transfer finishes
Interrupt Pin Mode
0
0: normal operation. Interrupt will generate if any bit in
the interrupt register is set.
1: interrupt will generate upon receiving SOF packet or if
any bit in the interrupt register is set.
EPI4 Interrupt Enable
0
Interrupt Enable for endpoint index 4. During DMA
operation, EPI4 interrupt should be turned off to avoid
un-necessary interrupt service.
EPI5 Interrupt Enable
0
Interrupt Enable for endpoint index 5. During DMA
operation, EPI5 interrupt should be turned off to avoid
un-necessary interrupt service.
Table 6-6 DMA Configuration Register
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6.3 Data Flow Commands
6.3.1
Read Interrupt Register
Command
Data
Bit
0
: F4h
: Read 1 or 2 bytes
Symbol
Endpoint 0 Out
1
Endpoint 0 In
2
Endpoint 1 Out
3
Endpoint 1 In
4
Endpoint 2 Out
5
Endpoint 2 In
6
Bus Reset
7
Suspend Change
Bit
0
Symbol
DMA EOT
1
Reserved
6.3.2
7-2
Symbol
Full/Empty
Stall
Reserved
6.3.3
Bit
0
4-1
5
6
Description
Interrupt for end of DMA transfer. This bit will be cleared
after reading.
0b’xxxxxxx Reserved
Table 6-8 Interrupt Register Byte 2
Reset
0
Description
0: selected endpoint buffer is empty
1: selected endpoint buffer is not empty
0
0: selected endpoint is not stalled
1: selected endpoint is stalled
0b’xxxxxx Reserved
Table 6-9 Endpoint Status Register
Read Last Transaction Status
Command
Data
Reset
0
: 00-05h (0ih where ‘i’ is the endpoint index (EPI) as defined in Table 5-1 and
Table 5-2)
: Optional Read 1 byte
Data
1
Description
Interrupt for endpoint 0 OUT buffer. Cleared by Read
Last Transaction Status command.
0
Interrupt for endpoint 0 IN buffer. Cleared by Read Last
Transaction Status command.
0
Interrupt for endpoint 1 OUT buffer. Cleared by Read
Last Transaction Status command.
0
Interrupt for endpoint 1 IN buffer. Cleared by Read Last
Transaction Status command.
0
Interrupt for endpoint 2 OUT buffer. Cleared by Read
Last Transaction Status command.
0
Interrupt for endpoint 2 IN buffer. Cleared by Read Last
Transaction Status command.
0
Interrupt for bus reset. This bit will be cleared after
reading.
0
Interrupt for USB bus suspend status change. This bit
will be set to ‘1’ when FT120 goes to suspend (missing 3
continuous SOFs) or resumes from suspend. This bit will
be cleared after reading.
Table 6-7 Interrupt Register Byte 1
Select Endpoint
Command
Bit
0
Reset
0
: 40-45h (4ih where ‘i’ is the endpoint index (EPI) as defined in Table 5-1 and
Table 5-2)
: Read 1 byte
Symbol
Data Receive/Transmit
Success
Error Code
Setup Packet
Data 0/1 Packet
Reset
0
0b’0000
0
0
Description
0: indicate USB data receive or transmit not OK
1: indicate USB data receive or transmit OK
Refer to Table 6-11
0: indicate not a setup packet
1: indicate last received packet has a SETUP token
0: packet has a DATA0 token
1: packet has a DATA1 token
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Bit
7
Clearance No.: FTDI# 291
Symbol
Reset
Description
Previous Status not
0
0: previous transaction status was read
Read
0: previous transaction status was not read
Table 6-10 Endpoint Last Transaction Status Register
Error Code
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1101
1111
6.3.4
Result
No error
PID encoding error
PID unknown
Unexpected packet
Token CRC error
Data CRC error
Time out error
Reserved
Unexpected EOP
Packet NAKed
Sent stall
Buffer overflow
Bit stuff error
Wrong DATA PID
Table 6-11 Transaction error code
Read Endpoint Status
Command
: 80-85h (8ih where ‘i’ is the endpoint index (EPI) as defined in Table 5-1 and
Table 5-2)
: Read 1 byte
Data
Bit
1-0
2
Symbol
Reserved
Setup packet
4-3
5
Reserved
Buffer 0 Full
6
Buffer 1 Full
7
Endpoint Stalled
6.3.5
Reset
0b’00
0
Description
Reserved
0: indicate not a setup packet
1: indicate last received packet has a SETUP token
0b’xx
Reserved
0
0: ping buffer is not filled up
1: ping buffer is filled up
0
0: pong buffer is not filled up
1: pong buffer is filled up
Note: this bit only applicable to EP2 which supports pingpong buffer
0
0: endpoint is not stalled
1: endpoint is stalled
Table 6-12 Endpoint Buffer Status Register
Read Buffer
Command
Data
: F0h
: Read multiple bytes
The Read Buffer command is used to read the received packet from the selected endpoint OUT buffer.
The data in the endpoint buffer is organized as follows:
o
o
o
o
o
o
byte
byte
byte
byte
…
byte
0:
1:
2:
3:
reserved, don’t care
length of payload packet
Payload packet byte 1
Payload packet byte 2
n: Payload packet byte n (n = packet length + 2)
For DMA read operation the first two bytes are skipped. Only the payload packet itself will be read and
stored in system memory.
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FT120 Datasheet Datasheet
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6.3.6
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Write Buffer
Command
Data
: F0h
: Write multiple bytes
The Write Buffer command is used to write payload packet to the selected endpoint IN buffer.
The data must be organized in the same way as described in the Read Buffer command. Byte 0 should
always be set to 00h.
For DMA write operation the first two bytes are skipped. Only the payload packet itself shall be written to
the selected endpoint OUT buffer. Buffer is validated when the max packet size is reached, or when the
DMA transfer is terminated by EOT_n (usually the last packet).
6.3.7
Clear Buffer
Command
Data
: F2h
: None
The Clear Buffer command should be issued after all data has been read out from the endpoint buffer.
This is to free the buffer to receive next packet from USB host.
6.3.8
Validate Buffer
Command
Data
: FAh
: None
The Validate Buffer command should be issued after all data has been written to the endpoint buffer. This
is to set the buffer full flag so that the packet can be sent to USB host when IN token arrives.
6.3.9
Set Endpoint Status
Command
: 40-45h (4ih where ‘i’ is the endpoint index (EPI) as defined in Table 5-1 and
Table 5-2)
: Write 1 byte
Data
Bit
0
Stall
Symbol
7-1
Reserved
6.3.10
Command
Data
Reset
0
Description
0: Disable the endpoint STALL state.
1: Enable the endpoint STALL state.
For EP0 OUT (control OUT endpoint) the STALL state will
automatically be cleared by receiving a SETUP packet.
When this bit is cleared, the endpoint will reinitialize. Any
data in the endpoint buffer will be flushed away, and the
PID for next packet will carry DATA0 flag.
0b’xxxxxxx Reserved
Table 6-13 Endpoint Control Register
Acknowledge Setup
: F1h
: None
When receiving a SETUP packet the FT120 will flush the IN buffer and disable the Validate Buffer and
Clear Buffer commands for both IN and OUT endpoints. The MCU shall read and process the SETUP
packet, and then issue the Acknowledge Setup command to re-enable the Validate Buffer and Clear
Buffer commands. The Acknowledge Setup command must be sent to both IN and OUT endpoints.
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FT120 Datasheet Datasheet
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6.4 General Commands
6.4.1
Read Current Frame Number
Command
Data
: F5h
: Read One or Two Bytes
Bit
7-0
Symbol
Frame Number LSB
Bit
2-0
Symbol
Frame Number MSB
7-3
Reserved
6.4.2
Command
Data
Reset
00h
Description
Frame number for last received SOF, byte 1 (least
significant byte)
Table 6-14 Frame Number LSB Register
Reset
0b’000
Description
Frame number for last received SOF, byte 2 (Most
significant byte)
0b’00000
Reserved
Table 6-15 Frame Number MSB Register
Send Resume
: F6h
: None
To perform remote-wakeup when suspended, the MCU needs to issue Send Resume command. The
FT120 will send an upstream resume signal for a period of 10 ms. If the clock is not running during
suspend, the MCU needs to wakeup FT120 by drive SUSPEND pin to LOW, followed by Send Resume
command.
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FT120 Datasheet Datasheet
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Clearance No.: FTDI# 291
7 Reference Schematic
Figure 7-1 shows a reference schematic for a FT120 module which can be connected to a generic
microcontroller to add USB device function. The reference design supports both bus-powered and selfpowered applications.
Figure 7-1 FT120 Reference schematics
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FT120 Datasheet Datasheet
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Clearance No.: FTDI# 291
8 Devices Characteristics and Ratings
8.1 Absolute Maximum Ratings
The absolute maximum ratings for the FT120 devices are as follows. These are in accordance with the
Absolute Maximum Rating System (IEC 60134). Exceeding these may cause permanent damage to the
device.
Parameter
Value
Unit
Storage Temperature
-65 to 150
168
(IPC/JEDEC J-STD-033A MSL Level 3
Compliant)*
-40 to 85
TBD
°C
Floor Life (Out of Bag) At Factory Ambient
(30°C / 60% Relative Humidity)
Ambient Temperature (Power Applied)
Latch-up current
Electrostatic Discharge Voltage(ESD)
±2000
human body model(HBM)
Electrostatic Discharge Voltage(ESD)
±200
machine model(MM)
Electrostatic Discharge Voltage(ESD)
±500
charged device model(CDM)
VCC Supply Voltage
-0.5 to +6.0
DC Input Voltage – USBDP and USBDM
-0.5 to +3.8
DC Input Voltage – High Impedance
-0.5 to + (VCC +0.5)
Bidirectional
DC Input Voltage – All Other Inputs
-0.5 to + (VCC +0.5)
DC Output Current – Outputs
22
Table 8-1 Absolute Maximum Ratings
Hours
°C
mA
V
V
V
V
V
V
V
mA
* If devices are stored out of the packaging beyond this time limit the devices should be baked before
use. The devices should be ramped up to a temperature of +125°C and baked for up to 17 hours.
8.2 DC Characteristics
DC Characteristics (Ambient Temperature = -40°C to +85°C)
Parameter
VCC1
VCC2
Description
VCC Operating
Supply Voltage
VCC Operating
Supply Voltage
Minimum
Typical
Maximum
Units
Conditions
4.0
5.0
5.5
V
Normal Operation
3.0
3.3
3.6
V
Icc1
Operating Supply
Current
5
mA
Icc2
Operating Supply
Current
8
mA
Icc3
Operating Supply
Current
84
μA
VOUT3V3
3.3v regulator
3.0
3.3
3.6
output
Table 8-2 Operating Voltage and Current
Copyright © Future Technology Devices International Limited
V
Regulator by-pass
mode Operation
Normal Operation,
USB bus transmit
or receive,
CLKOUT off
Normal Operation,
USB bus transmit
or receive,
CLKOUT = 12 MHz
USB Suspend,
Clock Running =
‘0’, excluding the
DP_Pullup current
VCC=5V
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FT120 Datasheet Datasheet
Version 1.4
Document No.: FT_000646
Parameter
Voh
Vol
Vih
Vil
Description
Parameter
UVoh
UVol
UVse
UCom
UVDif
Minimum
Output Voltage High
Output Voltage Low
Input Voltage High
Input Voltage Low
Table 8-3
Description
I/O Pins Static Output
(Low)
Single Ended Rx
Threshold
Differential Common
Mode
Differential Input
Sensitivity
Driver Output
Impedance
UDrvZ
Maximum
Units
Conditions
3.6
0.4
V
V
V
V
I source = 4mA
I sink = 4mA
2.0
0.8
digital I/O Pin Characteristics
Minimum
I/O Pins Static Output
(High)
Typical
2.4
Typical
Clearance No.: FTDI# 291
Maximum
Units
Conditions
2.8
3.6
V
RL = 1.5kΩ to 3.6
V
-
0.3
V
RL = 15kΩ to GND
0.8
2.0
V
0.8
2.5
V
0.2
29
V
-
44
Including external
22 Ω ±1% series
resistor
Ω
Table 8-4 USB I/O Pin (USBDP, USBDM) Characteristics
8.3 AC Characteristics
Parameter
Minimum
Value
Typical
Unit
Maximum
Frequency of Operation
5.997
6.000
6.003
MHz
(see Note 1)
Duty Cycle
45
50
55
%
Table 8-5 Crystal or clock Characteristics (OSCI, OSCO pins)
Note 1: Equivalent to ±500ppm
Symbol
tLH
tAVLL
tLLAX
tCLWL
tWHCH
tAVWL
tWHAX
tWL
tWDSU
tWDH
tWC
t(WC-WD)
tCLRL
tRHCH
tAVRL
tRL
tRLDD
tRHDZ
tRC
t(WC-RD)
Parameter
ALE Timings:
ALE High Pulse Width
Address Valid to ALE Low Time
ALE Low to Address Transition Time
Write Timings:
CS_n (DMACK_n) Low to WR_n Low Time
WR_n High to CS_n (DMACK_n) High Time
A0 Valid to WR_n Low Time
WR_n High to A0 Transition Time
WR_n Low Pulse Width
Write Data Setup Time
Write Data Hold Time
Write Cycle Time
Write command to write data
Read Timings:
CS_n (DMACK_n) Low to RD_n Low Time
RD_n High to CS_n (DMACK_n) High Time
A0 Valid to RD_n Low Time
RD_n Low Pulse Width
RD_n Low to Data Valid Time
RD_n High to Data Hi-Z Time
Read Cycle Time
Write command to read data
Table 8-6 Parallel Interface IO timing
Copyright © Future Technology Devices International Limited
Min
Max
Unit
10
ns
ns
ns
20
10
0
5
0
5
20
30
10
500
600
ns
ns
ns
ns
ns
ns
ns
ns
ns
0
5
0
20
Ns
Ns
Ns
Ns
Ns
Ns
Ns
Ns
20
20
500
600
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FT120 Datasheet Datasheet
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Clearance No.: FTDI# 291
Figure 8-1 ALE Timing
Figure 8-2 Parallel interface timing
Symbol
tRHSH
tAHRH
tSHAH
tEL
tSLRL
tRHSH
tSHAH
tELRL
Parameter
Single-cycle DMA Timings:
DMREQ High to RD_n/WR_n High Time
DMACK_n High to DMREQ High Time
RD_n/WR_n High to DMACK_n High Time
EOT_n Low Pulse Width (Simultaneous DMACK_n, RD_n/WR_n
and EOT_n low time)
Burst DMA Timings:
RD_n/WR_n Low to DMREQ Low Time
DMREQ High to RD_n/WR_n High Time
RD_n/WR_n High to DMACK_n High Time
EOT Timings:
EOT_n Low to DMREQ Low Time
Table 8-7 DMA timing characteristics
Copyright © Future Technology Devices International Limited
Min
Max
120
330
130
10
Unit
Ns
Ns
Ns
Ns
40
Ns
Ns
Ns
40
Ns
120
130
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FT120 Datasheet Datasheet
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Figure 8-3 Single cycle DMA timing
Figure 8-4 Burst mode DMA timing
Figure 8-5 DMA terminated by EOT_n
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FT120 Datasheet Datasheet
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9 Package Parameters
The FT120T is the TSSOP-28 package.. The solder reflow profile is described in Section 9.3.
9.1 TSSOP-28 Package Dimensions
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FT120 Datasheet Datasheet
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Figure 9-1 TSSOP-28 Package Dimensions
The FT120T is supplied in a RoHS compliant 28 pin TSSOP package. The package is lead (Pb) free and
uses a ‘green’ compound. The package is fully compliant with European Union directive 2002/95/EC.
This package is nominally 4.4mm x 9.7mm body (6.4mm x9.7mm including pins). The pins are on a 0.65
mm pitch. The above mechanical drawing shows the TSSOP-28 package.
All dimensions are in millimetres.
9.2 TSSOP-28 Package Markings
Figure 9-2 TSSOP-28 Package Markings
The date code format is YYWW where WW = 2 digit week number, YY = 2 digit year number.
9.3 Solder Reflow Profile
The FT120 is supplied in Pb free TSSOP-28 and QFN-28 packages. The recommended solder reflow profile
for both package options is shown in Figure 9-3.
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FT120 Datasheet Datasheet
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Temperature, T (Degrees C)
tp
Tp
Critical Zone: when
T is in the range
TL to Tp
Ramp Up
TL
tL
TS Max
Ramp
Down
TS Min
tS
Preheat
25
T = 25º C to TP
Time, t (seconds)
Figure 9-3 FT120 Solder Reflow Profile
The recommended values for the solder reflow profile are detailed in Table 9-1. Values are shown for
both a completely Pb free solder process (i.e. the FT120 is used with Pb free solder), and for a non-Pb
free solder process (i.e. the FT120 is used with non-Pb free solder).
Profile Feature
Pb Free Solder
Process
Non-Pb Free Solder Process
Average Ramp Up Rate (Ts to Tp)
3°C / second Max.
3°C / Second Max.
Preheat
- Temperature Min (Ts Min.)
- Temperature Max (Ts Max.)
- Time (ts Min to ts Max)
150°C
200°C
60 to 120 seconds
100°C
150°C
60 to 120 seconds
Time Maintained Above Critical
Temperature TL:
217°C
- Temperature (TL)
60 to 150 seconds
- Time (tL)
Peak Temperature (Tp)
260°C
Time within 5°C of actual Peak
20 to 40 seconds
Temperature (tp)
Ramp Down Rate
6°C / second Max.
Time for T= 25°C to Peak Temperature,
8 minutes Max.
Tp
Table 9-1 Reflow Profile Parameter Values
Copyright © Future Technology Devices International Limited
183°C
60 to 150 seconds
240°C
20 to 40 seconds
6°C / second Max.
6 minutes Max.
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FT120 Datasheet Datasheet
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Contact Information
Head Office – Glasgow, UK
Branch Office – Tigard, Oregon, USA
Future Technology Devices International Limited
Unit 1, 2 Seaward Place, Centurion Business Park
Glasgow G41 1HH
United Kingdom
Tel: +44 (0) 141 429 2777
Fax: +44 (0) 141 429 2758
Future Technology Devices International Limited (USA)
7130 SW Fir Loop
Tigard, OR 97223-8160
USA
Tel: +1 (503) 547 0988
Fax: +1 (503) 547 0987
E-mail (Sales)
E-mail (Support)
E-mail (General Enquiries)
E-mail (Sales)
E-mail (Support)
E-mail (General Enquiries)
sales1@ftdichip.com
support1@ftdichip.com
admin1@ftdichip.com
us.sales@ftdichip.com
us.support@ftdichip.com
us.admin@ftdichip.com
Branch Office – Taipei, Taiwan
Branch Office – Shanghai, China
Future Technology Devices International Limited (Taiwan)
2F, No. 516, Sec. 1, NeiHu Road
Taipei 114
Taiwan, R.O.C.
Tel: +886 (0) 2 8797 1330
Fax: +886 (0) 2 8791 3576
Future Technology Devices International Limited (China)
Room 1103, No. 666 West Huaihai Road,
Shanghai, 200052
China
Tel: +86 21 62351596
Fax: +86 21 62351595
E-mail (Sales)
E-mail (Support)
E-mail (General Enquiries)
E-mail (Sales)
E-mail (Support)
E-mail (General Enquiries)
tw.sales1@ftdichip.com
tw.support1@ftdichip.com
tw.admin1@ftdichip.com
cn.sales@ftdichip.com
cn.support@ftdichip.com
cn.admin@ftdichip.com
Web Site
http://ftdichip.com
Distributor and Sales Representatives
Please visit the Sales Network page of the FTDI Web site for the contact details of our distributor(s) and sales
representative(s) in your country.
System and equipment manufacturers and designers are responsible to ensure that their systems, and any Future Technology Devices International Ltd
(FTDI) devices incorporated in their systems, meet all applicable safety, regulatory and system-level performance requirements. All application-related
information in this document (including application descriptions, suggested FTDI devices and other materials) is provided for reference only. While FTDI
has taken care to assure it is accurate, this information is subject to customer confirmation, and FTDI disclaims all liability for system designs and for any
applications assistance provided by FTDI. Use of FTDI devices in life support and/or safety applications is entirely at the user’s risk, and the user agrees to
defend, indemnify and hold harmless FTDI from any and all damages, claims, suits or expense resulting from such use. This document is subject to change
without notice. No freedom to use patents or other intellectual property rights is implied by the publication of this document. Neither the whole nor any part
of the information contained in, or the product described in this document, may be adapted or reproduced in any material or electronic form without the prior
written consent of the copyright holder. Future Technology Devices International Ltd, Unit 1, 2 Seaward Place, Centurion Business Park, Glasgow G41
1HH, United Kingdom. Scotland Registered Company Number: SC136640
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FT120 Datasheet Datasheet
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Clearance No.: FTDI# 291
Appendix A – References
Document References
NA
Acronyms and Abbreviations
Terms
Description
AIO
Analog Input and Output
DMA
Direct Access Memory
DPLL
Digital Phase Locked Loop
FPGA
Field-Programmable Gate Array
IC
Integrated Circuit
LDO
Low Drop Out
LED
Light Emitting Diode
MCU
Microcontroller Unit
OD
Open Drain Output
OHCI
Open Host Controller Interface
QFN
Quad Flat No-Lead
RoHS
SIE
TSSOP
Restriction of Hazardous Substances
Serial Interface Engine
Thin Shrink Small Outline Package
USB
Universal Serial Bus
UHCI
Universal Host Controller Interface
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FT120 Datasheet Datasheet
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Clearance No.: FTDI# 291
Appendix B - List of Figures and Tables
List of Figures
Figure 2-1 FT120 Block Diagram ..................................................................................................... 3
Figure 3-1 TSSOP-28 package schematic symbol .............................................................................. 6
Figure 7-1 FT120 Reference schematics ......................................................................................... 18
Figure 8-1 ALE Timing ................................................................................................................. 21
Figure 8-2 Parallel interface timing ............................................................................................... 21
Figure 8-3 Single cycle DMA timing ............................................................................................... 22
Figure 8-4 Burst mode DMA timing ............................................................................................... 22
Figure 8-5 DMA terminated by EOT_n ........................................................................................... 22
Figure 9-1 TSSOP-28 Package Dimensions ..................................................................................... 24
Figure 9-2 TSSOP-28 Package Markings ........................................................................................ 24
Figure 9-3 FT120 Solder Reflow Profile .......................................................................................... 25
List of Tables
Table 3-1 FT120 Pin Description ..................................................................................................... 7
Table 4-1 Interrupt modes ............................................................................................................. 9
Table 5-1 Endpoint configuration for EP0 and EP1 ........................................................................... 10
Table 5-2 Endpoint configuration for EP2 ....................................................................................... 10
Table 6-1 FT120 command set ..................................................................................................... 11
Table 6-2 Address Enable Register ................................................................................................ 12
Table 6-3 Endpoint Enable Register ............................................................................................... 12
Table 6-4 Configuration Register (Byte 1) ...................................................................................... 12
Table 6-5 Clock Division Factor Register (Byte 2) ............................................................................ 13
Table 6-6 DMA Configuration Register ........................................................................................... 13
Table 6-7 Interrupt Register Byte 1 ............................................................................................... 14
Table 6-8 Interrupt Register Byte 2 ............................................................................................... 14
Table 6-9 Endpoint Status Register ............................................................................................... 14
Table 6-10 Endpoint Last Transaction Status Register ..................................................................... 15
Table 6-11 Transaction error code ................................................................................................ 15
Table 6-12 Endpoint Buffer Status Register .................................................................................... 15
Table 6-13 Endpoint Control Register ............................................................................................ 16
Table 6-14 Frame Number LSB Register ........................................................................................ 17
Table 6-15 Frame Number MSB Register........................................................................................ 17
Table 8-1 Absolute Maximum Ratings ............................................................................................ 19
Table 8-2 Operating Voltage and Current ....................................................................................... 19
Table 8-3 digital I/O Pin Characteristics ......................................................................................... 20
Table 8-4 USB I/O Pin (USBDP, USBDM) Characteristics .................................................................. 20
Table 8-5 Crystal or clock Characteristics (OSCI, OSCO pins) ........................................................... 20
Table 8-6 Parallel Interface IO timing ............................................................................................ 20
Table 8-7 DMA timing characteristics............................................................................................. 21
Table 9-1 Reflow Profile Parameter Values ..................................................................................... 25
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FT120 Datasheet Datasheet
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Appendix C - Revision History
Document Title:
FT120 Datasheet
Document Reference No.:
FT_000646
Clearance No.:
FTDI# 291
Product Page:
http://www.ftdichip.com/Products/ICs/FT120.htm
Document Feedback:
Send Feedback
Revision
Changes
Date
1.0
Initial Release
22-05-2012
1.1
Updated Release
23-03-2015
1.2
Updated Figure 9.1
01-04-2015
1.3
Removed references to FT120Q; Updated TSSOP-28 Package Dimensions
and marking
29-05-2020
1.4
Updated TSSOP-28 Package Dimensions
19-08-2020
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