H57V2622GMR-75X

256Mb : x32 Dual Die Synchronous DRAM 256M (8Mx32bit) Hynix SDRAM Memory This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev 1.0 / Oct. 2009 1 111 Synchronous DRAM Memory 256Mbit H57V2622GMR Series Document Title 256Mbit (8M x32) Synchronous DRAM Revision History Revision No. 0.1 1.0 History Initial Draft Release Draft Date Sep. 2009 Oct. 2009 Remark Preliminary Rev 1.0 / Oct. 2009 2 111 Synchronous DRAM Memory 256Mbit H57V2622GMR Series DESCRIPTION The Hynix H57V2622GMR Synchronous DRAM (Dual Die) ideally suited for the consumer memory applications which requires large memory density and high bandwidth uses Hinix’s 128Mb SDR monolithic die and has similar functionality. Synchronous DRAM is a type of DRAM which operates in synchronization with input clock. The Hynix Synchronous DRAM latch each control signal at the rising edge of a basic input clock (CLK) and input/output data in synchronization with the input clock (CLK). The address lines are multiplexed with the Data Input/ Output signals on a multiplexed x32 Input/ Output bus. All the commands are latched in synchronization with the rising edge of CLK. The Synchronous DRAM provides for programmable read or write Burst length of Programmable burst lengths: 1, 2, 4, 8 locations or full page. An AUTO PRECHARGE function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. The Synchronous DRAM uses an internal pipelined architecture to achieve high-speed operation. This architecture is compartible with the 2n rule of prefetch architectures, but it also allows the column address to be changed on every clock cycle to achieve a high-speed, fully random access. Precharging one bank while accessing one of the other three banks will hide the precharge cycles and provide seamless, high-speed, randon-access operation. Read and write accesses to the Hynix Synchronous DRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and the row to be accessed. The address bits registered coincident with the READ or WRITE command are used to select the bank and the starting column location for the burst access. A burst of Read or Write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst Read or Write command on any cycle(This pipelined design is not restricted by a 2N rule). All inputs are LVTTL compatible. Devices will have a VDD and VDDQ supply of 3.3V (nominal). Rev 1.0 / Oct. 2009 3 111 Synchronous DRAM Memory 256Mbit H57V2622GMR Series 256Mb Synchronous DRAM(8M x 32) FEATURES ● Standard SDRAM Protocol Uses 2pcs of 128Mb Monolithic Die Power Supply Voltage : VDD = 3.3V, VDDQ = 3.3V All device pins are compatible with LVTTL interface 4096 Refresh cycles / 64ms Programmable CAS latency of 2 or 3 Programmable Burst Length and Burst Type Operating Temp. - Commercial Temp. : 0oC ~ 70oC, Industrial Temp. : -40oC ~ 85oC ● ● ● ● ● ● ● ● This product is in compliance with the directive pertaining of RoHS. ORDERING INFORMATION Part Number H57V2622GMR-60X H57V2622GMR-75X H57V2622GMR-60X H57V2622GMR-75X Note : 1. H57V2622GMR-XXC : Normal power, Commercial Temp. (0~70℃) 2. H57V2622GMR-XXI : Normal power, Industrial Temp. (-40~85℃) 3. H57V2622GMR-XXL : Low power, Commercail Temp. (0~70℃) 4. H57V2622GMR-XXJ : Low power, Industrial Temp. (-40~85℃) Clock Frequency 166MHz 133MHz 166MHz 133MHz CAS Latency 3 3 3 3 Voltage Organization Interface 3.3V 4Banks x 2Mbits x16 x 2Die LVTTL Rev 1.0 / Oct. 2009 4 111 Synchronous DRAM Memory 256Mbit H57V2622GMR Series BALL CONFIGURATION 1 A B C D E F G H J K L M N P R DQ26 DQ28 VSSQ VSSQ VDDQ VSS A4 A7 CLK DQM1 VDDQ VSSQ VSSQ DQ11 DQ13 2 DQ24 VDDQ DQ27 DQ29 DQ31 DQM3 A5 A8 CKE NC DQ8 DQ10 DQ12 VDDQ DQ15 3 VSS VSSQ DQ25 DQ30 NC A3 A6 NC A9 NC VSS DQ9 DQ14 VSSQ VSS 4 5 6 7 VDD VDDQ DQ22 DQ17 NC A2 8 DQ23 VSSQ DQ20 DQ18 DQ16 DQM2 A0 BA1 /CS /WE DQ7 DQ5 DQ3 VSSQ DQ0 9 DQ21 DQ19 VDDQ VDDQ VSSQ VDD A1 A11 /RAS DQM0 VSSQ VDDQ Top View A10 NC BA0 /CAS VDD DQ6 DQ1 VDDQ VDD VDDQ DQ4 DQ2 Rev 1.0 / Oct. 2009 5 111 Synchronous DRAM Memory 256Mbit H57V2622GMR Series BALL DESCRIPTIONS SYMBOL TYPE DESCRIPTION Clock : The system clock input. All other inputs are registered to the SDRAM on the rising edge of CLK Clock Enable: Controls internal clock signal and when deactivated, the SDRAM will be one of the states among power down, suspend or self refresh Chip Select: Enables or disables all inputs except CLK, CKE and DQM Bank Address: Selects bank to be activated during RAS activity Selects bank to be read/written during CAS activity Row Address: RA0 ~ RA11, Column Address: CA0 ~ CA8 Auto-precharge flag: A10 Command Inputs: RAS, CAS and WE define the operation Refer function truth table for details Data Mask: Controls output buffers in read mode and masks input data in write mode Data Input / Output: Multiplexed data input / output pin Power supply I/O Power supply No connection : These pads should be left unconnected CLK INPUT CKE INPUT CS INPUT BA0, BA1 INPUT A0 ~ A11 INPUT RAS, CAS, WE INPUT DQM0 ~ DQM3 I/O DQ0 ~ DQ31 VDD / VSS VDDQ / VSSQ NC I/O SUPPLY SUPPLY - Rev 1.0 / Oct. 2009 6 111 Synchronous DRAM Memory 256Mbit H57V2622GMR Series FUNCTIONAL BLOCK DIAGRAM 2Mbit x 4banks x 16 I/O x 2 Die Synchronous DRAM Self refresh logic & timer Internal Row Counter CLK CKE CS RAS CAS WE DQM0 ~ DQM3 State Machine Row Active Row Pre Decoder X Decorders X Decoders 2Mx16 Bank0~4 2nd Die 1st Die 2Mx16 Bank0~4 DQ0 I/O Buffer & Logic Sense AMP & I/O Gate Refresh Memory Cell Array Column Active Column Pre Decoder Y decoerders DQ31 Bank Select Column Add Counter A0 A1 Address Buffers Address Register Burst Length Burst Counter Pipe Line Control A11 BA1 BA0 Mode Register CAS Latency Data Out Control Rev 1.0 / Oct. 2009 7 111 Synchronous DRAM Memory 256Mbit H57V2622GMR Series ABSOLUTE MAXIMUM RATING Parameter Ambient Temperature (Commercial Temp.) Ambient Temperature (Industrial Temp.) Storage Temperature Voltage on Any Pin relative to VSS Voltage on VDD supply relative to VSS Short Circuit Output Current Power Dissipation Soldering Temperature . Time Symbol TA TSTG VIN, VOUT VDD, VDDQ IOS PD TSOLDER Rating 0 ~ 70 -40 ~ 85 -55 ~ 125 -1.0 ~ 4.6 -1.0 ~ 4.6 50 1 260 . 10 o Unit oC oC oC V V mA W C . Sec DC OPERATING CONDITION (Commercial : TA = 0~70℃, Industrial : TA = -40~85℃) Parameter Power Supply Voltage Input High Voltage Input Low Voltage Note: Symbol VDD, VDDQ VIH VIL Min 3.0 2.0 -0.3 Max 3.6 VDDQ + 0.3 0.8 Unit V V V Note 1 1, 2 1, 3 1. All voltages are referenced to VSS = 0V. 2. VIH(Max) is acceptable VDDQ + 2V for a pulse width with 1ns, then (tR/2-0.5)ns should be added to the parameter. Rev 1.0 / Oct. 2009 11 111 Synchronous DRAM Memory 256Mbit H57V2622GMR Series AC CHARACTERISTICS II Parameter (AC operating conditions unless otherwise noted) 166 Min 60 60 18 42 18 12 1 0 2 Max 100K 5 2 0 2 3 1 1 64 2 0 2 3 2 1 1 64 133 Min 63 63 20 42 20 15 1 0 2 Max 100K - Symbol Operation Auto Refresh tRC tRRC tRCD tRAS tRP tRRD tCCD tWTL tDPL tDAL tDQZ tDQM tMRD CL = 3 CL = 2 tPROZ3 tPROZ2 tDPE tSRE tREF Unit ns ns ns ns ns ns CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK ms Note RAS Cycle Time RAS to CAS Delay RAS Active Time RAS Precharge Time RAS to RAS Bank Active Delay CAS to CAS Delay Write Command to Data-In Delay Data-in to Precharge Command Data-In to Active Command DQM to Data-Out Hi-Z DQM to Data-In Mask MRS to New Command Precharge to Data Output High-Z Power Down Exit Time Self Refresh Exit Time Refresh Time Note: 1 1. A new command can be given tRC after self refresh exit. Rev 1.0 / Oct. 2009 12 111 Synchronous DRAM Memory 256Mbit H57V2622GMR Series BASIC FUNCTIONAL DESCRIPTION Mode Register BA1 0 BA0 0 A11 0 A10 0 A9 OP Code A8 0 A7 0 A6 A5 CAS Latency A4 A3 BT A2 A1 Burst Length A0 OP Code A9 0 1 Write Mode Burst Read and Burst Write Burst Read and Single Write Burst Type A3 0 1 Burst Type Sequential Interleave CAS Latency A6 0 0 0 0 1 1 1 1 A5 0 0 1 1 0 0 1 1 A4 0 1 0 1 0 1 0 1 CAS Latency Reserved Reserved 2 3 Reserved Reserved Reserved Reserved Burst Length A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 Burst Length A3 = 0 1 2 4 8 Reserved Reserved Reserved Full page A3=1 1 2 4 8 Reserved Reserved Reserved Reserved Rev 1.0 / Oct. 2009 13 111 Synchronous DRAM Memory 256Mbit H57V2622GMR Series COMMAND TRUTH TABLE Function Mode Register Set No Operation Device Deselect Bank Active Read Read with Autoprecharge Write Write with Autoprecharge Precharge All Banks Precharge selected Bank Burst stop DQM Auto Refresh Burst-Read Single-Write Self Refresh Entry Self Refresh Exit Precharge Power Down Entry Precharge Power Down Exit Clock Suspend Entry Clock Suspend Exit Note : CKEn-1 H H H H H H H H H H H H H H H L H L H L CKEn X X X X X X X X X X X X H X L H L H L H CS L L H L L L L L L L L L L L H L H L H L H L RAS L H X L H H H H L L H X L L L X H X H X H X V X CAS L H X H L L L L H H H L L L X H X H X H X V WE L H X H H H L L L L L H H H X H X H X H X V DQM X X X X ADDR A10 /AP X X BA Note Op Code Row Address Column L H L H H L X X X V V V V V X V 2 X X X X X X V X X X X X X X X Column Column Column X X A9 Pin High (Other Pins OP code) X X X X X X 1 1. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high. 2. see to Next page (DQM TRUTH TABLE) Rev 1.0 / Oct. 2009 14 111 Synchronous DRAM Memory 256Mbit H57V2622GMR Series DQM TRUTH TABLE Function Data Write/Output enable Data Mask/Output disable DQ0 to DQ7 write enable / output enable DQ0 to DQ7 write inhibit / output disable DQ8 to DQ15 write enable / output enable DQ8 to DQ15 write inhibit / output disable DQ16 to DQ23 write enable / output enable DQ16 to DQ23 write inhibit / output disable DQ24 to DQ31 write enable / output enable DQ24 to DQ31 write inhibit / output disable Note CKEn-1 H H H H H H H H H H CKEn X X X X X X X X X X DQM0 L H L H X X X X X X DQM1 L H X X L H X X X X DQM2 L H X X X X L H X X DQM3 L H X X X X X X L H 1. H: High Level, L: Low Level, X: Don't Care 2. Write DQM Latency is 0 CLK and Read DQM Latency is 2 CLK Rev 1.0 / Oct. 2009 15 111 Synchronous DRAM Memory 256Mbit H57V2622GMR Series CURRENT STATE TRUTH TABLE (Sheet 1 of 4) Current State Command CS RAS CAS WE L L L L idle L L L H L L L L Row Active L L L H L L L Read L L L L L L L L H H H X L L L L H H H X L L L L H H H L L H H L L H X L L H H L L H X L L H H L L H L H L H L H H X L H L H L H H X L H L H L H H X BA BA BA BA X X BA BA BA BA X X X BA BA BA BA X X BA0/ BA1 Amax-A0 OP CODE X X Row Add. Col Add. A10 Col Add. A10 X X OP CODE X X Row Add. Col Add. A10 Col Add. A10 X X OP CODE X X Row Add. Col Add. A10 Col Add. A10 X Description Mode Register Set Auto or Self Refresh Precharge Bank Activate Write/WriteAP Read/ReadAP No Operation Device Deselect Mode Register Set Auto or Self Refresh Precharge Bank Activate Write/WriteAP Read/ReadAP No Operation Device Deselect Mode Register Set Auto or Self Refresh Precharge Bank Activate Write/WriteAP Read/ReadAP No Operation Action Set the Mode Register Start Auto or Self Refresh No Operation Activate the specified bank and row ILLEGAL ILLEGAL No Operation No Operation or Power Down ILLEGAL ILLEGAL Precharge ILLEGAL Start Write : optional AP(A10=H) Start Read : optional AP(A10=H) No Operation No Operation ILLEGAL ILLEGAL Termination Burst: Start the Precharge ILLEGAL Termination Burst: Start Write(optional AP) Termination Burst: Start Read(optional AP) Continue the Burst 4 8,9 8 13 13 4 4 3 3 13 13 7 4 6 6 5 Notes Rev 1.0 / Oct. 2009 16 111 Synchronous DRAM Memory 256Mbit H57V2622GMR Series CURRENT STATE TRUTH TABLE Current State Read CS RAS CAS WE H L L L L Write L L L H L L L Read with Auto Precharge L L L L H L L Write with Auto Precharge L L L L L H X L L L L H H H X L L L L H H H X L L L L H H H X X L L H H L L H X L L H H L L H X L L H H L L H X X L H L H L H H X L H L H L H H X L H L H L H H X X BA BA BA BA X X X BA BA BA BA X X X BA BA BA BA X X BA0/ BA1 X (Sheet 2 of 4) Command Amax-A0 X OP CODE X X Row Add. Col Add. A10 Col Add. A10 X X OP CODE X X Row Add. Col Add. A10 Col Add. A10 X X OP CODE X X Row Add. Col Add. A10 Col Add. A10 X X Description Device Deselect Mode Register Set Action Continue the Burst ILLEGAL 13 13 10 4 8 8,9 Notes Auto or Self Refresh ILLEGAL Precharge Bank Activate Write/WriteAP Read/ReadAP No Operation Device Deselect Mode Register Set Termination Burst: Start the Precharge ILLEGAL Termination Burst: Start Write(optional AP) Termination Burst: Start Read(optional AP) Continue the Burst Continue the Burst ILLEGAL 13 13 4,12 4,12 12 12 Auto or Self Refresh ILLEGAL Precharge Bank Activate Write/WriteAP Read/ReadAP No Operation Device Deselect Mode Register Set ILLEGAL ILLEGAL ILLEGAL ILLEGAL Continue the Burst Continue the Burst ILLEGAL 13 13 4,12 4,12 12 12 Auto or Self Refresh ILLEGAL Precharge Bank Activate Write/WriteAP Read/ReadAP No Operation Device Deselect ILLEGAL ILLEGAL ILLEGAL ILLEGAL Continue the Burst Continue the Burst Rev 1.0 / Oct. 2009 17 111 Synchronous DRAM Memory 256Mbit H57V2622GMR Series CURRENT STATE TRUTH TABLE Current State CS RAS CAS WE L L L L Precharging L L L H L L L L Row Activating L L L H L L L L Write Recovering L L L L L L L H H H X L L L L H H H X L L L L H H H L L H H L L H X L L H H L L H X L L H H L L H L H L H L H H X L H L H L H H X L H L H L H H X BA BA BA BA X X BA BA BA BA X X X BA BA BA BA X X BA0/ BA1 (Sheet 3 of 4) Command Amax-A0 OP CODE X X Row Add. Col Add. A10 Col Add. A10 X X OP CODE X X Row Add. Col Add. A10 Col Add. A10 X X OP CODE X X Row Add. Col Add. A10 Col Add. A10 X Description Mode Register Set ILLEGAL Action Notes 13 13 Auto or Self Refresh ILLEGAL Precharge Bank Activate Write/WriteAP Read/ReadAP No Operation Device Deselect Mode Register Set No Operation: Bank(s) idle after tRP ILLEGAL ILLEGAL ILLEGAL No Operation: Bank(s) idle after tRP No Operation: Bank(s) idle after tRP ILLEGAL 4,12 4,12 4,12 13 13 4,12 4,11,1 2 4,12 4,12 Auto or Self Refresh ILLEGAL Precharge Bank Activate Write/WriteAP Read/ReadAP No Operation Device Deselect Mode Register Set ILLEGAL ILLEGAL ILLEGAL ILLEGAL No Operation: Row Active after tRCD No Operation: Row Active after tRCD ILLEGAL 13 13 4,13 4,12 Auto or Self Refresh ILLEGAL Precharge Bank Activate Write/WriteAP Read/ReadAP No Operation ILLEGAL ILLEGAL Start Write: Optional AP(A10=H) Start Read: Optional AP(A10=H) No Operation: Row Active after tDPL 9 Rev 1.0 / Oct. 2009 18 111 Synchronous DRAM Memory 256Mbit H57V2622GMR Series CURRENT STATE TRUTH TABLE Current State Write Recovering CS RAS CAS WE H L L L Write Recovering with Auto Precharge L L L L H L L L L Refreshing L L L H L L L Mode Register Accessing L L L L H X L L L L H H H X L L L L H H H X L L L L H H H X X L L H H L L H X L L H H L L H X L L H H L L H X X L H L H L H H X L H L H L H H X L H L H L H H X X BA BA BA BA X X X BA BA BA BA X X X BA BA BA BA X X BA0/ BA1 X (Sheet 4 of 4) Command Amax-A0 X OP CODE X X Row Add. Col Add. A10 Col Add. A10 X X OP CODE X X Row Add. Col Add. A10 Col Add. A10 X X OP CODE X X Row Add. Col Add. A10 Col Add. A10 X X Description Device Deselect Mode Register Set Action No Operation: Row Active after tDPL ILLEGAL 13 13 4,13 4,12 4,12 4,9,12 Notes Auto or Self Refresh ILLEGAL Precharge Bank Activate Write/WriteAP Read/ReadAP No Operation Device Deselect Mode Register Set ILLEGAL ILLEGAL ILLEGAL ILLEGAL No Operation: Precharge after tDPL No Operation: Precharge after tDPL ILLEGAL 13 13 13 13 13 13 Auto or Self Refresh ILLEGAL Precharge Bank Activate Write/WriteAP Read/ReadAP No Operation Device Deselect Mode Register Set ILLEGAL ILLEGAL ILLEGAL ILLEGAL No Operation: idle after tRC No Operation: idle after tRC ILLEGAL 13 13 13 13 13 13 Auto or Self Refresh ILLEGAL Precharge Bank Activate Write/WriteAP Read/ReadAP No Operation Device Deselect ILLEGAL ILLEGAL ILLEGAL ILLEGAL No Operation: idle after 2 clock cycles No Operation: idle after 2 clock cycles Rev 1.0 / Oct. 2009 19 111 Synchronous DRAM Memory 256Mbit H57V2622GMR Series Note : 1. H: Logic High, L: Logic Low, X: Don't care, BA: Bank Address, AP: Auto Precharge. 2. All entries assume that CKE was active during the preceding clock cycle. 3. If both banks are idle and CKE is inactive, then in power down cycle 4. Illegal to bank in specified states. Function may be legal in the bank indicated by Bank Address, depending on the state of that bank. 5. If both banks are idle and CKE is inactive, then Self Refresh mode. 6. Illegal if tRCD is not satisfied. 7. Illegal if tRAS is not satisfied. 8. Must satisfy burst interrupt condition. 9. Must satisfy bus contention, bus turn around, and/or write recovery requirements. 10. Must mask preceding data which don't satisfy tDPL. 11. Illegal if tRRD is not satisfied 12. Illegal for single bank, but legal for other banks in multi-bank devices. 13. Illegal for all banks. Rev 1.0 / Oct. 2009 20 111 Synchronous DRAM Memory 256Mbit H57V2622GMR Series CKE Enable(CKE) Truth TABLE Current State CKE Previous Current Cycle Cycle H L L L L L L H L Power Down L H L X H H H H H L X H CS X H L L L L X X H L RAS X X H H H L X X X H L X X L H H H H All Banks Idle H H H H H H L L H H H H H L L L L L X X H L L L L H L L L L X X X H L L L X H L L L X (Sheet 1 of 2) Command CAS X X H H L X X X X H X L X X X X H L L X X H L L X WE X X H L X X X X X H X X L X X X X H L X X X H L X X X X X BA0, ADDR BA1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X Maintain Power Down Mode Refer to the idle State section of the Current State Truth Table Auto Refresh Mode Register Set Refer to the idle State section of the Current State Truth Table Entry Self Refresh Mode Register Set Power Down 4 4 3 3 3 4 3 3 3 ILLEGAL 2 INVALID Exit Self Refresh with Device Deselect Exit Self Refresh with No Operation ILLEGAL ILLEGAL ILLEGAL Maintain Self Refresh INVALID Power Down mode exit, all banks idle 1 2 Action Notes 1 2 2 2 2 2 Self Refresh OP CODE OP CODE X X Rev 1.0 / Oct. 2009 21 111 Synchronous DRAM Memory 256Mbit H57V2622GMR Series CKE Enable(CKE) Truth TABLE Current State CKE Previous Current Cycle Cycle H Any State other than listed above H CS RAS (Sheet 2 of 2) Command CAS WE BA0, ADDR BA1 X X Action Refer to operations of the Current State Truth Table Begin Clock Suspend next cycle Exit Clock Suspend next cycle Maintain Clock Suspend Notes X X X X H L L L H L X X X X X X X X X X X X X X X X X X Note : 1. For the given current state CKE must be low in the previous cycle. 2. When CKE has a low to high transition, the clock and other inputs are re-enabled asynchronously. When exiting power down mode, a NOP (or Device Deselect) command is required on the first positive edge of clock after CKE goes high. 3. The address inputs depend on the command that is issued. 4. The Precharge Power Down mode, the Self Refresh mode, and the Mode Register Set can only be entered from the all banks idle state. 5. When CKE has a low to high transition, the clock and other inputs are re-enabled asynchronously. When exiting deep power down mode, a NOP (or Device Deselect) command is required on the first positive edge of clock after CKE goes high and is maintained for a minimum 200usec. Rev 1.0 / Oct. 2009 22 111 Synchronous DRAM Memory 256Mbit H57V2622GMR Series PACKAGE INFORMATION 90 Ball FBGA, 8mm x 13mm x 1.1mm, 0.8mm pitch Unit [mm] 8.00 ± 0.10 0.8(Typ) 0 .8 6.40 BSC A1 Index Mark 0.8(Typ) 0.450 ± 0.05 Bottom View 5.6 ± 0.05 13.0 ± 0.10 11.20 BSC 3.20 ± 0.05 4.00 ± 0.05 0.340 ± 0.05 1.1max Side View Rev 1.0 / Oct. 2009 23