74FCT388915T10PYG

IDT74FCT388915T 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER (3-STATE) COMMERCIAL TEMPERATURE RANGE 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER (WITH 3-STATE) FEATURES: • 0.5 MICRON CMOS Technology • Input frequency range: 10MHz – f2Q Max. spec (FREQ_SEL = HIGH) • Max. output frequency: 150MHz • Pin and function compatible with FCT88915T, MC88915T • 5 non-inverting outputs, one inverting output, one 2x output, one ÷2 output; all outputs are TTL-compatible • 3-State outputs • Duty cycle distortion < 500ps (max.) • 32/–16mA drive at CMOS output voltage levels • VCC = 3.3V ± 0.3V • Inputs can be driven by 3.3V or 5V components • Available in 28 pin PLCC and SSOP packages IDT74FCT388915T 70/100/133/150 DESCRIPTION: The FCT388915T uses phase-lock loop technology to lock the frequency and phase of outputs to the input reference clock. It provides low skew clock distribution for high performance PCs and workstations. One of the outputs is fed back to the PLL at the FEEDBACK input resulting in essentially zero delay across the device. The PLL consists of the phase/ frequency detector, charge pump, loop filter and VCO. The VCO is designed for a 2Q operating frequency range of 40MHz to f2Q Max. The FCT388915T provides 8 outputs, the Q5 output is inverted from the Q outputs. The 2Q runs at twice the Q frequency and Q/2 runs at half the Q frequency. The FREQ_SEL control provides an additional ÷ 2 option in the output path. PLL _EN allows bypassing of the PLL, which is useful in static test modes. When PLL_EN is low, SYNC input may be used as a test clock. In this test mode, the input frequency is not limited to the specified range and the polarity of outputs is complementary to that in normal operation (PLL_EN = 1). The LOCK output attains logic HIGH when the PLL is in steady-state phase and frequency lock. When OE/RST is low, all the outputs are put in high impedance state and registers at Q, Q and Q/2 outputs are reset. The FCT388915T requires one external loop filter component as recommended in Figure 3. FUNCTIONAL BLOCK DIAGRAM FEED BAC K Voltage Controlled Oscilator LF REF_SEL PLL_EN 0 1 M ux 2Q ( ÷ 1) ( ÷ 2) 1M 0 u x D Q LOCK SYNC (0) SYNC (1) 0M u 1x Phase/Freq. Detector Charge Pum p Q0 Divide -By-2 FREQ_SEL OE/RST CP R Q D CP R Q R Q Q Q1 D CP Q2 D CP R D CP R Q3 Q Q4 D CP R D CP R Q Q5 Q Q/2 The IDT logo is a registered trademark of Integrated Device Technology, Inc. COMMERCIAL TEMPERATURE RANGE 1 OCTOBER 2008 DSC-4243/7 © 2004 Integrated Device Technology, Inc. IDT74FCT388915T 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER (3-STATE) COMMERCIAL TEMPERATURE RANGE PIN CONFIGURATION OE/RST GND VCC Q5 Q4 VCC GND Q5 VCC OE/RST FEEDBACK REF_SEL SYNC(0) VCC(AN) LF GND(AN) SYNC(1) FREQ_SEL GND Q0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 Q4 VCC 2Q Q/2 GND Q3 VCC Q2 GND LOCK PLL_EN GND Q1 VCC SYNC(0) VCC(AN) LF GND(AN) SYNC(1) 7 8 9 10 11 FEEDBK REF_SEL 5 6 4 3 2 1 28 27 26 25 24 23 22 21 20 19 Q/2 GND Q3 VCC Q2 GND LOCK 12 FREQ_SEL 13 GND 14 Q0 15 VCC 16 Q1 17 GND 18 PLL_EN SSOP TOP VIEW PLCC TOP VIEW PIN DESCRIPTION Pin Name SYNC(0) SYNC(1) REF_SEL FREQ_SEL FEEDBACK LF Q0-Q4 Q5 2Q Q/2 LOCK OE/RST PLL_EN I/O I I I I I I O O O O O I I Reference clock input Reference clock input Chooses reference between SYNC (0) & SYNC (1) (refer to functional block diagram) Selects between ÷ 1 and ÷ 2 frequency options (refer to functional block diagram) Feedback input to phase detector Input for external loop filter connection Clock output Inverted clock output Clock output (2 x Q frequency) Clock output (Q frequency ÷ 2) Indicates phase lock has been achieved (HIGH when locked) Asynchronous reset (active LOW) and output enable (active HIGH). When HIGH, outputs are enabled. When LOW, outputs are in HIGH impedance. Disables phase-lock for low frequency testing (refer to functional block diagram) Description 2 2Q IDT74FCT388915T 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER (3-STATE) COMMERCIAL TEMPERATURE RANGE ABSOLUTE MAXIMUM RATINGS(1) Symbol VTERM(2) VTERM(3) VTERM(4) TSTG IOUT Description Terminal Voltage with Respect to GND Terminal Voltage with Respect to GND Terminal Voltage with Respect to GND Storage Temperature DC Output Current Max –0.5 to +4.6 –0.5 to +7 –0.5 to VCC+0.5 –65 to +150 –60 to +60 Unit V V V °C mA CAPACITANCE (TA = +25°C, F = 1.0MHz) Symbol CIN COUT Parameter Input Capacitance Output Capacitance Conditions VIN = 0V VOUT = 0V Typ. 4.5 5.5 Max. 6 8 Unit pF pF NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Vcc terminals. 3. Input terminals. 4. Outputs and I/O terminals. DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Commercial: TA = 0°C to +70°C, VCC = 3.3V ± 0.3V Symbol VIH VIL IIH IIL IOZH IOZL VIK IODH IODL VOH VOL VH ICCL ICCH ICCZ Parameter Input HIGH Level Input LOW Level Input HIGH Current(4) Input LOW Current(4) High Impedance Output Current(4) (3-State Output Pins) Clamp Diode Voltage Output Drive Current Output Drive Current Output HIGH Voltage Output LOW Voltage Input Hysteresis Quiescent Power Supply Current VCC = Min., IIN = –18mA VCC = Min., VIN = VIH or VIL, VO = VCC = Min., VIN = VIH or VIL, VO = VCC = Min VCC = Min — VCC = Max.,VIN = GND or VCC (Test Mode) 1.5V(3) 1.5V(3) IOH = –16mA IOL = 32mA Test Conditions(1) Guaranteed Logic HIGH Level Guaranteed Logic LOW Level VCC = Max. VCC = Max. VCC = Max. VI = 5.5V VI = GND VI = VCC VI = GND Min. 2 — — — — — — –36 50 2.4(4) — — — Typ.(2) — — — — — — –0.7 — — 3.3 0.3 100 2 Max. 5.5 0.8 ±1 ±1 ±1 ±1 –1.2 — — — 0.5 — 6 V mA mA V V mV µA Unit V V µA µA µA NOTES: 1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 3.3V, +25°C ambient. 3. Not more than one output should be tested at one time. Duration of the test should not exceed one second. 4. VOH = VCC - 0.6V at rated current. 3 IDT74FCT388915T 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER (3-STATE) COMMERCIAL TEMPERATURE RANGE POWER SUPPLY CHARACTERISTICS Symbol ΔICC ICCD CPD IC Parameter Quiescent Power Supply Current TTL Inputs HIGH Dynamic Power Supply Current(4) Power Dissipation Capacitance Total Power Supply Current(6) VCC = Max. VIN = VCC –2.1V(3) VCC = Max. All Outputs Open 50% Duty Cycle VCC = Max. PLL_EN = 1, LOCK = 1, FEEDBACK = Q4 SYNC frequency = 50MHz. All bits loaded with 15pF VCC = Max. PLL_EN = 1, LOCK = 1, FEEDBACK = Q4 SYNC frequency = 50MHz. All bits loaded with 50Ω Thevenin termination and 20pF NOTES: 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 3.3V, +25°C ambient. 3. Per TTL driven input. All other inputs at VCC or GND. 4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations. It is derived with Q frequency as the reference. 5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested. 6. IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + DICC DHNT + ICCD (f) + ILOAD ICC = Quiescent Current (ICCL, ICCH and ICCZ) ΔICC = Power Supply Current for a TTL High Input (VIN = 3.4V) DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at DH ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL) f = 2Q Frequency ILOAD = Dynamic Current due to load. Test Conditions(1) VIN = VCC –0.6V(3) VIN = VCC VIN = GND Min. — — — — Typ.(2) 2 0.2 15 30 Max. 30 0.3 25 60 Unit µA mA/ MHz pF mA — 90 120 mA SYNCH INPUT TIMING REQUIRMENTS Symbol TRISE/FALL Parameter Rise/Fall Times, SYNC inputs (0.8V to 2V) Frequency Input Frequency, SYNC Inputs Duty Cycle Input Duty Cycle, SYNC Inputs 10(1) 25% 2Q fmax 75% MHz — Min. — Max. 3 Unit ns OUTPUT FREQUENCY SPECIFICATIONS Max. (2) Symbol f2Q fQ fQ/2 Parameter Operating frequency 2Q Output Operating frequency Q0-Q4, Q5 Outputs Operating frequency Q/2 Output Min. 40 20 10 70 70 35 17.5 100 100 50 25 133 (3) 133 66.7 33.3 150 (3) 150 75 37.5 Unit MHz MHz MHz NOTES: 1. Note 7 in "General AC Specification Notes" and Figure 3 describes this specification and its actual limits depending on the feedback connection. 2. Maximum operating frequency is guaranteed with the part in a phase locked condition and all outputs loaded. 3. At this frequency, 2Q cannot be used as feedback. 4 IDT74FCT388915T 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER (3-STATE) COMMERCIAL TEMPERATURE RANGE SWITCHING CHARACTERISTICS OVER OPERATING RANGE Symbol tRISE/FALL All Outputs tPULSE WIDTH (3) Q, Q, Q/2 outputs(3) tPULSE WIDTH 2Q Output(3) tPD tSKEWr (rising)(3,4) tSKEWf (falling)(3,4) tSKEWall (3,4) tLOCK(6) tPZH tPZL tPHZ tPLZ Parameter Rise/Fall Time (between 0.8V and 2V) Output Pulse Width Q0-Q4, Q5, Q/2, @ 1.5V Output Pulse Width 2Q @ 1.5V SYNC input to FEEDBACK delay Output to Output Skew between outputs 2Q, Q0-Q4, Q/2 (rising edges only) Output to Output Skew between outputs Q0-Q4 (falling edges only) Output to Output Skew 2Q, Q/2, Q0-Q4 rising, Q5 falling Time required to acquire Phase-Lock from time SYNC input signal is received Output Enable Time OE/RST (LOW-to-HIGH) to Q, 2Q, Q/2, Q Output Disable Time OE/RST (HIGH-to-LOW) to Q, 2Q, Q/2, Q 3(2) 14 ns 3(2) 14 ns 1(2) 10 ms — 800 ps — 250 ps Load = 50Ω to VCC/2, CL = 20pF 0.1µF from LF to Analog GND(5) Load = 50Ω to VCC/2, CL = 20pF — 600 ps +0.1 +1.3 ns 0.5tCYCLE – 1(5) 0.5tCYCLE + 1(5) ns Load = 50Ω to VCC/2, CL = 20pF 0.5tCYCLE – 0.8(5) 0.5tCYCLE + 0.8(5) ns Condition(1) Load = 50Ω to VCC/2, CL = 20pF Min. 0.2(2) Max. 2 Unit ns SYNC-FEEDBACK(3) (measured at SYNC0 or 1 and FEEDBACK input pins) GENERAL AC SPECIFICATION NOTES: 1. See test circuit and waveforms. 2. Minimum limits are guaranteed but not tested. 3. These specifications are guaranteed but not production tested. 4. Under equally loaded conditions, as specified under test conditions and at a fixed temperature and voltage. 5. tCYCLE = 1/frequency at which each output (Q, Q, Q/2 or 2Q) is expected to run. 6. With VCC fully powered-on and an output properly connected to the FEEDBACK pin, tLOCK Max. is with C1 = 0.1µF, tLOCK Min. is with C1 = 0.01µF. (Where C1 is loop filter capacitor shown in Figure 2). 7. The wiring diagrams and written explanations of Figure 3 demonstrate the input and output frequency relationships for various possible feedback configurations. The allowable SYNC input range to stay in the phase-locked condition is also indicated. There are two allowable SYNC frequency ranges, depending on whether FREQ_SEL is HIGH or LOW. Also it is possible to feed back the Q5 output, thus creating a 180° phase shift between the SYNC input and the Q outputs. The table below summarizes the allowable SYNC frequency range for each possible configuration. FREQ_SEL Level HIGH HIGH HIGH HIGH LOW LOW LOW LOW Feedback Output Q/2 Any Q (Q0-Q4) Q5 2X_Q Q/2 Any Q (Q0-Q4) Q5 2X_Q Allowable SYNC Input Frequency Range (MHZ) 10 to (2x_Q fMAX Spec)/4 20 to (2x_Q fMAX Spec)/2 20 to (2x_Q fMAX Spec)/2 40 to (2x_Q fMAX Spec) 5 to (2x_Q fMAX Spec)/8 10 to (2x_Q fMAX Spec)/4 10 to (2x_Q fMAX Spec)/4 20 to (2x_Q fMAX Spec)/2 Corresponding 2Q Output Frequency Range 40 to (2Q fMAX Spec) 40 to (2Q fMAX Spec) 40 to (2Q fMAX Spec) 40 to (2Q fMAX Spec) 20 to (2Q fMAX Spec)/2 20 to (2Q fMAX Spec)/2 20 to (2Q fMAX Spec)/2 20 to (2Q fMAX Spec)/2 Phase Relationship of the Q Outputs to Rising SYNC Edge 0° 0° 180° 0° 0° 0° 180° 0° 5 IDT74FCT388915T 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER (3-STATE) COMMERCIAL TEMPERATURE RANGE GENERAL AC SPECIFICATION NOTES (continued): 8. The tPD spec describes how the phase offset between the SYNC input and the output connected to the FEEDBACK input, varies with process, temperature and voltage. The phase measurements were made at 1.5V. The Q/2 output was terminated at the FEEDBACK input with 100Ω to VCC and 100Ω to ground. tPD measurements were made with the loop filter connection shown in Figure 1 below: External Loop Filter LF 0.1 μ F C1 Analog GND Figure 1 NOTES: 1. Figure 2 shows a loop filter and analog isolation scheme which will be effective in most applications. The following guidelines should be followed to ensure stable and jitter-free operation: a. All loop filter and analog isolation components should be tied as close to the package as possible. Stray current passing through the parasitics of long traces can cause undesirable voltage transients at the LF pin. b. The 10µF low frequency bypass capacitor and the 0.1µF high frequency bypass capacitor form a wide bandwidth filter that will minimize the 388915T's sensitivity to voltage transients from the system digital VCC supply and ground planes. If good bypass techniques are used on a board design near components which may cause digital VCC and ground noise, VCC step deviations should not occur at the 388915T's digital VCC supply. The purpose of the bypass filtering scheme shown in figure 2 is to give the 388915T additional protection from the power supply and ground plane transients that can occur in a high frequency, high speed digital system. c. The loop filter capacitor (0.1µF) can be a ceramic chip capacitor, the same as a standard bypass capacitor. 2. In addition to the bypass capacitors used in the analog filter of Figure 2 there should be a 0.1µF bypass capacitor between each of the other (digital) four VCC pins and the board ground plane. This will reduce output switching noise caused by the 388915T outputs, in addition to reducing potential for noise in the "analog" section of the chip. These bypass capacitors should also be tied as close to the 388915T package as possible. BOARD V CC ANALOG V CC 10 μ F Low Freq. Bypass 0.1 μ F High Freq. Bypass LF 0.1 μ F (Loop Filter Cap) Analog loop filter section of the FCT388915T ANALOG GND BOARD GND A separate Analog power supply is not necessary and should not be used. Following these prescribed guidelines is all that is necessary to use the FCT388915T in a normal digital environm ent. Figure 2. Recommended Loop Filter and Analog Isolation Scheme for the FCT388915T 6 IDT74FCT388915T 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER (3-STATE) COMMERCIAL TEMPERATURE RANGE 25 MHz feedback signal 50 MHz signal The frequency relationship shown here is applicable to all Q outputs (Q0, Q1, Q2, Q3 and Q4). 1:2 INPUT TO "Q" OUTPUT FREQUENCY RELATIONSHIP In this application, the Q/2 output is connected to the FEEDBACK input. The internal PLL will line up the positive edges of Q/2 and SYNC, thus the Q/2 frequency will equal the SYNC frequency. The Q outputs (Q0-Q4, Q5) will always run at 2X the Q/2 frequency, and the 2Q output will run at 4X the Q/2 frequency. 50 M Hz signal 12.5 M Hz feedback signal HIGH OE/ RST FEEDBACK LOW 25 MHz input REF_SEL SYNC(0) V CC (AN) LF GND(AN) FCT388915T Q2 Q3 Q5 Q4 2Q Q/2 12.5 MHz signal 25 MHz "Q" Clock O utputs HIGH FQ_SEL OE/ RST Q5 Q4 2Q Q/2 Q0 Q1 PLL_EN HIGH FEEDBACK LOW 12.5 MHz input REF_SEL SYNC(0) V CC (AN) LF GND(AN) FQ_SEL Q0 HIGH Q1 FCT388915T HIGH Q3 25 MHz "Q" Clock Outputs Q2 Allowable Input Frequency Range: 20MHz to (f2Q MAX Spec)/2 (for FREQ_SEL HIGH) 10MHz to (f2Q MAX Spec)/4 (for FREQ_SEL LOW) Figure 3b. Wiring Diagram and Frequency Relationships With Q4 Output Feedback PLL_EN HIGH 2:1 INPUT TO "Q" OUTPUT FREQUENCY RELATIONSHIP In this application, the 2Q output is connected to the FEEDBACK input. The internal PLL will line up the positive edges of 2Q and SYNC, thus the 2Q frequency will equal the SYNC frequency. The Q/2 output will always run at 1/4 the 2Q frequency, and the Q output will run at 1/2 the 2Q frequency. 50 MHz feedback signal HIGH OE/ RST Q5 Q4 2Q Q/2 12.5 MHz input 25 MHz "Q" Clock Outputs Allowable Input Frequency Range: 10MHz to ( f2Q MAX Spec)/4 (for FREQ_SEL HIGH) 5MHz to (f2Q MAX Spec)/8 (for FREQ_SEL LOW) Figure 3a. Wiring Diagram and Frequency Relationships With Q/ 2 Output Feedback FEEDBACK LOW REF_SEL SYNC(0) V CC (AN) LF GND(AN) FQ_SEL Q0 Q1 FCT388915T 1:1 INPUT TO "Q" OUTPUT FREQUENCY RELATIONSHIP In this application, the Q4 output is connected to the FEEDBACK input. The internal PLL will line up the positive edges of Q4 and SYNC, thus the Q4 frequency (and the rest of the "Q" outputs) will equal the SYNC frequency. The Q/2 output will always run at 1/2 the Q frequency, and the 2Q output will run at 2X the Q frequency. 50 MHz input Q3 Q2 PLL_EN HIGH HIGH Allowable Input Frequency Range: 40MHz to (f2Q MAX Spec) (for FREQ_SEL HIGH) 20MHz to (f2Q MAX Spec)/2 (for FREQ_SEL LOW) Figure 3c. Wiring Diagram and Frequency Relationships With 2Q Output Feedback 7 IDT74FCT388915T 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER (3-STATE) COMMERCIAL TEMPERATURE RANGE CMMU FCT388915T CLOCK @f SYSTEM CLO CK SO UR CE PLL 2f CPU CM MU CPU CARD CM MU CMMU CM MU CMMU FCT388915T PLL 2f CPU CM MU CPU CARD CM MU DISTRIBUTE CLO CK @ f CMMU CM MU CLOCK @ 2f at point of use FCT388915T PLL 2f MEMORY CO NTROL MEMORY CAR DS CLOCK @ 2f at point of use Figure 4. Multiprocessing Application Using the FCT388915T for Frequency Multiplication and Low Board-to-Board skew FCT388915T SYSTEM LEVEL TESTING FUNCTIONALITY When the PLL_EN pin is LOW, the PLL is bypassed and the FCT388915T is in low frequency "test mode". In test mode (with FREQ_SEL HIGH), the 2Q output is inverted from the selected SYNC input, and the Q outputs are divideby-2 (negative edge triggered) of the SYNC input, and the Q/2 output is divideby-4 (negative edge triggered). With FREQ_SEL LOW the 2Q output is divideby-2 of the SYNC, the Q outputs divide-by-4, and the Q/2 output divide-by-8. These relationships can be seen in the block diagram. A recommended test configuration would be to use SYNC0 or SYNC1 as the test clock input, and tie PLL_EN and REF_SEL together and connect them to the test select logic. This functionality is needed since most board-level testers run at 1 MHz or below, and theFCT 388915T cannot lock onto that low of an input frequency. In the test mode described above, any test frequency test can be used. 8 IDT74FCT388915T 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER (3-STATE) COMMERCIAL TEMPERATURE RANGE TEST CIRCUITS AND WAVEFORMS V CC VCC VCC 100 Ω V IN Pulse Generator D.U.T. 20pF RT 100 Ω CL V OU T Pulse Generator V IN D.U.T. 500 Ω V OU T GND 6.0V 500 Ω RT 50Ω to VCC/2, CL = 20pF Enable and Disable Test Circuit SYNC IN PUT (SYNC (1) or SYNC (0)) 1.5V t CYCLE SYNC IN PUT tP D V CC/2 FEED BAC K INPUT V CC/2 Q/2 OUTPUT t SKEW ALL t SKEW f t SKEW r t SKEW f t SKEW r V CC/2 t CYCLE "Q" OUTPUTS V CC/2 Q5 OUTPUT V CC/2 2Q OUTPUT Q0-Q4 OUTPUTS Propagation Delay, Output Skew (These waveforms represent the configuration of Figure 3a) NOTES: 1. The FCT388915T aligns rising edges of the FEEDBACK input and SYNC input, therefore the SYNC input does not require a 50% duty cycle. 2. All skew specs are measured between the VCC/2 crossing point of the appropriate output edges. All skews are specified as "windows", not as ± deviation around a center point. 3. If a Q ouput is connected to the FEEDBACK input (this situation is not shown), the Q output frequency would match the SYNC input frequency, the 2Q output would run at twice the SYNC frequency and the Q/2 output would run at half the SYNC frequency. ENABLE D ISABLE 3V SWITCH POSITION Test Disable Low Enable Low Disable High Enable High Switch 6V GND CONTROL INPUT t PZL OUTPUT NORMALLY LOW SW ITCH 6V t PZH OUTPUT NORMALLY HIGH SW ITCH GND 3V 1.5V 0.3V t PHZ 0.3V 1.5V 0V t PLZ 1.5V 0V 3V V OL VOH 0V Enable and Disable Times NOTES: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH. 2. Pulse Generator for All Pulses: tF ≤ 2.5ns; tR ≤ 2.5ns. DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. 9 IDT74FCT388915T 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER (3-STATE) COMMERCIAL TEMPERATURE RANGE ORDERING INFORMATION XXXX XX FCT Temp. Range Device Type XX Speed XX Package J JG PY PYG 70 (1) 100 (1) 133 (1) 150 388915T 74 (1) Plastic Leaded Chip Carrier PLCC - Green Small Shrink Outline IC SSOP - Green 70MHz Max. Frequency 100MHz Max. Frequency 133MHz Max. Frequency 150MHz Max. Frequency 3.3V Low skew PLL-based CMOS clock driver 0°C to +70°C NOTE: 1. When ordering GREEN packages, replace this numeric value with the equivalent letter below. B= 70 MHz (JG or PYG) C= 100 MHz (JG or PYG) D= 133 MHz (JG or PYG) E= 150 MHz (JG or PYG) For example, to order a 133MHz version, Green PLCC, the nomenclature would be 74FCT388915TDJG. CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 for SALES: 800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com for Tech Support: clockhelp@idt.com 10