843002AKI-40T

175MHZ, FEMTOCLOCKTM VCXO BASED SONET/SDH JITTER ATTENUATOR ICS843002I-40 Features • • • • • • • • • Two Differential LVPECL outputs Selectable CLKx, nCLKx differential input pairs CLKx, nCLKx pairs can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL or single-ended LVCMOS or LVTTL levels Maximum output frequency: 175MHz FemtoClock VCO frequency range: 560MHz - 700MHz RMS phase jitter @ 155.52MHz, using a 19.44MHz crystal (12kHz to 20MHz): 0.81ps (typical) Full 3.3V or mixed 3.3V core/2.5V output operating supply -40°C to 85°C ambient operating temperature Available in both standard (RoHS 5) and lead-free (RoHS 6) packages General Description The ICS843002I-40 is a member of the HiperClockS™ family of high performance clock HiPerClockS™ solutions from IDT. The ICS843002I-40 is a PLL based synchronous clock generator that is optimized for SONET/SDH line card applications where jitter attenuation and frequency translation is needed. The device contains two internal PLL stages that are cascaded in series. The first PLL stage uses a VCXO which is optimized to provide reference clock jitter attenuation and to be jitter tolerant, and to provide a stable reference clock for the 2nd PLL stage (typically 19.44MHz). The second PLL stage provides additional frequency multiplication (x32), and it maintains low output jitter by using a low phase noise FemtoClock VCO. PLL multiplication ratios are selected from internal lookup tables using device input selection pins. The device performance and the PLL multiplication ratios are optimized to support non-FEC (non-Forward Error Correction) SONET/SDH applications with rates up to OC-48 (SONET) or STM-16 (SDH). The VCXO requires the use of an external, inexpensive pullable crystal. VCXO PLL uses external passive loop filter components which are used to optimize the PLL loop bandwidth and damping characteristics for the given line card application. ICS The ICS843002I-40 includes two clock input ports. Each one can accept either a single-ended or differential input. Each input port also includes an activity detector circuit, which reports input clock activity through the LOR0 and LOR1 logic output pins. The two input ports feed an input selection mux. “Hitless switching” is accomplished through proper filter tuning. Jitter transfer and wander characteristics are influenced by loop filter tuning, and phase transient performance is influenced by both loop filter tuning and alignment error between the two reference clocks. Typical ICS843002I-40 configuration in SONET/SDH Systems: Pin Assignment XTAL_OUT XTAL_IN R_SEL2 R_SEL1 R_SEL0 VEE nCLK1 CLK1 32 31 30 29 28 27 26 25 LF1 LF0 ISET VCC CLK0 nCLK0 CLK_SEL nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 VCCA QA QA_SEL0 QA_SEL1 QB_SEL1 QB_SEL0 nQA nc 24 23 22 21 20 19 18 17 LOR0 LOR1 nc VCCO_LVCMOS VCCO_LVPECL nQB QB VEE • • • • VCXO 19.44MHz crystal Loop bandwidth: 50Hz - 250Hz Input Reference clock frequency selections: 19.44MHz, 38.88MHz, 77.76MHz, 155.52MHz, 311.04MHz, 622.08MHz Output clock frequency selections: 19.44MHz, 77.76MHz, 155.52MHz, Hi-Z ICS843002I-40 32-Lead VFQFN 5mm x 5mm x 0.925mm package body K Package Top View IDT™ / ICS™ VCXO BASED SONET/SDH JITTER ATTENUATOR 1 ICS843002AKI-40 REV. A NOVEMBER 7, 2007 ICS843002I-40 175MHZ, FEMTOCLOCKS™ VCXO BASED SONET/SDH JITTER ATTENUATOR Block Diagram XTAL_OUT 19.44 MHz ICS843002I-40 VCCO_LVCMOS CLK1 nCLK1 LOR1 CLK0 nCLK0 LOR0 Activity Detector Activity Detector ISET LF0 Phase Detector LF1 1 R Divider = 1, 2, 4, 8, 16 or 32 Divide by 32 Charge Pump and Loop Filter XTAL_IN External Loop Components 19.44 MHz Pullable xtal VCXO 0 Divide by 32 VCXO Jitter Attenuation PLL VCCO_LVPECL 622.08 MHz 110 110 CLK_SEL FemtoClock PLL x32 C0 Divider = 4, 8, 32, or HiZ 111 2 QA nQA QA_SEL1:0 QB nQB 2 111 R_SEL2:0 3 C1 Divider = 4, 8, 32, or HiZ QB_SEL1:0 NOTE: 19.44MHz VCXO crystal shown is typical for SONET/SDH device applications. IDT™ / ICS™ VCXO BASED SONET/SDH JITTER ATTENUATOR 2 ICS843002AKI-40 REV. A NOVEMBER 7, 2007 ICS843002I-40 175MHZ, FEMTOCLOCKS™ VCXO BASED SONET/SDH JITTER ATTENUATOR Table 1. Pin Descriptions Number 1, 2 3 4 5 6 7 8, 11, 22 9, 10 12, 13 14 15, 16 17, 27 18, 19 20 21 23 24 25 26 28, 29, 30 31, 32 Name LF1, LF0 ISET VCC CLK0 nCLK0 CLK_SEL nc QA_SEL1, QA_SEL0 QB_SEL1, QB_SEL0 VCCA QA, nQA VEE QB, nQB VCCO_LVPECL VCCO_LVCMOS LOR1 LOR0 nCLK1 CLK1 R_SEL0, R_SEL1, R_SEL2 XTAL_OUT, XTAL_IN Type Analog Input/Output Analog Input/Output Power Input Input Input Unused Input Input Power Output Power Output Power Power Output Output Input Input Input Pullup Pulldown Pulldown Pulldown Pullup Pullup Pulldown Pullup Pulldown Pulldown Description Loop filter connection node pins. Charge pump current setting pin. Core power supply pin. Non-inverting differential clock input. Inverting differential clock input. VCC/2 bias voltage when left floating. Input clock select. LVCMOS/LVTTL interface levels. See Table 3A. No connect. Output divider control for QA/nQA LVPECL outputs. LVCMOS/LVTTL interface levels.See Table 3C. Output divider control for QB/nQB LVPECL outputs. LVCMOS/LVTTL interface levels.See Table 3C. Analog supply pin. Differential clock output pair. LVPECL interface levels. Negative supply pins. Differential clock output pair. LVPECL interface levels. Output supply pin for LVPECL outputs. Output supply pin for LVCMOS/LVTTL outputs. Alarm output, loss of reference for CLK1/nCLK1. LVCMOS/LVTTL interface levels. Alarm output, loss of reference for CLK0/nCLK0. LVCMOS/LVTTL interface levels. Inverting differential clock input. VCC/2 bias voltage when left floating. Non-inverting differential clock input. Input divider selection. LVCMOS/LVTTL interface levels. See Table 3B. Crystal oscillator interface. The XTAL_IN is the input. XTAL_OUT is the output. Input NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol CIN RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Test Conditions Minimum Typical 4 50 50 Maximum Units pF kΩ kΩ IDT™ / ICS™ VCXO BASED SONET/SDH JITTER ATTENUATOR 3 ICS843002AKI-40 REV. A NOVEMBER 7, 2007 ICS843002I-40 175MHZ, FEMTOCLOCKS™ VCXO BASED SONET/SDH JITTER ATTENUATOR Function Tables Table 3A. Input Reference Selection Function Table Input CLK_SEL 0 1 Function Input Selected CLK0/nCLK0 CLK1/nCLK1 Table 3B. Input Reference Divider Selection Function Table Inputs R_SEL2 0 0 0 0 1 1 1 1 R_SEL1 0 0 1 1 0 0 1 1 R_SEL0 0 1 0 1 0 1 0 1 Function R Divider Value or State ÷1 ÷2 ÷4 ÷8 ÷16 ÷32 bypass VCXO PLL bypass VCXO and FemtoClock PLLs Table 3C. Output Divider Selection Function Table Inputs QX_SEL1 0 0 1 1 QX_SEL0 0 1 0 1 Function Output Divider Value or State Output QX/nQX (Hi-Z) ÷32 ÷8 ÷4 IDT™ / ICS™ VCXO BASED SONET/SDH JITTER ATTENUATOR 4 ICS843002AKI-40 REV. A NOVEMBER 7, 2007 ICS843002I-40 175MHZ, FEMTOCLOCKS™ VCXO BASED SONET/SDH JITTER ATTENUATOR Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Supply Voltage, VCC Inputs, VI Outputs, VO (LVCMOS) Outputs, IO (LVPECL) Continuos Current Surge Current Package Thermal Impedance, θJA Storage Temperature, TSTG Rating 4.6V -0.5V to VCC + 0.5V -0.5V to VCCO_LVCMOS + 0.5V 50mA 100mA 37°C/W (0 mps) -65°C to 150°C DC Electrical Characteristics Table 4A. Power Supply DC Characteristics, VCC = 3.3V±5%, VCCO_LVCMOS, VCCO_LVPECL = 3.3V±5% or 2.5V±5%, VEE = 0V, TA = -40°C to 85°C Symbol VCC VCCA VCCO_LVCMOS, VCCO_LVPECL IEE ICCA Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage 2.375 Power Supply Current Analog Supply Current 2.5 2.625 210 15 V mA mA Test Conditions Minimum 3.135 VCC – 0.15 3.135 Typical 3.3 3.3 3.3 Maximum 3.465 VCC 3.465 Units V V V IDT™ / ICS™ VCXO BASED SONET/SDH JITTER ATTENUATOR 5 ICS843002AKI-40 REV. A NOVEMBER 7, 2007 ICS843002I-40 175MHZ, FEMTOCLOCKS™ VCXO BASED SONET/SDH JITTER ATTENUATOR Table 4B. LVCMOS/LVTTL DC Characteristics, VCC = 3.3V±5%, VCCO_LVCMOS = 3.3V±5% or 2.5V±5%, VEE = 0V, TA = -40°C to 85°C Symbol VIH VIL Parameter Input High Voltage Input Low Voltage QA_SEL[0:1], QB_SEL[0:1] CLK_SEL, R_SEL[0:2] QA_SEL[0:1], QB_SEL[0:1] CLK_SEL, R_SEL[0:2] LOR0, LOR1 NOTE 1 LOR0, LOR1 NOTE 1 VCC = VIN = 3.465V VCC = VIN = 3.465V VCC = 3.465V, VIN = 0V VCC = 3.465V, VIN = 0V VCCO_LVCMOS = 3.465V VCCO_LVCMOS = 2.625V VCCO_LVCMOS = 3.465V or 2.625V -150 -5 2.6 1.8 0.5 Test Conditions Minimum 2 -0.3 Typical Maximum VCC + 0.3 0.8 5 150 Units V V µA µA µA µA V V V IIH Input High Current IIL Input Low Current VOH VOL Output High Voltage Output Low Voltage NOTE 1: Outputs terminated with 50Ω to VCCO_LVCMOS/2.See Parameter Measurement Information Section, “Output Load Test Circuit”. Table 4C. Differential DC Characteristics, VCC = 3.3V±5%, VCCO_LVPECL = 3.3V±5% or 2.5V±5%, VEE = 0V, TA = -40°C to 85°C Symbol IIH IIL VPP VCMR Parameter Input High Current CLK0/nCLK0, CLK1/nCLK1 CLK0, CLK1 Input Low Current nCLK0, nCLK1 Peak-to-Peak Voltage; NOTE 1 Common Mode Input Voltage; NOTE 1, 2 Test Conditions VCC = VIN = 3.465V VCC = 3.465V, VIN = 0V VCC = 3.465V, VIN = 0V -5 -150 0.15 VEE + 0.5 1.3 VCC – 0.85 Minimum Typical Maximum 150 Units µA µA µA V V NOTE 1: VIL cannot be less than -0.3V NOTE 2: Common mode input voltage is defined as VIH. Table 4D. LVPECL DC Characteristics, VCC = VCCO_LVPECL = 3.3V±5%, VEE = 0V, TA = -40°C to 85°C Symbol VOH VOL VSWING Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Peak-to-Peak Output Voltage Swing Test Conditions Minimum VCCO – 1.4 VCCO – 2.0 0.6 Typical Maximum VCCO – 0.9 VCCO – 1.7 1.0 Units V V V NOTE 1: Outputs terminated with 50Ω to VCCO_LVPECL – 2V. IDT™ / ICS™ VCXO BASED SONET/SDH JITTER ATTENUATOR 6 ICS843002AKI-40 REV. A NOVEMBER 7, 2007 ICS843002I-40 175MHZ, FEMTOCLOCKS™ VCXO BASED SONET/SDH JITTER ATTENUATOR Table 4E. LVPECL DC Characteristics, VCC = 3.3V±5%, VCCO_LVPECL = 2.5V±5%, VEE = 0V, TA = -40°C to 85°C Symbol VOH VOL VSWING Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Peak-to-Peak Output Voltage Swing Test Conditions Minimum VCCO – 1.4 VCCO – 2.0 0.4 Typical Maximum VCCO – 0.9 VCCO – 1.5 1.0 Units V V V NOTE 1: Outputs terminated with 50Ω to VCCO_LVPECL – 2V. AC Electrical Characteristics Table 5. AC Characteristics, VCC = 3.3V±5%, VCCO_LVCMOS = VCCO_LVPECL = 3.3V±5% or 2.5V±5%, VEE = 0V, TA = -40°C to 85°C Parameter Symbol fOUT tsk(o) tjit(Ø) tR / tF odc Output Frequency Output Skew; NOTE 1, 2 RMS Phase Jitter (Random); NOTE 3 Output Rise/Fall Time Output Duty Cycle 155.52MHz, Integration Range: 12kHz – 20MHz 20% to 80% 100 45 0.81 800 55 Test Conditions Minimum 19.44 Typical Maximum 175 50 Units MHz ps ps ps % See Parameter Measurement Information section. NOTE 1: Defined as skew between outputs at the same supply voltage, same frequency, and with equal load conditions. Measured at the output differential cross points. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Please refer to the Phase Noise plots. IDT™ / ICS™ VCXO BASED SONET/SDH JITTER ATTENUATOR 7 ICS843002AKI-40 REV. A NOVEMBER 7, 2007 ICS843002I-40 175MHZ, FEMTOCLOCKS™ VCXO BASED SONET/SDH JITTER ATTENUATOR Typical Phase Noise at 155.52MHz ➝ Filter 155.52MHz RMS Phase Jitter (Random) 12kHz to 20MHz = 0.81ps (typical) Noise Power dBc Hz ➝ Raw Phase Noise Data ➝ Phase Noise Result by adding a filter to raw data Offset Frequency (Hz) IDT™ / ICS™ VCXO BASED SONET/SDH JITTER ATTENUATOR 8 ICS843002AKI-40 REV. A NOVEMBER 7, 2007 ICS843002I-40 175MHZ, FEMTOCLOCKS™ VCXO BASED SONET/SDH JITTER ATTENUATOR Parameter Measurement Information 2.8V±0.04V 2V 2V 2V 2.8V±0.04V VCC, VCCO_LVPECL, VCCO_LVCMOS VCCA Qx SCOPE VCC, VCCO_LVCMOS VCCA VCCO_LVPECL Qx SCOPE LVPECL nQx VEE LVPECL VEE nQx -1.3V± 0.165V -0.5V± 0.125V 3.3V Core/3.3V LVPECL Output Load AC Test Circuit 3.3V Core/2.5V LVPECL Output Load AC Test Circuit VCC nQx Qx nCLK0, nCLK1 V PP Cross Points V CMR nQy Qy CLK0, CLK1 t sk(o) VEE Differential Input Level Output Skew Phase Noise Plot Noise Power 80% Phase Noise Mask 80% VSW I N G Clock Outputs f1 Offset Frequency f2 20% tR tF 20% RMS Jitter = Area Under the Masked Phase Noise Plot RMS Phase Jitter Output Rise/Fall Time IDT™ / ICS™ VCXO BASED SONET/SDH JITTER ATTENUATOR 9 ICS843002AKI-40 REV. A NOVEMBER 7, 2007 ICS843002I-40 175MHZ, FEMTOCLOCKS™ VCXO BASED SONET/SDH JITTER ATTENUATOR nQA, nQB QA, QB t PW t PERIOD odc = t PW t PERIOD x 100% Output Duty Cycle/Pulse Width/Period Application Information Recommendations for Unused Input and Output Pins Inputs: CLK/nCLK Inputs For applications not requiring the use of the differential input, both CLKx and nCLKx can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from CLKx to ground. Outputs: LVPECL Outputs All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. LVCMOS Outputs LVCMOS Control Pins All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. All unused LVCMOS output can be left floating. There should be no trace attached. IDT™ / ICS™ VCXO BASED SONET/SDH JITTER ATTENUATOR 10 ICS843002AKI-40 REV. A NOVEMBER 7, 2007 ICS843002I-40 175MHZ, FEMTOCLOCKS™ VCXO BASED SONET/SDH JITTER ATTENUATOR Power Supply Filtering Technique As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The ICS843002I-40 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VCC, VCCA, VCCO_LVPECL and VCCO_LVCMOS should be individually connected to the power supply plane through vias, and 0.01µF bypass capacitors should be used for each pin. Figure 1 illustrates this for a generic VCC pin and also shows that VCCA requires that an additional 10Ω resistor along with a 10µF bypass capacitor be connected to the VCCA pin. 3.3V VCC .01µF VCCA .01µF 10µF 10Ω Figure 1. Power Supply Filtering Wiring the Differential Input to Accept Single Ended Levels Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VCC/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. VCC R1 1K Single Ended Clock Input CLKx V_REF nCLKx C1 0.1u R2 1K Figure 2. Single-Ended Signal Driving Differential Input IDT™ / ICS™ VCXO BASED SONET/SDH JITTER ATTENUATOR 11 ICS843002AKI-40 REV. A NOVEMBER 7, 2007 ICS843002I-40 175MHZ, FEMTOCLOCKS™ VCXO BASED SONET/SDH JITTER ATTENUATOR Differential Clock Input Interface The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 3A to 3F show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example, in Figure 3A, the input termination applies for IDT HiPerClockS open emitter LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. 3.3V 3.3V 1.8V Zo = 50Ω Zo = 50Ω CLK Zo = 50Ω Zo = 50Ω nCLK nCLK CLK 3.3V LVPECL HiPerClockS Input R1 50 R2 50 HiPerClockS Input LVHSTL IDT HiPerClockS LVHSTL Driver R1 50 R2 50 R2 50 Figure 3A. HiPerClockS CLK/nCLK Input Driven by an IDT Open Emitter HiPerClockS LVHSTL Driver Figure 3B. HiPerClockS CLK/nCLK Input Driven by a 3.3V LVPECL Driver 3.3V 3.3V 3.3V Zo = 50Ω CLK CLK Zo = 50Ω nCLK R1 100 R3 125 R4 125 3.3V 3.3V Zo = 50Ω LVPECL R1 84 R2 84 HiPerClockS Input Zo = 50Ω nCLK LVDS Receiver Figure 3C. HiPerClockS CLK/nCLK Input Driven by a 3.3V LVPECL Driver Figure 3D. HiPerClockS CLK/nCLK Input Driven by a 3.3V LVDS Driver 2.5V 3.3V 2.5V R3 120 Zo = 60Ω R4 120 2.5V 3.3V *R3 33 Zo = 50Ω CLK Zo = 50Ω nCLK CLK Zo = 60Ω nCLK HCSL *R4 33 R1 50 R2 50 HiPerClockS Input SSTL R1 120 R2 120 HiPerClockS *Optional – R3 and R4 can be 0Ω Figure 3E. HiPerClockS CLK/nCLK Input Driven by a 3.3V HCSL Driver Figure 3F. HiPerClockS CLK/nCLK Input Driven by a 2.5V SSTL Driver IDT™ / ICS™ VCXO BASED SONET/SDH JITTER ATTENUATOR 12 ICS843002AKI-40 REV. A NOVEMBER 7, 2007 ICS843002I-40 175MHZ, FEMTOCLOCKS™ VCXO BASED SONET/SDH JITTER ATTENUATOR VFQFN EPAD Thermal Release Path In order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the Printed Circuit Board (PCB) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in Figure 4. The solderable area on the PCB, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. Sufficient clearance should be designed on the PCB between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. While the land pattern on the PCB provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are necessary to effectively conduct from the surface of the PCB to the ground plane(s). The land pattern must be connected to ground through these vias. The vias act as “heat pipes”. The number of vias (i.e. “heat pipes”) are application specific and dependent upon the package power dissipation as well as electrical conductivity requirements. Thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. Maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. It is recommended to use as many vias connected to ground as possible. It is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal land. Precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. Note: These recommendations are to be used as a guideline only. For further information, please refer to the Application Note on the Surface Mount Assembly of Amkor’s Thermally/Electrically Enhance Leadfame Base Package, Amkor Technology. PIN SOLDER EXPOSED HEAT SLUG SOLDER PIN PIN PAD GROUND PLANE THERMAL VIA LAND PATTERN (GROUND PAD) PIN PAD Figure 4. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale) IDT™ / ICS™ VCXO BASED SONET/SDH JITTER ATTENUATOR 13 ICS843002AKI-40 REV. A NOVEMBER 7, 2007 ICS843002I-40 175MHZ, FEMTOCLOCKS™ VCXO BASED SONET/SDH JITTER ATTENUATOR Termination for 3.3V LVPECL Outputs The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50Ω transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 5A and 5B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. 3.3V Zo = 50Ω FOUT Zo = 50Ω 50Ω 1 Z ((VOH + VOL) / (VCC – 2)) – 2 o 50Ω VCC - 2V RTT Zo = 50Ω 84Ω 84Ω FIN 125Ω Zo = 50Ω FOUT FIN 125Ω RTT = Figure 5A. 3.3V LVPECL Output Termination Figure 5B. 3.3V LVPECL Output Termination IDT™ / ICS™ VCXO BASED SONET/SDH JITTER ATTENUATOR 14 ICS843002AKI-40 REV. A NOVEMBER 7, 2007 ICS843002I-40 175MHZ, FEMTOCLOCKS™ VCXO BASED SONET/SDH JITTER ATTENUATOR Termination for 2.5V LVPECL Outputs Figure 6A and Figure 6B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50Ω to VCC – 2V. For VCCO = 2.5V, the VCCO – 2V is very close to ground level. The R3 in Figure 6B can be eliminated and the termination is shown in Figure 6C. 2.5V 2.5V 2.5V VCC = 2.5V R1 250 50Ω + 50Ω – 50Ω – R3 250 50Ω + VCC = 2.5V 2.5V LVPECL Driver R1 50 R2 50 2.5V LVPECL Driver R2 62.5 R4 62.5 R3 18 Figure 6A. 2.5V LVPECL Driver Termination Example Figure 6B. 2.5V LVPECL Driver Termination Example 2.5V VCC = 2.5V 50Ω + 50Ω – 2.5V LVPECL Driver R1 50 R2 50 Figure 6C. 2.5V LVPECL Driver Termination Example IDT™ / ICS™ VCXO BASED SONET/SDH JITTER ATTENUATOR 15 ICS843002AKI-40 REV. A NOVEMBER 7, 2007 ICS843002I-40 175MHZ, FEMTOCLOCKS™ VCXO BASED SONET/SDH JITTER ATTENUATOR Schematic Example Figure 7 shows a schematic example of the ICS843002I-40 application schematic. In this example, the device is operated at VCC = 3.3V. The decoupling capacitors should be located as close as possible to the power pin. The input is driven by a 3.3V LVPECL driver. The 2-pole filter example is used in this schematic. Please refer to the ICS843002I-40 datasheet for additional loop filter recommendations. Figure 7. ICS843002I-40 Schematic Example Loss of Reference Indicator (LOR0 and LOR1) Output Pins The LOR0 and LOR1 pins are controlled by the internal clock activity monitor circuits. The clock activity monitor circuits are clocked by the VCXO PLL phase detector feedback clock. The LOR output is asserted high if there are three consecutive feedback clock edges without any reference clock edges (in both cases, either a negative or positive transition is counted as an “edge”). The LOR output will otherwise be low. In a phase detector observation interval, the activity monitor does not flag excessive reference transitions as an error. The monitor only distinguishes between transitions occurring and no transitions occurring. IDT™ / ICS™ VCXO BASED SONET/SDH JITTER ATTENUATOR 16 ICS843002AKI-40 REV. A NOVEMBER 7, 2007 ICS843002I-40 175MHZ, FEMTOCLOCKS™ VCXO BASED SONET/SDH JITTER ATTENUATOR VCXO-PLL EXTERNAL COMPONENTS Choosing the correct external components and having a proper printed circuit board (PCB) layout is a key task for quality operation of the VCXO-PLL. In choosing a crystal, special precaution must be taken with the package and load capacitance (CL). In addition, frequency, accuracy and temperature range must also be considered. Since the pulling range of a crystal also varies with the package, it is recommended that a metal-canned package like HC49 be used. Generally, a metal-canned package has a larger pulling range than a surface mounted device (SMD). For crystal selection information, refer to the VCXO Crystal Selection Application Note. The crystal’s load capacitance CL characteristic determines it resonating frequency and is closely related to the VCXO tuning range. The total external capacitance seen by the crystal when installed on a board is the sum of the stray board capacitance, IC package lead capacitance, internal varactor capacitance and any installed tuning capacitors (CTUNE). If the crystal CL is greater than the total external capacitance, the VCXO will oscillate at a higher frequency than the crystal specification. If the crystal (CL) is lower than the total external capacitance, the VCXO will oscillate at a lower frequency than the crystal specification. In either case, the absolute tuning range is reduced. The correct value of CL is dependant on the characteristics of the VCXO. The recommended CL in the Crystal Parameter Table balances the tuning range by centering the tuning curve. The VCXO-PLL Loop Bandwidth Selection Table shows RS, CS and CP values for recommended high, mid and low loop bandwidth configurations. The device has been characterized using these parameters. For other configurations, refer to the Loop Filter Component Selection for VCXO Based PLLs Application Note. The crystal and external loop filter components should be kept as close as possible to the device. Loop filter and crystal traces should be kept short and separated from each other. Other signal traces should be kept separate and not run underneath the device, loop filter or crystal components. LF0 LF1 ISET RS CP CS RSET XTAL_IN CTUNE 19.44MHz CTUNE XTAL_OUT VCXO Characteristics Table Symbol kVCXO CV_LOW CV_HIGH Parameter VCXO Gain Low Varactor Capacitance High Varactor Capacitance Typical 5800 12.6 24.5 Units Hz/V pF pF VCXO-PLL Loop Bandwidth Selection Table Bandwidth 10Hz (Low) 70Hz (Mid) 100Hz (High) Crystal Frequency (MHz) 19.44 19.44 19.44 RS (kΩ) 5 10 15 CS (µF) 1.0 1.0 1.0 CP (µF) 0.10 0.01 0.01 RSET (kΩ) 9.5 4.75 4.75 Crystal Characteristics Symbol fN fT fS CL CO CO / C1 ESR Parameter Mode of Oscillation Frequency Frequency Tolerance Frequency Stability Operating Temperature Range Load Capacitance Shunt Capacitance Pullability Ratio Equivalent Series Resistance Drive Level Aging @ 25 0C IDT™ / ICS™ VCXO BASED SONET/SDH JITTER ATTENUATOR 17 Test Conditions Minimum Typical Fundamental 19.44 Maximum Units MHz ±20 ±20 -40 12 4 220 240 50 1 ±3 per year +85 ppm ppm 0 C pF pF Ω mW ppm ICS843002AKI-40 REV. A NOVEMBER 7, 2007 ICS843002I-40 175MHZ, FEMTOCLOCKS™ VCXO BASED SONET/SDH JITTER ATTENUATOR Power Considerations This section provides information on power dissipation and junction temperature for the ICS843002I-40. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS843002I-40 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • • Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 210mA = 727.65mW Power (outputs)MAX = 30mW/Loaded Output pair If all outputs are loaded, the total power is 2 * 30mW = 60mW Total Power_MAX (3.3V, with all outputs switching) = 727.65mW + 60mW = 787.65mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockS devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 37°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.788W * 37°C/W = 114.2°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (single layer or multi-layer). Table 6. Thermal Resistance θJA for 48 Lead TQFP, Forced Convection θJA by Velocity Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 37.0°C/W 1 32.4°C/W 2.5 29.0°C/W IDT™ / ICS™ VCXO BASED SONET/SDH JITTER ATTENUATOR 18 ICS843002AKI-40 REV. A NOVEMBER 7, 2007 ICS843002I-40 175MHZ, FEMTOCLOCKS™ VCXO BASED SONET/SDH JITTER ATTENUATOR 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 8. VCCO Q1 VOUT RL 50Ω VCCO - 2V Figure 8. LVPECL Driver Circuit and Termination To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage of VCCO – 2V. • For logic high, VOUT = VOH_MAX = VCCO_MAX – 0.9V (VCCO_MAX – VOH_MAX) = 0.9V For logic low, VOUT = VOL_MAX = VCCO_MAX – 1.7V (VCCO_MAX – VOL_MAX) = 1.7V • Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(VOH_MAX – (VCCO_MAX – 2V))/RL] * (VCCO_MAX – VOH_MAX) = [(2V - (VCCO_MAX – VOH_MAX))/RL] * (VCCO_MAX – VOH_MAX) = [(2V - 0.9V)/50Ω] * 0.9V = 19.8mW Pd_L = [(VOL_MAX – (VCCO_MAX – 2V))/RL] * (VCCO_MAX – VOL_MAX) = [(2V – (VCCO_MAX – VOL_MAX))/RL] * (VCCO_MAX – VOL_MAX) = [(2V – 1.7V)/50Ω] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW IDT™ / ICS™ VCXO BASED SONET/SDH JITTER ATTENUATOR 19 ICS843002AKI-40 REV. A NOVEMBER 7, 2007 ICS843002I-40 175MHZ, FEMTOCLOCKS™ VCXO BASED SONET/SDH JITTER ATTENUATOR Reliability Information Table 7. θJA vs. Air Flow Table for a 32 Lead VFQFN θJA vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 37.0°C/W 1 32.4°C/W 2.5 29.0°C/W Transistor Count The transistor count for ICS843002I-40 is: 5536 IDT™ / ICS™ VCXO BASED SONET/SDH JITTER ATTENUATOR 20 ICS843002AKI-40 REV. A NOVEMBER 7, 2007 ICS843002I-40 175MHZ, FEMTOCLOCKS™ VCXO BASED SONET/SDH JITTER ATTENUATOR Package Outline and Package Dimensions Package Outline - K Suffix for 32-Lead VFQFN S eating Plan e Ind ex Area N Anvil Singula tion A1 A3 L N 1 2 E2 (N -1)x e E2 2 (Re f.) (Ref.) (N -1)x e (R ef.) N &N Even e (Ty p.) 2 If N & N are Even OR To p View b A D Chamfer 4x 0.6 x 0.6 max OPTIONAL 0. 08 C C (Ref.) e D2 2 D2 N &N Odd Th er mal Ba se NOTE: The following package mechanical drawing is a generic drawing that applies to any pin count VFQFN package. This drawing is not intended to convey the actual pin count or pin layout of this device. The pin count and pinout are shown on the front page. The package dimensions are in Table 8 below. Table 8. Package Dimensions JEDEC Variation: VHHD-2/-4 All Dimensions in Millimeters Symbol Minimum Nominal Maximum N 32 A 0.80 1.00 A1 0 0.05 A3 0.25 Ref. b 0.18 0.25 0.30 8 ND & NE D&E 5.00 Basic D2 & E2 3.0 3.3 e 0.50 Basic L 0.30 0.40 0.50 Reference Document: JEDEC Publication 95, MO-220 IDT™ / ICS™ VCXO BASED SONET/SDH JITTER ATTENUATOR 21 ICS843002AKI-40 REV. A NOVEMBER 7, 2007 ICS843002I-40 175MHZ, FEMTOCLOCKS™ VCXO BASED SONET/SDH JITTER ATTENUATOR Ordering Information Table 9. Ordering Information Part/Order Number 843002AKI-40 843002AKI-40T 843002AKI-40LF 843002AKI-40LFT Marking ICS3002AI40 ICS3002AI40 ICS002AI40L ICS002AI40L Package 32 Lead VFQFN 32 Lead VFQFN “Lead-Free” 32 Lead VFQFN “Lead-Free” 32 Lead VFQFN Shipping Packaging Tray 2500 Tape & Reel Tray 2500 Tape & Reel Temperature -40°C to 85°C -40°C to 85°C -40°C to 85°C -40°C to 85°C NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications, such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDT™ / ICS™ VCXO BASED SONET/SDH JITTER ATTENUATOR 22 ICS843002AKI-40 REV. A NOVEMBER 7, 2007 ICS843002I-40 175MHZ, FEMTOCLOCKS™ VCXO BASED SONET/SDH JITTER ATTENUATOR Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 For Tech Support netcom@idt.com 480-763-2056 Corporate Headquarters Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.) Asia Pacific and Japan Integrated Device Technology Singapore (1997) Pte. Ltd. Reg. No. 199707558G 435 Orchard Road #20-03 Wisma Atria Singapore 238877 +65 6 887 5505 Europe IDT Europe, Limited 321 Kingston Road Leatherhead, Surrey KT22 7TU England +44 (0) 1372 363 339 Fax: +44 (0) 1372 378851 www.IDT.com © 2007 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA