175MHz, FemtoClock® VCXO Based
Sonet/SDH Jitter Attenuators
843002I-40
DATA SHEET
General Description
Features
The ICS843002I-40 is a PLL based synchronous clock generator
that is optimized for SONET/SDH line card applications where
jitter attenuation and frequency translation is needed. The device
contains two internal PLL stages that are cascaded in series. The
first PLL stage uses a VCXO which is optimized to provide
reference clock jitter attenuation and to be jitter tolerant, and to
provide a stable reference clock for the 2nd PLL stage (typically
19.44MHz). The second PLL stage provides additional frequency
multiplication (x32), and it maintains low output jitter by using a low
phase noise FemtoClock VCO. PLL multiplication ratios are
selected from internal lookup tables using device input selection
pins. The device performance and the PLL multiplication ratios are
optimized to support non-FEC (non-Forward Error Correction)
SONET/SDH applications with rates up to OC-48 (SONET) or
STM-16 (SDH). The VCXO requires the use of an external,
inexpensive pullable crystal. VCXO PLL uses external passive
loop filter components which are used to optimize the PLL loop
bandwidth and damping characteristics for the given line card
application.
•
•
•
Two Differential LVPECL outputs
•
•
•
Maximum output frequency: 175MHz
•
•
•
Full 3.3V or mixed 3.3V core/2.5V output operating supply
The ICS843002I-40 includes two clock input ports. Each one can
accept either a single-ended or differential input. Each input port
also includes an activity detector circuit, which reports input clock
activity through the LOR0 and LOR1 logic output pins. The two
input ports feed an input selection mux. “Hitless switching” is
accomplished through proper filter tuning. Jitter transfer and
wander characteristics are influenced by loop filter tuning, and
phase transient performance is influenced by both loop filter
tuning and alignment error between the two reference clocks.
Available in lead-free (RoHS 6) package
nCLK1
VEE
CLK1
R_SEL0
R_SEL1
R_SEL2
XTAL_IN
XTAL_OUT
32 31 30 29 28 27 26 25
LF1
1
24
LOR0
LF0
2
23
LOR1
ISET
3
22
nc
VCC
4
21
VCCO_LVCMOS
CLK0
5
20
VCCO_LVPECL
nCLK0
6
19
nQB
CLK_SEL
7
18
QB
17
VEE
nc
Output clock frequency selections:
19.44MHz, 77.76MHz, 155.52MHz, Hi-Z
8
nQA
QA
VCCA
QB_SEL0
9 10 11 12 13 14 15 16
QA_SEL1
•
-40°C to 85°C ambient operating temperature
nc
Input Reference clock frequency selections:
19.44MHz, 38.88MHz, 77.76MHz, 155.52MHz, 311.04MHz,
622.08MHz
RMS phase jitter @ 155.52MHz, using a 19.44MHz crystal
(12kHz to 20MHz): 0.81ps (typical)
QB_SEL1
•
FemtoClock VCO frequency range: 560MHz - 700MHz
QA_SEL0
VCXO 19.44MHz crystal
CLKx, nCLKx pairs can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL or
single-ended LVCMOS or LVTTL levels
Pin Assignment
Typical ICS843002I-40 configuration in SONET/SDH Systems:
•
Selectable CLKx, nCLKx differential input pairs
ICS843002I-40
32-Lead VFQFN
5mm x 5mm x 0.925mm package body
K Package
Top View
843002I-40 Rev C 9/4/14
1
©2014 Integrated Device Technology, Inc.
843002I-40 DATA SHEET
Block Diagram
LF0
VCCO_LVCMOS
CLK1
nCLK1
Activity
Detector
LOR1
1
R Divider =
1, 2, 4, 8,
16 or 32
Phase
Detector
Divide
by 32
LF1
Charge
Pump
and Loop
Filter
0
CLK0
nCLK0
XTAL_OUT
ISET
ICS843002I-40
19.44 MHz
Pullable
xtal
XTAL_IN
External
Loop
Components
VCXO
19.44 MHz
Divide
by 32
Activity
Detector
VCXO Jitter Attenuation PLL
LOR0
VCCO_LVPECL
622.08 MHz
CLK_SEL
110
FemtoClock
PLL
x32
110
QA
nQA
C0 Divider =
4, 8, 32, or HiZ
111
2
QA_SEL1:0
111
R_SEL2:0
QB
nQB
C1 Divider =
4, 8, 32, or HiZ
3
2
QB_SEL1:0
NOTE: 19.44MHz VCXO crystal shown is typical for SONET/SDH device applications.
175MHZ, FEMTOCLOCK® VCXO BASED SONET/SDH JITTER
ATTENUATORS
2
Rev C 9/4/14
843002I-40 DATA SHEET
Table 1. Pin Descriptions
Number
Name
Type
Description
1, 2
LF1, LF0
Analog
Input/Output
Loop filter connection node pins.
3
ISET
Analog
Input/Output
Charge pump current setting pin.
4
VCC
Power
5
CLK0
Input
Pulldown
Non-inverting differential clock input.
Inverting differential clock input. VCC/2 bias voltage when left floating.
Input clock select. LVCMOS/LVTTL interface levels. See Table 3A.
Core power supply pin.
6
nCLK0
Input
Pullup
Pulldown
7
CLK_SEL
Input
Pulldown
8, 11, 22
nc
Unused
9,
10
QA_SEL1,
QA_SEL0
Input
Pullup
Output divider control for QA/nQA LVPECL outputs.
LVCMOS/LVTTL interface levels.See Table 3C.
12,
13
QB_SEL1,
QB_SEL0
Input
Pullup
Output divider control for QB/nQB LVPECL outputs.
LVCMOS/LVTTL interface levels.See Table 3C.
14
VCCA
Power
Analog supply pin.
15, 16
QA, nQA
Output
Differential clock output pair. LVPECL interface levels.
17, 27
VEE
Power
Negative supply pins.
18, 19
QB, nQB
Output
Differential clock output pair. LVPECL interface levels.
20
VCCO_LVPECL
Power
Output supply pin for LVPECL outputs.
21
VCCO_LVCMOS
Power
Output supply pin for LVCMOS/LVTTL outputs.
23
LOR1
Output
Alarm output, loss of reference for CLK1/nCLK1.
LVCMOS/LVTTL interface levels.
24
LOR0
Output
Alarm output, loss of reference for CLK0/nCLK0.
LVCMOS/LVTTL interface levels.
25
nCLK1
Input
Pullup
Pulldown
Inverting differential clock input. VCC/2 bias voltage when left floating.
26
CLK1
Input
Pulldown
Non-inverting differential clock input.
28,
29,
30
R_SEL0,
R_SEL1,
R_SEL2
Input
Pulldown
Input divider selection. LVCMOS/LVTTL interface levels. See Table 3B.
31,
32
XTAL_OUT,
XTAL_IN
Input
No connect.
Crystal oscillator interface. The XTAL_IN is the input.
XTAL_OUT is the output.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
CIN
Input Capacitance
4
pF
RPULLUP
Input Pullup Resistor
50
k
RPULLDOWN
Input Pulldown Resistor
50
k
175MHZ, FEMTOCLOCK® VCXO BASED SONET/SDH JITTER
ATTENUATORS
Test Conditions
3
Minimum
Typical
Maximum
Units
Rev C 9/4/14
843002I-40 DATA SHEET
Function Tables
Table 3A. Input Reference Selection Function Table
Input
Function
CLK_SEL
Input Selected
0
CLK0/nCLK0
1
CLK1/nCLK1
Table 3B. Input Reference Divider Selection Function Table
Inputs
Function
R_SEL2
R_SEL1
R_SEL0
R Divider Value or State
0
0
0
÷1
0
0
1
÷2
0
1
0
÷4
0
1
1
÷8
1
0
0
÷16
1
0
1
÷32
1
1
0
bypass VCXO PLL
1
1
1
bypass VCXO and FemtoClock PLLs
Table 3C. Output Divider Selection Function Table
Inputs
Function
QX_SEL1
QX_SEL0
Output Divider Value or State
0
0
Output QX/nQX (High-Impedance)
0
1
÷32
1
0
÷8
1
1
÷4
Rev C 9/4/14
4
175MHZ, FEMTOCLOCK® VCXO BASED SONET/SDH JITTER
ATTENUATORS
843002I-40 DATA SHEET
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Rating
Supply Voltage, VCC
4.6V
Inputs, VI
-0.5V to VCC + 0.5V
Outputs, VO (LVCMOS)
-0.5V to VCCO_LVCMOS + 0.5V
Outputs, IO (LVPECL)
Continuos Current
Surge Current
50mA
100mA
Package Thermal Impedance, JA
37C/W (0 mps)
Storage Temperature, TSTG
-65C to 150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VCC = 3.3V±5%, VCCO_LVCMOS, VCCO_LVPECL = 3.3V±5% or 2.5V±5%, VEE = 0V,
TA = -40°C to 85°C
Symbol
Parameter
VCC
Core Supply Voltage
VCCA
Analog Supply Voltage
VCCO_LVCMOS,
VCCO_LVPECL
Output Supply Voltage
IEE
ICCA
Minimum
Typical
Maximum
Units
3.135
3.3
3.465
V
VCC – 0.15
3.3
VCC
V
3.135
3.3
3.465
V
2.375
2.5
2.625
V
Power Supply Current
210
mA
Analog Supply Current
15
mA
175MHZ, FEMTOCLOCK® VCXO BASED SONET/SDH JITTER
ATTENUATORS
Test Conditions
5
Rev C 9/4/14
843002I-40 DATA SHEET
Table 4B. LVCMOS/LVTTL DC Characteristics, VCC = 3.3V±5%, VCCO_LVCMOS = 3.3V±5% or 2.5V±5%, VEE = 0V,
TA = -40°C to 85°C
Symbol
Parameter
VIH
Input High Voltage
VIL
Input Low Voltage
IIH
IIL
VOH
VOL
Test Conditions
Minimum
Typical
Maximum
Units
2
VCC + 0.3
V
-0.3
0.8
V
QA_SEL[0:1],
QB_SEL[0:1]
VCC = VIN = 3.465V
5
µA
CLK_SEL,
R_SEL[0:2]
VCC = VIN = 3.465V
150
µA
Input High Current
QA_SEL[0:1],
QB_SEL[0:1]
VCC = 3.465V, VIN = 0V
-150
µA
CLK_SEL,
R_SEL[0:2]
VCC = 3.465V, VIN = 0V
-5
µA
VCCO_LVCMOS = 3.465V,
IOH = 1mA
2.6
V
VCCO_LVCMOS = 2.625V,
IOH = 1mA
1.8
V
Input Low Current
Output High Voltage
Output Low Voltage
LOR0, LOR1
LOR0, LOR1
VCCO_LVCMOS = 3.465V or
2.625V, IOL= -1mA
0.5
V
Table 4C. Differential DC Characteristics, VCC = 3.3V±5%, VCCO_LVPECL = 3.3V±5% or 2.5V±5%, VEE = 0V,
TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
IIH
Input High Current
IIL
Input Low Current
VPP
Peak-to-Peak Voltage; NOTE 1
VCMR
Common Mode Input Voltage; NOTE 1, 2
Minimum
Typical
Maximum
Units
150
µA
CLK0/nCLK0,
CLK1/nCLK1
VCC = VIN = 3.465V
CLK0, CLK1
VCC = 3.465V, VIN = 0V
-5
µA
nCLK0, nCLK1
VCC = 3.465V, VIN = 0V
-150
µA
0.15
1.3
V
VEE + 0.5
VCC – 0.85
V
NOTE 1: VIL cannot be less than -0.3V
NOTE 2: Common mode input voltage is defined as VIH.
Table 4D. LVPECL DC Characteristics, VCC = VCCO_LVPECL = 3.3V±5%, VEE = 0V, TA = -40°C to 85°C
Symbol
Parameter
VOH
Output High Voltage; NOTE 1
VOL
Output Low Voltage; NOTE 1
VSWING
Peak-to-Peak Output Voltage Swing
Test Conditions
Minimum
Typical
Maximum
Units
VCCO – 1.4
VCCO – 0.9
V
VCCO – 2.0
VCCO – 1.7
V
0.6
1.0
V
NOTE 1: Outputs terminated with 50 to VCCO_LVPECL – 2V.
Rev C 9/4/14
6
175MHZ, FEMTOCLOCK® VCXO BASED SONET/SDH JITTER
ATTENUATORS
843002I-40 DATA SHEET
Table 4E. LVPECL DC Characteristics, VCC = 3.3V±5%, VCCO_LVPECL = 2.5V±5%, VEE = 0V, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
VOH
Output High Voltage; NOTE 1
VOL
Output Low Voltage; NOTE 1
VSWING
Peak-to-Peak Output Voltage Swing
Minimum
Typical
Maximum
Units
VCCO – 1.4
VCCO – 0.9
V
VCCO – 2.0
VCCO – 1.5
V
0.4
1.0
V
NOTE 1: Outputs terminated with 50 to VCCO_LVPECL – 2V.
AC Electrical Characteristics
Table 5. AC Characteristics, VCC = 3.3V±5%, VCCO_LVCMOS = VCCO_LVPECL = 3.3V±5% or 2.5V±5%, VEE = 0V,
TA = -40°C to 85°C
Symbol
Parameter
fOUT
Output Frequency
tsk(o)
Output Skew; NOTE 1, 2
tjit(Ø)
RMS Phase Jitter (Random);
NOTE 3
tR / tF
Output Rise/Fall Time
odc
Output Duty Cycle
Test Conditions
Minimum
Typical
19.44
155.52MHz,
Integration Range: 12kHz – 20MHz
20% to 80%
Maximum
Units
175
MHz
150
ps
0.81
ps
100
800
ps
45
55
%
See Parameter Measurement Information section.
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: Defined as skew between outputs at the same supply voltage, same frequency, and with equal load conditions.
Measured at the output differential cross points.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Please refer to the Phase Noise plots.
175MHZ, FEMTOCLOCK® VCXO BASED SONET/SDH JITTER
ATTENUATORS
7
Rev C 9/4/14
843002I-40 DATA SHEET
➝
Typical Phase Noise at 155.52MHz
Filter
➝
Raw Phase Noise Data
➝
Noise Power dBc
Hz
155.52MHz
RMS Phase Jitter (Random)
12kHz to 20MHz = 0.81ps (typical)
Phase Noise Result by adding
a filter to raw data
Offset Frequency (Hz)
Rev C 9/4/14
8
175MHZ, FEMTOCLOCK® VCXO BASED SONET/SDH JITTER
ATTENUATORS
843002I-40 DATA SHEET
Parameter Measurement Information
2.8V ± 0.04V
2V
2V
2.8V ± 0.04V
2V
VCC,
VCCO_LVCMOS
VCC,
VCCO_LVPECL,
VCCO_LVCMOS
Qx
SCOPE
VCCA
VCCA
VCCO_LVPECL
nQx
VEE
-1.3V ± 0.165V
-0.5V ± 0.125V
3.3V Core/3.3V LVPECL Output Load AC Test Circuit
3.3V Core/2.5V LVPECL Output Load AC Test Circuit
VCC
nQx
Qx
nCLK0, nCLK1
V
V
Cross Points
PP
nQy
CMR
CLK0, CLK1
Qy
VEE
Differential Input Level
Output Skew
Noise Power
Phase Noise Plot
nQA, nQB
Phase Noise Mask
QA, QB
f1
Offset Frequency
f2
RMS Jitter = Area Under the Masked Phase Noise Plot
Output Rise/Fall Time
RMS Phase Jitter
175MHZ, FEMTOCLOCK® VCXO BASED SONET/SDH JITTER
ATTENUATORS
9
Rev C 9/4/14
843002I-40 DATA SHEET
nQA, nQB
QA, QB
Output Duty Cycle/Pulse Width/Period
Application Information
Recommendations for Unused Input and Output Pins
Inputs:
Outputs:
CLK/nCLK Inputs
LVPECL Outputs
For applications not requiring the use of the differential input, both
CLKx and nCLKx can be left floating. Though not required, but for
additional protection, a 1k resistor can be tied from CLKx to
ground.
All unused LVPECL outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential output
pair should either be left floating or terminated.
LVCMOS Outputs
LVCMOS Control Pins
All unused LVCMOS output can be left floating. There should be no
trace attached.
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1k resistor can be used.
Rev C 9/4/14
10
175MHZ, FEMTOCLOCK® VCXO BASED SONET/SDH JITTER
ATTENUATORS
843002I-40 DATA SHEET
Power Supply Filtering Technique
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter
performance, power supply isolation is required. The
ICS843002I-40 provides separate power supplies to isolate any
high switching noise from the outputs to the internal PLL. VCC,
VCCA, VCCO_LVPECL and VCCO_LVCMOS should be individually
connected to the power supply plane through vias, and 0.01µF
bypass capacitors should be used for each pin. Figure 1 illustrates
this for a generic VCC pin and also shows that VCCA requires that
an additional 10 resistor along with a 10F bypass capacitor be
connected to the VCCA pin.
Figure 1. Power Supply Filtering
Wiring the Differential Input to Accept Single Ended Levels
Figure 2 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = VCC/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio of
R1 and R2 might need to be adjusted to position the V_REF in the
center of the input voltage swing. For example, if the input clock
swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and
R2/R1 = 0.609.
VCC
R1
1K
Single Ended Clock Input
CLKx
V_REF
nCLKx
C1
0.1u
R2
1K
Figure 2. Single-Ended Signal Driving Differential Input
175MHZ, FEMTOCLOCK® VCXO BASED SONET/SDH JITTER
ATTENUATORS
11
Rev C 9/4/14
843002I-40 DATA SHEET
Differential Clock Input Interface
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both VSWING and VOH must meet the
VPP and VCMR input requirements. Figures 3A to 3F show interface
examples for the HiPerClockS CLK/nCLK input driven by the most
common driver types. The input interfaces suggested here are
examples only. Please consult with the vendor of the driver
component to confirm the driver termination requirements. For
example, in Figure 3A, the input termination applies for IDT
HiPerClockS open emitter LVHSTL drivers. If you are using an
LVHSTL driver from another vendor, use their termination
recommendation.
3.3V
1.8V
Zo = 50Ω
CLK
Zo = 50Ω
nCLK
Differential
Input
LVHSTL
IDT
LVHSTL Driver
R1
50Ω
R2
50Ω
Figure 3A. HiPerClockS CLK/nCLK Input
Driven by an IDT Open Emitter
HiPerClockS LVHSTL Driver
Figure 3B. HiPerClockS CLK/nCLK Input
Driven by a 3.3V LVPECL Driver
Figure 3C. HiPerClockS CLK/nCLK Input
Driven by a 3.3V LVPECL Driver
Figure 3D. HiPerClockS CLK/nCLK Input
Driven by a 3.3V LVDS Driver
3.3V
2.5V
3.3V
3.3V
2.5V
R3
120Ω
*R3
R4
120Ω
Zo = 60Ω
CLK
CLK
Zo = 60Ω
nCLK
nCLK
HCSL
*R4
Differential
Input
SSTL
R1
120Ω
Differential
Input
Figure 3F. HiPerClockS CLK/nCLK Input
Driven by a 2.5V SSTL Driver
Figure 3E. HiPerClockS CLK/nCLK Input
Driven by a 3.3V HCSL Driver
Rev C 9/4/14
R2
120Ω
12
175MHZ, FEMTOCLOCK® VCXO BASED SONET/SDH JITTER
ATTENUATORS
843002I-40 DATA SHEET
VFQFN EPAD Thermal Release Path
In order to maximize both the removal of heat from the package and
the electrical performance, a land pattern must be incorporated on
the Printed Circuit Board (PCB) within the footprint of the package
corresponding to the exposed metal pad or exposed heat slug on the
package, as shown in Figure 4. The solderable area on the PCB, as
defined by the solder mask, should be at least the same size/shape
as the exposed pad/slug area on the package to maximize the
thermal/electrical performance. Sufficient clearance should be
designed on the PCB between the outer edges of the land pattern
and the inner edges of pad pattern for the leads to avoid any shorts.
and dependent upon the package power dissipation as well as
electrical conductivity requirements. Thus, thermal and electrical
analysis and/or testing are recommended to determine the minimum
number needed. Maximum thermal and electrical performance is
achieved when an array of vias is incorporated in the land pattern. It
is recommended to use as many vias connected to ground as
possible. It is also recommended that the via diameter should be 12
to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is
desirable to avoid any solder wicking inside the via during the
soldering process which may result in voids in solder between the
exposed pad/slug and the thermal land. Precautions should be taken
to eliminate any solder voids between the exposed heat slug and the
land pattern. Note: These recommendations are to be used as a
guideline only. For further information, please refer to the Application
Note on the Surface Mount Assembly of Amkor’s
Thermally/Electrically Enhance Leadframe Base Package, Amkor
Technology.
While the land pattern on the PCB provides a means of heat transfer
and electrical grounding from the package to the board through a
solder joint, thermal vias are necessary to effectively conduct from
the surface of the PCB to the ground plane(s). The land pattern must
be connected to ground through these vias. The vias act as “heat
pipes”. The number of vias (i.e. “heat pipes”) are application specific
PIN
PIN PAD
SOLDER
EXPOSED HEAT SLUG
GROUND PLANE
THERMAL VIA
SOLDER
LAND PATTERN
(GROUND PAD)
PIN
PIN PAD
Figure 4. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)
Rev C 9/4/14
13
175MHZ, FEMTOCLOCK® VCXO BASED SONET/SDH JITTER
ATTENUATORS
843002I-40 DATA SHEET
Termination for 3.3V LVPECL Outputs
The clock layout topology shown below is a typical termination for
LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
transmission lines. Matched impedance techniques should be
used to maximize operating frequency and minimize signal
distortion. Figures 5A and 5B show two different layouts which are
recommended only as guidelines. Other suitable clock layouts may
exist and it would be recommended that the board designers
simulate to guarantee compatibility across all printed circuit and
clock component process variations.
The differential output is a low impedance follower output that
generate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must be
used for functionality. These outputs are designed to drive 50
R3
125
3.3V
R4
125
3.3V
3.3V
Zo = 50
+
_
LVPECL
Input
Zo = 50
R1
84
Figure 5A. 3.3V LVPECL Output Termination
Rev C 9/4/14
R2
84
Figure 5B. 3.3V LVPECL Output Termination
14
175MHZ, FEMTOCLOCK® VCXO BASED SONET/SDH JITTER
ATTENUATORS
843002I-40 DATA SHEET
Termination for 2.5V LVPECL Outputs
ground level. The R3 in Figure 6B can be eliminated and the
termination is shown in Figure 6C.
Figure 6A and Figure 6B show examples of termination for 2.5V
LVPECL driver. These terminations are equivalent to terminating
50 to VCC – 2V. For VCCO = 2.5V, the VCCO – 2V is very close to
2.5V
VCC = 2.5V
2.5V
2.5V
VCC = 2.5V
R1
250Ω
50Ω
R3
250Ω
+
50Ω
50Ω
+
–
50Ω
2.5V LVPECL Driver
–
R1
50Ω
2.5V LVPECL Driver
R2
62.5Ω
R2
50Ω
R4
62.5Ω
R3
18Ω
Figure 6A. 2.5V LVPECL Driver Termination Example
Figure 6B. 2.5V LVPECL Driver Termination Example
2.5V
VCC = 2.5V
50Ω
+
50Ω
–
2.5V LVPECL Driver
R1
50Ω
R2
50Ω
Figure 6C. 2.5V LVPECL Driver Termination Example
175MHZ, FEMTOCLOCK® VCXO BASED SONET/SDH JITTER
ATTENUATORS
15
Rev C 9/4/14
843002I-40 DATA SHEET
Schematic Example
driver. The 2-pole filter example is used in this schematic. Please
refer to the ICS843002I-40 datasheet for additional loop filter
recommendations.
Figure 7 shows a schematic example of the ICS843002I-40
application schematic. In this example, the device is operated at
VCC = 3.3V. The decoupling capacitors should be located as close
as possible to the power pin. The input is driven by a 3.3V LVPECL
Figure 7. ICS843002I-40 Schematic Example
Loss of Reference Indicator (LOR0 and LOR1) Output Pins
The LOR0 and LOR1 pins are controlled by the internal clock
activity monitor circuits. The clock activity monitor circuits are
clocked by the VCXO PLL phase detector feedback clock. The
LOR output is asserted high if there are three consecutive
feedback clock edges without any reference clock edges (in both
Rev C 9/4/14
cases, either a negative or positive transition is counted as an
“edge”). The LOR output will otherwise be low. In a phase detector
observation interval, the activity monitor does not flag excessive
reference transitions as an error. The monitor only distinguishes
between transitions occurring and no transitions occurring.
16
175MHZ, FEMTOCLOCK® VCXO BASED SONET/SDH JITTER
ATTENUATORS
843002I-40 DATA SHEET
VCXO-PLL EXTERNAL COMPONENTS
Choosing the correct external components and having a proper
printed circuit board (PCB) layout is a key task for quality operation
of the VCXO-PLL. In choosing a crystal, special precaution must
be taken with the package and load capacitance (CL). In addition,
frequency, accuracy and temperature range must also be
considered. Since the pulling range of a crystal also varies with
the package, it is recommended that a metal-canned package like
HC49 be used. Generally, a metal-canned package has a larger
pulling range than a surface mounted device (SMD). For crystal
selection information, refer to the VCXO Crystal Selection
Application Note.
reduced. The correct value of CL is dependant on the
characteristics of the VCXO. The recommended CL in the Crystal
Parameter Table balances the tuning range by centering the
tuning curve.
The VCXO-PLL Loop Bandwidth Selection Table shows RS, CS
and CP values for recommended high, mid and low loop bandwidth
configurations. The device has been characterized using these
parameters. For other configurations, refer to the Loop Filter
Component Selection for VCXO Based PLLs Application Note.
The crystal and external loop
filter components should be
kept as close as possible to the
device. Loop filter and crystal
traces should be kept short and
separated from each other.
Other signal traces should be
kept separate and not run
underneath the device, loop
filter or crystal components.
The crystal’s load capacitance CL characteristic determines it
resonating frequency and is closely related to the VCXO tuning
range. The total external capacitance seen by the crystal when
installed on a board is the sum of the stray board capacitance, IC
package lead capacitance, internal varactor capacitance and any
installed tuning capacitors (CTUNE).
If the crystal CL is greater than the total external capacitance, the
VCXO will oscillate at a higher frequency than the crystal
specification. If the crystal (CL) is lower than the total external
capacitance, the VCXO will oscillate at a lower frequency than the
crystal specification. In either case, the absolute tuning range is
LF0
LF1
ISET
RS
CP
RSET
CS
XTAL_IN
CTUNE
19.44MHz
XTAL_OUT
CTUNE
VCXO Characteristics Table
Symbol
Parameter
Typical
Units
kVCXO
VCXO Gain
5800
Hz/V
CV_LOW
Low Varactor Capacitance
12.6
pF
CV_HIGH
High Varactor Capacitance
24.5
pF
VCXO-PLL Loop Bandwidth Selection Table
Bandwidth
Crystal Frequency (MHz)
RS (k)
CS (µF)
CP (µF)
RSET (k)
10Hz (Low)
19.44
5
1.0
0.10
9.5
70Hz (Mid)
19.44
10
1.0
0.01
4.75
100Hz (High)
19.44
15
1.0
0.01
4.75
Crystal Characteristics
Symbol
Parameter
Test Conditions
Minimum
fN
Frequency
fT
Frequency Tolerance
±20
ppm
fS
Frequency Stability
±20
ppm
Mode of Oscillation
Typical
Maximum
Units
Fundamental
19.44
Operating Temperature Range
-40
MHz
+85
0
C
CL
Load Capacitance
12
pF
CO
Shunt Capacitance
4
pF
CO / C1
Pullability Ratio
ESR
Equivalent Series Resistance
220
50
Drive Level
Aging @ 25 0C
175MHZ, FEMTOCLOCK® VCXO BASED SONET/SDH JITTER
ATTENUATORS
240
17
1
mW
±3 per year
ppm
Rev C 9/4/14
843002I-40 DATA SHEET
Power Considerations
This section provides information on power dissipation and junction temperature for the ICS843002I-40.
Equations and example calculations are also provided.
1.
Power Dissipation.
The total power dissipation for the ICS843002I-40 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 210mA = 727.65mW
•
Power (outputs)MAX = 30mW/Loaded Output pair
If all outputs are loaded, the total power is 2 * 30mW = 60mW
Total Power_MAX (3.3V, with all outputs switching) = 727.65mW + 60mW = 787.65mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device.
The maximum recommended junction temperature for HiPerClockS devices is 125°C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA
Tj = Junction Temperature
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow
and a multi-layer board, the appropriate value is 37°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.788W * 37°C/W = 114.2°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type
of board (single layer or multi-layer).
Table 6. Thermal Resistance JA for 48 Lead TQFP, Forced Convection
JA by Velocity
Meters per Second
Multi-Layer PCB, JEDEC Standard Test Boards
Rev C 9/4/14
0
1
2.5
37.0°C/W
32.4°C/W
29.0°C/W
18
175MHZ, FEMTOCLOCK® VCXO BASED SONET/SDH JITTER
ATTENUATORS
843002I-40 DATA SHEET
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 8.
VCCO
Q1
VOUT
RL
50Ω
VCCO - 2V
Figure 8. LVPECL Driver Circuit and Termination
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage
of VCCO – 2V.
•
For logic high, VOUT = VOH_MAX = VCCO_MAX – 0.9V
(VCCO_MAX – VOH_MAX) = 0.9V
•
For logic low, VOUT = VOL_MAX = VCCO_MAX – 1.7V
(VCCO_MAX – VOL_MAX) = 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(VOH_MAX – (VCCO_MAX – 2V))/RL] * (VCCO_MAX – VOH_MAX) = [(2V – (VCCO_MAX – VOH_MAX))/RL] * (VCCO_MAX – VOH_MAX) =
[(2V – 0.9V)/50] * 0.9V = 19.8mW
Pd_L = [(VOL_MAX – (VCCO_MAX – 2V))/RL] * (VCCO_MAX – VOL_MAX) = [(2V – (VCCO_MAX – VOL_MAX))/RL] * (VCCO_MAX – VOL_MAX) =
[(2V – 1.7V)/50] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
175MHZ, FEMTOCLOCK® VCXO BASED SONET/SDH JITTER
ATTENUATORS
19
Rev C 9/4/14
843002I-40 DATA SHEET
Reliability Information
Table 7. JA vs. Air Flow Table for a 32 Lead VFQFN
JA vs. Air Flow
Meters per Second
Multi-Layer PCB, JEDEC Standard Test Boards
0
1
2.5
37.0°C/W
32.4°C/W
29.0°C/W
Transistor Count
The transistor count for ICS843002I-40 is: 5536
Rev C 9/4/14
20
175MHZ, FEMTOCLOCK® VCXO BASED SONET/SDH JITTER
ATTENUATORS
843002I-40 DATA SHEET
Package Outline and Package Dimensions
Package Outline - K Suffix for 32-Lead VFQFN
(Ref.)
S eating Plan e
N &N
Even
(N -1)x e
(R ef.)
A1
Ind ex Area
A3
N
To p View
Anvil
Anvil
Singulation
Singula tion
or
OR
Sawn
Singulation
L
N
e (Ty p.)
2 If N & N
1
are Even
2
E2
(N -1)x e
(Re f.)
E2
2
b
A
(Ref.)
D
Chamfer 4x
0.6 x 0.6 max
OPTIONAL
e
N &N
Odd
0. 08
C
D2
2
Th er mal
Ba se
D2
C
NOTE: The following package mechanical drawing is a generic drawing that applies to any pin count VFQFN package. This drawing is not
intended to convey the actual pin count or pin layout of this device. The pin count and pinout are shown on the front page. The package
dimensions are in Table 8 below.
Table 8. Package Dimensions
JEDEC Variation: VHHD-2/-4
All Dimensions in Millimeters
Symbol
Minimum
Nominal
Maximum
N
32
A
0.80
1.00
A1
0
0.05
A3
0.25 Ref.
b
0.18
0.25
0.30
8
ND & NE
D&E
5.00 Basic
D2 & E2
3.0
3.3
e
0.50 Basic
L
0.30
0.40
0.50
Reference Document: JEDEC Publication 95, MO-220
175MHZ, FEMTOCLOCK® VCXO BASED SONET/SDH JITTER
ATTENUATORS
21
Rev C 9/4/14
843002I-40 DATA SHEET
Ordering Information
Table 9. Ordering Information
Part/Order Number
843002AKI-40LF
843002AKI-40LFT
Marking
ICS002AI40L
ICS002AI40L
Package
“Lead-Free” 32 Lead VFQFN
“Lead-Free” 32 Lead VFQFN
Shipping Packaging
Tray
2500 Tape & Reel
Temperature
-40C to 85C
-40C to 85C
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
175MHZ, FEMTOCLOCK® VCXO BASED SONET/SDH JITTER
ATTENUATORS
22
Rev C 9/4/14
843002I-40 DATA SHEET
Revision History Sheet
Rev
Table
Page
A
T4B
6
LVCMOS DC Characteristics Table - added conditions to VOH and VOL.
1/22/09
B
T5
7
AC Characteristics Table - changed output skew from 50ps max. to 150ps max.
4/27/09
C
T9
22
Remove leaded parts from orderables table
11/13/12
1
General Description - Removed Loopbanwidth
Updated datasheet format
C
Description of Change
175MHZ, FEMTOCLOCK® VCXO BASED SONET/SDH JITTER
ATTENUATORS
Date
23
9/4/14
Rev C 9/4/14
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