8705BYT

ICS8705 ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR GENERAL DESCRIPTION The ICS8705 is a highly versatile 1:8 Differential-toLVCMOS/LVTTL Clock Generator. The ICS8705 has two selectable clock inputs. The CLK1, nCLK1 pair can accept most standard differential input levels. The single ended CLK0 input accepts LVCMOS or LVTTL input levels.The ICS8705 has a fully integrated PLL and can be configured as zero delay buffer, multiplier or divider and has an input and output frequency range of 15.625MHz to 250MHz. The reference divider, feedback divider and output divider are each programmable, thereby allowing for the following output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8. The external feedback allows the device to achieve “zero delay” between the input clock and the output clocks. The PLL_SEL pin can be used to bypass the PLL for system test and debug purposes. In bypass mode, the reference clock is routed around the PLL and into the internal output dividers. FEATURES • 8 LVCMOS/LVTTL outputs, 7Ω typical output impedance • Selectable CLK1, nCLK1 or LVCMOS/LVTTL clock inputs • CLK1, nCLK1 pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL • CLK0 input accepts LVCMOS or LVTTL input levels • Output frequency range: 15.625MHz to 250MHz • Input frequency range: 15.625MHz to 250MHz • VCO range: 250MHz to 500MHz • External feedback for “zero delay” clock regeneration with configurable frequencies • Programmable dividers allow for the following output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8 • Fully integrated PLL • Cycle-to-cycle jitter: 45ps (maximum) • Output skew: CLK0, 65ps (maximum) CLK1, nCLK1, 55ps (maximum) • Static Phase Offset: 25 ±125ps (maximum), CLK0 • Full 3.3V or 2.5V operating supply • 0°C to 70°C ambient operating temperature • Lead-Free package fully RoHS compliant BLOCK DIAGRAM PLL_SEL Q0 ÷2, ÷4, ÷8, ÷16, ÷32, ÷64, ÷128 CLK0 CLK1 nCLK1 CLK_SEL FB_IN 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8 0 1 1 PLL Q2 0 PIN ASSIGNMENT PLL_SEL SEL3 VDDO GND VDDA VDD Q7 Q6 Q1 32 31 30 29 28 27 26 25 SEL0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 24 23 22 VDDO Q5 GND Q4 VDDO Q3 GND Q2 Q3 Q4 Q5 Q6 Q7 SEL1 CLK0 nc CLK1 nCLK1 CLK_SEL MR ICS8705 21 20 19 18 17 SEL0 VDD FB_IN SEL2 VDDO Q0 GND Q1 VDDO SEL1 SEL2 SEL3 MR 8705BY 32-Lead LQFP 7mm x 7mm x 1.4 mm Y Package Top View www.idt.com 1 REV. H JULY 2, 2010 ICS8705 ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR TABLE 1. PIN DESCRIPTIONS Number 1, 2, 11 3 4 5 6 7 Name SEL0, SEL1, SEL2 CLK0 nc CLK1 nCLK1 CLK_SEL Input Input Input Pullup Type Input Input Description Determines output divider values in Table 3. Pulldown LVCMOS/LVTTL interface levels. Pulldown Clock input. LVCMOS/LVTTL interface levels. No connect. Pulldown Non-inver ting differential clock input. Inver ting differential clock input. Clock select input. When HIGH, selects differential CLK1, nCLK1. Pulldown When LOW, selects LVCMOS CLK0. LVCMOS/LVTTL interface levels. Active HIGH Master Reset. When logic HIGH, the internal dividers are Pulldown reset causing the outputs to go low. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. Core supply pins. LVCMOS/LVTTL feedback input to phase detector for regenerating Pulldown clocks with "zero delay". Connect to one of the outputs. LVCMOS/LVTTL interface levels. Output supply pins. Clock output. 7Ω typical output impedance. LVCMOS/LVTTL interface levels. 8 9, 32 10 12, 16, 20, 24, 28 13, 15, 17, 19, 21, 23, 25, 27 14, 18, 22, 26 MR VDD FB_IN VDDO Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7 GND Input Power Input Power Output Power Power supply ground. Determines output divider values in Table 3. 29 SEL3 Input Pulldown LVCMOS/LVTTL interface levels. 30 VDDA Power Analog supply pin. Selects between the PLL and reference clock as input to the dividers. 31 PLL_SEL Input Pullup When LOW, selects the reference clock (PLL Bypass). When HIGH, selects PLL (PLL Enabled). LVCMOS/LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol CIN RPULLUP RPULLDOWN CPD ROUT Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Power Dissipation Capacitance (per output) Output Impedance Test Conditions Minimum Typical 4 51 51 VDD, VDDO, VDDA = 3.465V 23 7 Maximum Units pF KΩ KΩ pF Ω 8705BY www.idt.com 2 REV. H JULY 2, 2010 ICS8705 ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR TABLE 3A. PLL ENABLE FUNCTION TABLE Inputs SEL3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 SEL2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 SEL1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 SEL0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Reference Frequency Range (MHz) 125 - 250 62.5 - 125 31.25 - 62.5 15.625 -31.25 125 - 250 62.5 - 125 31.25 - 62.5 125 - 250 62.5 - 125 125 - 250 62.5 - 125 31.25 - 62.5 15.625 - 31.25 31.25 - 62.5 15.625 - 31.25 15.625 - 31.25 Outputs PLL_SEL = 1 PLL Enable Mode Q0:Q7 ÷1 ÷1 ÷1 ÷1 ÷2 ÷2 ÷2 ÷4 ÷4 ÷8 x2 x2 x2 x4 x4 x8 TABLE 3B. PLL BYPASS FUNCTION TABLE Inputs SEL3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 8705BY SEL2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 SEL1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 www.idt.com 3 SEL0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Outputs PLL_SEL = 0 PLL Bypass Mode Q0:Q7 ÷8 ÷8 ÷8 ÷ 16 ÷ 16 ÷ 16 ÷ 32 ÷ 32 ÷ 64 ÷ 128 ÷4 ÷4 ÷8 ÷2 ÷4 ÷2 REV. H JULY 2, 2010 ICS8705 ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD Inputs, VI Outputs, VO Package Thermal Impedance, θJA Storage Temperature, TSTG 4.6V -0.5V to VDD + 0.5 V -0.5V to VDDO + 0.5V 47.9°C/W (0 lfpm) -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = 0°C TO 70°C Symbol VDD VDDA VDDO IDD IDDA IDDO Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Output Supply Current Test Conditions Minimum 3.135 3.135 3.135 Typical 3.3 3.3 3.3 Maximum 3.465 3.465 3.465 96 15 20 Units V V V mA mA mA TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = 0°C TO 70°C Symbol VIH Parameter Input High Voltage PLL_SEL, CLK_SEL, SEL0, SEL1, SEL2, SEL3, FB_IN, MR CLK0 PLL_SEL, CLK_SEL, SEL0, SEL1, SEL2, SEL3, FB_IN, MR CLK0 CLK0, CLK_SEL MR, FB_IN, SEL0, SEL1, SEL2, SEL3 PLL_SEL CLK0, CLK_SEL MR, FB_IN, SEL0, SEL1, SEL2, SEL3 PLL_SEL Test Conditions Minimum Typical 2 2 -0.3 -0.3 VDD = VIN = 3.465V VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V VDD = 3.465V, VIN = 0V -5 -150 2.6 0.5 Maximum VDD + 0.3 VDD + 0.3 0.8 1.3 150 5 Units V V V V µA µA µA µA V V VIL Input Low Voltage IIH Input High Current IIL VOH Input Low Current Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 VOL NOTE 1: Outputs terminated with 50Ω to VDDO/2. In the Parameter Measurement Information Section, see "3.3V Output Load Test Circuit". 8705BY www.idt.com 4 REV. H JULY 2, 2010 ICS8705 ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter IIH IIL VPP Input High Current Input Low Current CLK1 nCLK1 CLK1 nCLK1 Test Conditions VDD = VIN = 3.465V VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V VDD = 3.465V, VIN = 0V -5 -150 1.3 VDD - 0.85 Minimum Typical Maximum 150 5 Units µA µA µA µA V V Peak-to-Peak Input Voltage 0.15 Common Mode Input Voltage; GND + 0.5 VCMR NOTE 1, 2 NOTE 1: Common mode voltage is defined as VIH. NOTE 2: For single ended applications, the maximum input voltage for CLK1, nCLK1 is VDD + 0.3V. TABLE 5A. AC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = 0°C TO 70°C Symbol fMAX tpLH Parameter Output Frequency Propagation Delay, Low-to-High; NOTE 1 CLK0 CLK1, nCLK1 CLK0 PLL_SEL = 0V, f ≤ 250MHz, Qx ÷ 2 PLL_SEL = 0V, f ≤ 250MHz, Qx ÷ 2 PLL_SEL = 3.3V, fREF ≤ 200MHz, Qx ÷ 1 PLL_SEL = 3.3V, fREF ≤ 167MHz, Qx ÷ 1 PLL_SEL = 3.3V, fREF = 200MHz, Qx ÷ 1 PLL_SEL = 3.3V, fREF = 66MHz, Qx * 2 PLL_SEL = 3.3V, fREF = 66MHz, Qx * 2 PLL_SEL = 0V PLL_SEL = 0V fOUT > 40MHz 400 Test Conditions Minimum 15.625 5 5 -100 -15 -50 -150 0 25 + 135 +100 -25 150 Typical Maximum 250 7 7.3 150 285 250 100 300 65 55 45 1 950 Units MHz ns ns ps ps ps ps ps ps ps ps mS ps % % t(Ø) Static Phase Offset; NOTE 2, 4 CLK1, nCLK1 CLK0 CLK1, nCLK1 tsk(o) tjit(cc) tL tR / tF odc Output Skew; NOTE 3, 4 PLL Lock Time Output Rise/Fall Time Output Duty Cycle CLK0 CLK1, nCLK1 Cycle-to-Cycle Jitter; NOTE 4 43 57 PLL x 4 mode, fin = 45MHz, 47 53 fOUT = 180MHz All parameters measured at fMAX unless noted otherwise. NOTE 1: Measured from the differential input crossing point to the output at VDDO/2. NOTE 2: Defined as the time difference between the input reference clock and the average feedback input signal when the PLL is locked and the input reference frequency is stable. NOTE 3: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at VDDO/2. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. 8705BY www.idt.com 5 REV. H JULY 2, 2010 ICS8705 ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR TABLE 4D. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDO = 2.5V±5%, TA = 0°C TO 70°C Symbol VDD VDDA VDDO IDD IDDA IDDO Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Output Supply Current Test Conditions Minimum 2.375 2.375 2.375 Typical 2.5 2.5 2.5 Maximum 2.625 2.625 2.625 90 15 20 Units V V V mA mA mA TABLE 4E. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = VDDA = VDDO = 2.5V±5%, TA = 0°C TO 70°C Symbol VIH Parameter Input High Voltage PLL_SEL, CLK_SEL, SEL0, SEL1, SEL2, SEL3, FB_IN, MR CLK0 PLL_SEL, CLK_SEL, SEL0, SEL1, SEL2, SEL3, FB_IN, MR CLK0 CLK0, CLK_SEL MR, FB_IN, SEL0, SEL1, SEL2, SEL3 PLL_SEL CLK0, CLK_SEL MR, FB_IN, SEL0, SEL1, SEL2, SEL3 PLL_SEL Test Conditions Minimum Typical 2 2 -0.3 -0.3 VDD = VIN = 2.625V VDD = VIN = 2.625V VDD = 2.625V, VIN = 0V VDD = 2.625V, VIN = 0V -5 -150 1.8 0.5 Maximum VDD + 0.3 VDD + 0.3 0.8 1.3 150 5 Units V V V V µA µA µA µA V V VIL Input Low Voltage IIH Input High Current IIL VOH Input Low Current Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 VOL NOTE 1: Outputs terminated with 50Ω to VDDO/2. In the Parameter Measurement Information section, see "2.5V Output Load Test Circuit" figure. TABLE 4F. DIFFERENTIAL DC CHARACTERISTICS, VDD = VDDA = VDDO = 2.5V±5%, TA = 0°C TO 70°C Symbol IIH IIL VPP Parameter Input High Current Input Low Current CLK1 nCLK1 CLK1 nCLK1 Test Conditions VDD = VIN = 2.625V VDD = VIN = 2.625V VDD = 2.625V, VIN = 0V VDD = 2.625V, VIN = 0V -5 -150 1.3 VDD - 0.85 Minimum Typical Maximum 150 5 Units µA µA µA µA V V Peak-to-Peak Input Voltage 0.15 Common Mode Input Voltage; GND + 0.5 VCMR NOTE 1, 2 NOTE 1: Common mode voltage is defined as VIH. NOTE 2: For single ended applications, the maximum input voltage for CLK1, nCLK1 is VDD + 0.3V. 8705BY www.idt.com 6 REV. H JULY 2, 2010 ICS8705 ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR TABLE 5B. AC CHARACTERISTICS, VDD = VDDA = VDDO = 2.5V±5%, TA = 0°C TO 70°C Symbol fMAX tpLH Parameter Output Frequency Propagation Delay, Low-to-High; NOTE 1 CLK0 CLK1, nCLK1 CLK0 PLL_SEL = 0V, f ≤ 250MHz, Qx ÷ 2 PLL_SEL = 0V, f ≤ 250MHz, Qx ÷ 2 PLL_SEL = 2.5V, fREF ≤ 200MHz, Qx ÷ 1 PLL_SEL = 2.5V, fREF = 133MHz, Qx ÷ 1 PLL_SEL = 2.5V, fREF = 200MHz, Qx ÷ 1 PLL_SEL = 2.5V, fREF = 66MHz, Qx * 2 PLL_SEL = 2.5V, fREF = 66MHz, Qx * 2 PLL_SEL = 0V PLL_SEL = 0V fOUT > 40MHz PLL_SEL = 2.5V, fREF = 66MHz, Qx * 2 400 Test Conditions Minimum 15.625 5 5 -250 -50 -100 -150 0 25 100 +100 -25 150 Typical Maximum 250 7 7.3 200 250 300 100 300 65 55 45 ±50 1 950 Units MHz ns ns ps ps ps ps ps ps ps ps ps mS ps % % t(Ø) Static Phase Offset; NOTE 2, 4 CLK1, nCLK1 CLK0 CLK1, nCLK1 tsk(o) tjit(cc) t jit(θ) tL tR / tF odc Output Skew; NOTE 3, 4 CLK0 CLK1, nCLK1 Cycle-to-Cycle Jitter; NOTE 4 Phase Jitter; NOTE 4, 5 PLL Lock Time Output Rise/Fall Time Output Duty Cycle 43 57 PLL x 4 mode, fin = 45MHz, 45 55 fOUT = 180MHz All parameters measured at fMAX unless noted otherwise. NOTE 1: Measured from the differential input crossing point to the output at VDDO/2. NOTE 2: Defined as the time difference between the input reference clock and the average feedback input signal when the PLL is locked and the input reference frequency is stable. NOTE 3: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at VDDO/2. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. NOTE 5: Phase jitter is dependent on the input source used. 8705BY www.idt.com 7 REV. H JULY 2, 2010 ICS8705 ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR PARAMETER MEASUREMENT INFORMATION 1.65V±5% 1.25V±5% VDD, VDDA, VDDO SCOPE Qx VDD, VDDA, VDDO SCOPE Qx LVCMOS GND LVCMOS GND -1.165V±5% -1.25V±5% 3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT 2.5V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT V DD V DDO nCLK V PP Qx Cross Points V CMR 2 CLK Qy GND V DDO 2 t sk(o) DIFFERENTIAL INPUT LEVEL OUTPUT SKEW V DDO V DDO V DDO 80% 20% tR 80% 20% tF Q0:Q7 ➤ 8705BY 2 2 2 tcycle n ➤ t jit(cc) = tcycle n –tcycle n+1 1000 Cycles CYCLE-TO-CYCLE JITTER ➤ tcycle n+1 ➤ Clock Outputs OUTPUT RISE/FALL TIME www.idt.com 8 REV. H JULY 2, 2010 ICS8705 ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR nCLK1 CLK1 VOH VOL VOH VDDO CLK0 nCLK1 CLK1 VDD 2 FB_IN ➤ t (Ø) ➤ VOL 2 t jit(Ø) = t (Ø) — t (Ø) mean = Phase Jitter t (Ø) mean = Static Phase Offset (where t (Ø) is any random sample, and t (Ø) mean is the average of the sampled cycles measured on controlled edges) Q0:Q7 VDDO 2 ➤ t PD ➤ PHASE JITTER & STATIC PHASE OFFSET PROPAGATION DELAY VDDO VDDO 2 t PW t PERIOD VDDO 2 Q0:Q7 2 odc = t PW t PERIOD OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD 8705BY www.idt.com 9 REV. H JULY 2, 2010 ICS8705 ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR APPLICATION INFORMATION POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS8705 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDA, and VDDO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10 Ω r esistor along with a 10µF and a .01 μ F bypass capacitor should be connected to each VDDA. 3.3V VDD .01μF VDDA .01 μF 10 μF 10 Ω FIGURE 1. POWER SUPPLY FILTERING WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VCC/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. VDD R1 1K Single Ended Clock Input CLK V_REF nCLK C1 0.1u R2 1K FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT 8705BY www.idt.com 10 REV. H JULY 2, 2010 ICS8705 ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR DIFFERENTIAL CLOCK INPUT INTERFACE The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 3A to 3D show interface examples for the CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 4A, the input termination applies for LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. 3.3V 3.3V 3.3V 1.8V Zo = 50 Ohm Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R2 50 R3 50 LVPECL Zo = 50 Ohm CLK nCLK HiPerClockS Input HiPerClockS Input R1 50 R2 50 FIGURE 3A. CLK/NCLK INPUT DRIVEN BY LVHSTL DRIVER FIGURE 3B. CLK/NCLK INPUT DRIVEN BY 3.3V LVPECL DRIVER 3.3V 3.3V 3.3V R3 125 Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVPECL R1 84 R2 84 HiPerClockS Input R4 125 3.3V 3.3V LVDS_Driv er R1 100 Zo = 50 Ohm Zo = 50 Ohm CLK nCLK Receiv er FIGURE 3C. CLK/NCLK INPUT DRIVEN BY 3.3V LVPECL DRIVER FIGURE 3D. CLK/NCLK INPUT DRIVEN BY 3.3V LVDS DRIVER 8705BY www.idt.com 11 REV. H JULY 2, 2010 ICS8705 ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR LAYOUT GUIDELINE The schematic of the ICS8705 layout example is shown in Figure 4A. The ICS8705 recommended PCB board layout for this example is shown in Figure 4B. This layout example is used as a general guideline. The layout in the actual system will depend on the selected component types, the density of the components, the density of the traces, and the stack up of the P.C. board. VDD R7 10 - 15 VDDA PLL_SEL SEL3 R1 43 Zo = 50 VDD C16 10u VDD U1 C11 0.01u 32 31 30 29 28 27 26 25 VDD PLL_SEL VDDA SEL3 VDDO Q7 GND Q6 Ro ~ 7 Ohm Zo = 50 SEL0 SEL1 R4 Driv er_LVCMOS 43 1 2 3 4 5 6 7 8 SEL0 SEL1 CLK0 nc CLK1 nCLK1 CLK_SEL MR VDDO Q5 GND Q4 VDDO Q3 GND Q2 24 23 22 21 20 19 18 17 R5 1K R4 1K ICS8705 Logic Input Pin Examples SEL2 VDD Set Logic Input to '1' RU1 1K VDD Set Logic Input to '0' RU2 Not Install 9 10 11 12 13 14 15 16 VDD=3.3V or 2.5V VDD FB_IN SEL2 VDDO Q0 GND Q1 VDDO Zo = 50 R2 43 To Logic Input pins RD1 Not Install RD2 1K To Logic Input pins (U1-9) VDD (U1-12) (U1-16) (U1-20) (U1-24) (U1-28) (U1-32) C2 0.1uF C3 0.1uF C4 0.1uF C5 0.1uF C6 0.1uF C1 0.1uF C7 0.1uF FIGURE 4A. ICS8705 LVCMOS CLOCK GENERATOR SCHEMATIC EXAMPLE 8705BY www.idt.com 12 REV. H JULY 2, 2010 ICS8705 ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR The following component footprints are used in this layout example: All the resistors and capacitors are size 0603. POWER AND GROUNDING Place the decoupling capacitors as close as possible to the power pins. If space allows, placement of the decoupling capacitor on the component side is preferred. This can reduce unwanted inductance between the decoupling capacitor and the power pin caused by the via. Maximize the power and ground pad sizes and number of vias capacitors. This can reduce the inductance between the power and ground planes and the component power and ground pins. The RC filter consisting of R7, C11, and C16 should be placed as close to the VDDA pin as possible. CLOCK TRACES AND TERMINATION Poor signal integrity can degrade the system performance or cause system failure. In synchronous high-speed digital systems, the clock signal is less tolerant to poor signal integrity than other signals. Any ringing on the rising or falling edge or excessive ring back can cause system failure. The shape of the trace and the trace delay might be restricted by the available space on the board and the component location. While routing the traces, the clock signal traces should be routed first and should be locked prior to routing other signal traces. • The differential 50Ω output traces should have same length. • Avoid sharp angles on the clock trace. Sharp angle turns cause the characteristic impedance to change on the transmission lines. • Keep the clock traces on the same layer. Whenever possible, avoid placing vias on the clock traces. Placement of vias on the traces can affect the trace characteristic impedance and hence degrade signal integrity. • To prevent cross talk, avoid routing other signal traces in parallel with the clock traces. If running parallel traces is unavoidable, allow a separation of at least three trace widths between the differential clock trace and the other signal trace. • Make sure no other signal traces are routed between the clock trace pair. • The series termination resistors should be located as close to the driver pins as possible. GND 50 Ohm Trace R7 C16 C11 C1 VDD VIA Other signals VDDA C7 R1 Pin 1 C6 C5 U1 C4 C2 C3 R2 50 Ohm Trace FIGURE 4B. PCB BOARD LAYOUT FOR ICS8705 8705BY www.idt.com 13 REV. H JULY 2, 2010 ICS8705 ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR RELIABILITY INFORMATION TABLE 6. θJAVS. AIR FLOW TABLE FOR 32 LEAD LQFP θJA by Velocity (Linear Feet per Minute) 0 Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8°C/W 47.9°C/W 200 55.9°C/W 42.1°C/W 500 50.1°C/W 39.4°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS8705 is: 3126 8705BY www.idt.com 14 REV. H JULY 2, 2010 ICS8705 ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR PACKAGE OUTLINE - Y SUFFIX FOR 32 LEAD LQFP TABLE 7. PACKAGE DIMENSIONS JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS BBA SYMBOL N A A1 A2 b c D D1 D2 E E1 E2 e L θ ccc 0.45 0° --0.05 1.35 0.30 0.09 MINIMUM NOMINAL 32 --1.40 0.37 -9.00 BASIC 7.00 BASIC 5.60 Ref. 9.00 BASIC 7.00 BASIC 5.60 Ref. 0.80 BASIC 0.60 --0.75 7° 0.10 1.60 0.15 1.45 0.45 0.20 MAXIMUM Reference Document: JEDEC Publication 95, MS-026 8705BY www.idt.com 15 REV. H JULY 2, 2010 ICS8705 ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR TABLE 8. ORDERING INFORMATION Part/Order Number 8705BY 8705BYT 8705BYLF 8705BYLFT Marking ICS8705BY ICS8705BY ICS8705BYLF ICS8705BYLF Package 32 Lead LQFP 32 Lead LQFP 32 Lead "Lead Free" LQFP 32 Lead "Lead Free" LQFP Shipping Packaging tray 1000 tape & reel 250 per tray 1000 Temperature 0°C to 70°C 0°C to 70°C 0°C to 70°C 0°C to 70°C NOTE: Par ts that are ordered with an “LF” suffix to the par t number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Inc. (IDT) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. 8705BY www.idt.com 16 REV. H JULY 2, 2010 ICS8705 ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR REVISION HISTORY SHEET Rev A T3A B T5A T4D:T4F; T5B T3A T5A C T5B C C C C T1 T2 T1 T1 T1, T4A, T4D D T5A, T5B 7 2 2 2 2 8 2, 4, 6 5, 7 Table Page 1 3 5 6, 7 3 5 Description of Change Updated Block Diagram PLL Enable Function Table - revised the Reference Frequency Range column 3.3V AC Characteristics Table - updated the Output Frequency row from 350MHz Max. to 275MHz Max. Added 2.5V tables. PLL Enable Function Table - revised the Reference Frequency Range column 3.3V AC Characteristics Table - updated the Output Frequency row from 275MHz Max. to 250MHz Max. 2.5V AC Characteristics Table - updated the Output Frequency row from 275MHz Max. to 250MHz Max. Pin Description Table - revised power pin descriptions. Pin Characteristics Table - add 23pF (typical) in CPD row. Pin Description Table - Pin# 10 from description, replaced "Connect to pin 10." with "Connect to one of the outputs." Revised CLK0 description and MR description. Revised Output Rise/Fall Time Diagram. Revised description for VDD to read Core supply from Positive supply. AC Characteristics, added another row to "odc" with different test conditions and values. Updated format. Pin Description table - revised MR description. AC tables - Changed the Static Phase Offset limits for CLK1, nCLK1. AC tables - added Static Phase Offset with "fREF = 66MHz, Qx * 2". 3.3V AC table - corrected typo in SPO parameter to read NOTE 4 from NOTE 7. Throughout datasheet revised title to read "...Differential-to-LVCMOS/LVTTL..." 2.5V AC Characteristics Table - added Phase Jitter spec, and Note 5. Replaced Static Phase Offset Diagram with Phase Jitter & SPO Diagram. Pin Characteristics Table - changed CIN from 4pF max. to 4pF typical. 4/4/02 Date 1/25/02 3/14/02 4/10/02 7/15/02 8/1/02 8/21/02 11/22/02 E 1 T5A & T5B T5A & T5B 2 5&7 5&7 1/22/03 F T5B T2 7 9 2 2/13/03 G G G G G H 3/14/03 5/15/03 6/6/03 6/16/04 3/18/05 7/2/10 11 Added Differential Clock Input Interface section. 12 & 13 Added Layout Guideline T6 T8 T8 14 1 16 16 18 Ordering Information Table - added "Lead-Free" par t number Features Section - added temperature bullet. Ordering Information Table - Added "Lead-Free" note. Updated datasheet's header/footer with IDT from ICS. Removed "ICS" prefix from Par t/Order Number column. Added Contact Page. 8705BY www.idt.com 17 REV. H JULY 2, 2010 ICS8705 ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR We’ve Got Your Timing Solution. 6024 Silver Creek Valley Road San Jose, CA 95138 Sales 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 Tech Support netcom@idt.com © 2010 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA 8705BY www.idt.com 18 REV. H JULY 2, 2010