932S208YFLNT

DATASHEET Programmable Timing Control HubTM for Next Gen P4TM Processor Recommended Application: CK409B clock, Intel Yellow Cover part, Server Applications Output Features: • 4 - 0.7V current-mode differential CPU pairs • 1 - 0.7V current-mode differential SRC pair • 7 - PCI (33MHz) • 3 - PCICLK_F, (33MHz) free-running • 1 - USB, 48MHz • 1 - DOT, 48MHz • 2 - REF, 14.318MHz • 4 - 3V66, 66.66MHz • 1 - VCH/3V66, selectable 48MHz or 66MHz Key Specifications: • CPU/SRC outputs cycle-cycle jitter < 125ps • 3V66 outputs cycle-cycle jitter < 250ps • PCI outputs cycle-cycle jitter < 250ps • CPU outputs skew: < 100ps • +/- 300ppm frequency accuracy on CPU & SRC clocks Functionality CPU B6b5 FS_A FS_B MHz 0 0 100 0 MID Ref/N0 0 1 200 0 1 0 133 1 1 166 1 MID Hi-Z 0 0 200 0 1 400 1 1 0 266 1 1 333 SRC MHz 100/200 Ref/N1 100/200 100/200 100/200 Hi-Z 100/200 100/200 100/200 100/200 3V66 MHz 66.66 Ref/N2 66.66 66.66 66.66 Hi-Z 66.66 66.66 66.66 66.66 PCI MHz 33.33 Ref/N3 33.33 33.33 33.33 Hi-Z 33.33 33.33 33.33 33.33 REF USB/DOT MHz MHz 14.318 48.00 Ref/N4 Ref/N5 14.318 48.00 14.318 48.00 14.318 48.00 Hi-Z Hi-Z 14.318 48.00 14.318 48.00 14.318 48.00 14.318 48.00 ICS932S208 Features/Benefits: • Supports tight ppm accuracy clocks for Serial-ATA • Supports spread spectrum modulation, 0 to -0.5% down spread and +/- 0.25% center spread • • Supports CPU clks up to 400MHz in test mode Uses external 14.318MHz crystal Pin Configuration REF0 REF1 VDDREF X1 X2 GND PCICLK_F0 PCICLK_F1 PCICLK_F2 VDDPCI GND PCICLK0 PCICLK1 PCICLK2 PCICLK3 VDDPCI GND PCICLK4 PCICLK5 PCICLK6 PD# 3V66_0 3V66_1 VDD3V66 GND 3V66_2 3V66_3 SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 FS_B VDDA GNDA GND IREF FS_A CPUCLKT3 CPUCLKC3 VDDCPU CPUCLKT2 CPUCLKC2 GND CPUCLKT1 CPUCLKC1 VDDCPU CPUCLKT0 CPUCLKC0 GND SRCCLKT SRCCLKC VDD Vtt_PWRGD# VDD48 GND 48MHz_DOT 48MHz_USB SDATA 3V66_4/VCH 56-pin SSOP & TSSOP IDTTM Programmable Timing Control HubTM for Next Gen P4TM Processor ICS932S208 0743G—01/26/10 1 ICS932S208 Programmable Timing Control HubTM for Next Gen P4TM Processor Pin Description PIN # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 PIN NAME REF0 REF1 VDDREF X1 X2 GND PCICLK_F0 PCICLK_F1 PCICLK_F2 VDDPCI GND PCICLK0 PCICLK1 PCICLK2 PCICLK3 VDDPCI GND PCICLK4 PCICLK5 PCICLK6 PD# 3V66_0 3V66_1 VDD3V66 GND 3V66_2 3V66_3 SCLK PIN TYPE OUT OUT PWR IN OUT PWR OUT OUT OUT PWR PWR OUT OUT OUT OUT PWR PWR OUT OUT OUT IN OUT OUT PWR PWR OUT OUT IN DESCRIPTION 14.318 MHz reference clock. 14.318 MHz reference clock. Ref, XTAL power supply, nominal 3.3V Crystal input, Nominally 14.318MHz. Crystal output, Nominally 14.318MHz Ground pin. Free running PCI clock not affected by PCI_STOP# . Free running PCI clock not affected by PCI_STOP# . Free running PCI clock not affected by PCI_STOP# . Power supply for PCI clocks, nominal 3.3V Ground pin. PCI clock output. PCI clock output. PCI clock output. PCI clock output. Power supply for PCI clocks, nominal 3.3V Ground pin. PCI clock output. PCI clock output. PCI clock output. Asynchronous active low input pin used to power down the device into a low power state. The internal clocks are disabled and the VCO and the crystal are stopped. The latency of the power down will not be greater than 1.8ms. Internal pull-up of 150K nominal. 3.3V 66.66MHz clock output 3.3V 66.66MHz clock output Power pin for the 3V66 clocks. Ground pin. 3.3V 66.66MHz clock output 3.3V 66.66MHz clock output Clock pin of I2C circuitry 5V tolerant IDTTM Programmable Timing Control HubTM for Next Gen P4TM Processor 0743G—01/26/10 2 ICS932S208 Programmable Timing Control HubTM for Next Gen P4TM Processor Pin Description (continued) PIN # 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 PIN NAME 3V66_4/VCH SDATA 48MHz_USB 48MHz_DOT GND VDD48 Vtt_PWRGD# VDD SRCCLKC SRCCLKT GND CPUCLKC0 CPUCLKT0 VDDCPU CPUCLKC1 CPUCLKT1 GND CPUCLKC2 CPUCLKT2 VDDCPU CPUCLKC3 CPUCLKT3 FS_A IREF GND GNDA VDDA FS_B PIN TYPE OUT I/O OUT OUT PWR PWR IN PWR OUT OUT PWR OUT OUT PWR OUT OUT PWR OUT OUT PWR OUT OUT IN OUT PWR PWR PWR IN DESCRIPTION 66.66MHz clock output for AGP support. AGP-PCI should be aligned with a skew window tolerance of 500ps. VCH is 48MHz clock output for video controller hub. Data pin for I2C circuitry 5V tolerant 48MHz clock output. 48MHz clock output. Ground pin. Power pin for the 48MHz output.3.3V This 3.3V LVTTL input is a level sensitive strobe used to determine when latch inputs are valid and are ready to be sampled. This is an active low input. Power supply for SRC clocks, nominal 3.3V Complement clock of differential pair for S-ATA support. +/- 300ppm accuracy required. True clock of differential pair for S-ATA support. +/- 300ppm accuracy required. Ground pin. Complimentary clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. True clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. Supply for CPU clocks, 3.3V nominal Complimentary clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. True clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. Ground pin. Complimentary clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. True clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. Supply for CPU clocks, 3.3V nominal Complimentary clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. True clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. Frequency select pin, see Frequency table for functionality This pin establishes the reference current for the differential currentmode output pairs. This pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. 475 ohms is the standard value. Ground pin. Ground pin for core. 3.3V power for the PLL core. Frequency select pin, see Frequency table for functionality IDTTM Programmable Timing Control HubTM for Next Gen P4TM Processor 0743G—01/26/10 3 ICS932S208 Programmable Timing Control HubTM for Next Gen P4TM Processor General Description ICS932S208 follows Intel CK409B Yellow Cover specification. This clock synthesizer provides a single chip solution for next generation P4 Intel processors and Intel chipsets. ICS932S208 is driven with a 14.318MHz crystal. It generates CPU outputs up to 200MHz. It also provides a tight ppm accuracy output for Serial ATA support. Block Diagram Frequency Dividers PLL2 48MHz, USB, DOT X1 X2 XTAL REF (1:0) CPUCLKT (3:0) CPUCLKC (3:0) SRCCLKT0 SCLK SDATA Vtt_PWRGD# PD# FS_A FS_B Control Logic Programmable Spread PLL1 Programmable Frequency Dividers STOP Logic SRCCLKC0 3V66(4:0) PCICLK (6:0) PCICLKF (2:0) I REF Power Groups Pin Number VDD GND 3 6 24 25 10,16 11,17 36 39 55 54 34 33 N/A 53 48, 42 45 Description Xtal, Ref 3V66 [0:3] PCICLK outputs SRCCLK outputs Master clock, CPU Analog 48MHz, PLL IREF CPUCLK clocks IDTTM Programmable Timing Control HubTM for Next Gen P4TM Processor 0743G—01/26/10 4 ICS932S208 Programmable Timing Control HubTM for Next Gen P4TM Processor Absolute Maximum Ratings Symbol VDD_A VDD_In Ts Tambient Tcase ESD prot Parameter 3.3V Core Supply Voltage 3.3V Logic Input Supply Voltage Storage Temperature Ambient Operating Temp Case Temperature Input ESD protection human body model Min GND - 0.5 -65 0 Max VDD + 0.5V VDD + 0.5V 150 70 115 Units V V ° C °C °C V 2000 Electrical Characteristics - Input/Supply/Common Output Parameters TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5% PARAMETER Input High Voltage Input MID Voltage Input Low Voltage Input High Current SYMBOL VIH VMID VIL IIH IIL1 Input Low Current IIL2 Operating Supply Current Powerdown Current Input Frequency Pin Inductance1 3 CONDITIONS 3.3 V +/-5% 3.3 V +/-5% 3.3 V +/-5% VIN = VDD VIN = 0 V; Inputs with no pull-up resistors VIN = 0 V; Inputs with pull-up resistors Full Active, CL = Full load; all diff pairs driven all differential pairs tri-stated VDD = 3.3 V MIN 2 1 VSS - 0.3 -5 -5 -200 TYP MAX UNITS NOTES VDD + 0.3 V 1.8 V 0.8 V 5 uA uA uA 350 35 12 mA mA mA MHz nH pF pF pF ms kHz ns us ns ns us ns ns IDD3.3OP IDD3.3PD Fi Lpin CIN COUT CINX 14.31818 7 5 6 5 Logic Inputs Output pin capacitance X1 & X2 pins From VDD Power-Up or deTSTAB 1.8 Clk Stabilization1,2 assertion of PD# to 1st clock Modulation Frequency Triangular Modulation 30 33 SRC output enable after 15 Tdrive_SRC PCI_Stop# de-assertion CPU output enable after Tdrive_PD# 300 PD# de-assertion Tfall_Pd# PD# fall time of 5 Trise_Pd# PD# rise time of 5 CPU output enable after Tdrive_CPU_Stop# 10 CPU_Stop# de-assertion Tfall_CPU_Stop# PD# fall time of 5 Trise_CPU_Stop# PD# rise time of 5 1 Guaranteed by design, not 100% tested in production. 2 See timing diagrams for timing requirements. 3 Input frequency should be measured at the REF output pin and tuned to ideal 14.31818MHz to meet ppm frequency accuracy on PLL outputs. Input Capacitance1 3 1 1 1 1 1,2 1 1 1 1 2 1 1 2 IDTTM Programmable Timing Control HubTM for Next Gen P4TM Processor 0743G—01/26/10 5 ICS932S208 Programmable Timing Control HubTM for Next Gen P4TM Processor Electrical Characteristics - CPU & SRC 0.7V Current Mode Differential Pair TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL =2pF PARAMETER Current Source Output Impedance Output High Voltage Output Low Voltage Voltage High Voltage Low Max Voltage Min Voltage Crossing Voltage (abs) Crossing Voltage (var) Long Accuracy SYMBOL Zo1 VOH3 VOL3 VHigh VLow Vovs Vuds Vcross(abs) d-Vcross ppm CONDITIONS VO = Vx IOH = -1 mA IOL = 1 mA Statistical measurement on single ended signal using oscilloscope math function. Measurement on single ended signal using absolute value. Variation of crossing over all edges see Tperiod min-max values 200MHz nominal 200MHz spread 166.66MHz nominal 166.66MHz spread 133.33MHz nominal 133.33MHz spread 100.00MHz nominal 100.00MHz spread 200MHz nominal 166.66MHz nominal/spread 133.33MHz nominal/spread 100.00MHz nominal/spread VOL = 0.175V, VOH = 0.525V VOH = 0.525V VOL = 0.175V MIN 3000 2.4 0.4 660 -150 -300 250 850 mV 150 1150 550 140 -300 4.9985 4.9985 5.9982 5.9982 7.4978 7.4978 9.9970 9.9970 4.8735 5.8732 7.3728 9.8720 175 175 300 5.0015 5.0266 6.0018 6.0320 7.5023 5.4000 10.0030 10.0533 mV mV mV ppm ns ns ns ns ns ns ns ns ns ns ns ns ps ps ps ps 1 1 1 1 1 1,2 2 2 2 2 2 2 2 2 1,2 1,2 1,2 1,2 1 1 1 1 1 1 1 1 TYP MAX UNITS Ω V NOTES 1 Average period Tperiod Absolute min period Rise Time Fall Time Rise Time Variation Fall Time Variation Duty Cycle Tabsmin tr tf d-tr d-tf dt3 700 700 125 125 Measurement from differential 45 55 % wavefrom VT = 50% tsk3 100 ps Skew Measurement from differential tjcyc-cyc Jitter, Cycle to cycle 125 ps wavefrom 1 Guaranteed by design, not 100% tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that Ref output is at 14.31818MHz SRC clock outputs run at only 100MHz or 200MHz, specs for 133.33 and 166.66 do not apply to SRC clock pair. IDTTM Programmable Timing Control HubTM for Next Gen P4TM Processor 0743G—01/26/10 6 ICS932S208 Programmable Timing Control HubTM for Next Gen P4TM Processor Electrical Characteristics - 3V66 Mode: 3V66 [4:0] TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 10-30 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS ppm see Tperiod min-max values Long Accuracy 66.66MHz output nominal Tperiod Clock period 66.66MHz output spread VOH IOH = -1 mA Output High Voltage IOL = 1 mA VOL Output Low Voltage V OH @ MIN = 1.0 V IOH Output High Current VOH @ MAX = 3.135 V VOL @ MIN = 1.95 V IOL Output Low Current VOL @ MAX = 0.4 V Edge Rate Rising edge rate Falling edge rate Edge Rate tr1 VOL = 0.4 V, VOH = 2.4 V Rise Time VOH = 2.4 V, VOL = 0.4 V tf1 Fall Time dt1 VT = 1.5 V Duty Cycle Skew Jitter 1 MIN -300 14.9955 14.9955 2.4 -33 TYP MAX 300 15.0045 15.0799 0.55 -33 30 1 1 0.5 0.5 45 38 4 4 2 2 55 250 250 UNITS ppm ns ns V V mA mA mA mA V/ns V/ns ns ns % ps ps Notes 1,2 2 2 1 1 1 1 1 1 1 tsk1 tjcyc-cyc VT = 1.5 V VT = 1.5 V 3V66 Guaranteed by design, not 100% tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that Ref output is at 14.31818MHz Electrical Characteristics - PCICLK/PCICLK_F TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 10-30 pF (unless otherwise specified) PARAMETER Long Accuracy Clock period Output High Voltage Output Low Voltage Output High Current Output Low Current Edge Rate Edge Rate Rise Time Fall Time Duty Cycle Skew Jitter 1 2 SYMBOL ppm Tperiod VOH VOL IOH IOL CONDITIONS see Tperiod min-max values 33.33MHz output nominal 33.33MHz output spread IOH = -1 mA IOL = 1 mA V OH @MIN = 1.0 V VOH@ MAX = 3.135 V VOL @ MIN = 1.95 V VOL @ MAX = 0.4 V Rising edge rate Falling edge rate VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V 3V66 MIN -300 29.9910 29.9910 2.4 -33 TYP MAX 300 30.0090 30.1598 0.55 -33 UNITS ppm ns ns V V mA mA mA mA V/ns V/ns ns ns % ps ps Notes 1,2 2 2 30 1 1 0.5 0.5 45 38 4 4 2 2 55 500 250 tr1 tf1 dt1 tsk1 tjcyc-cyc 1 1 1 1 1 1 1 Guaranteed by design, not 100% tested in production. All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that Ref output is at 14.31818MHz IDTTM Programmable Timing Control HubTM for Next Gen P4TM Processor 0743G—01/26/10 7 ICS932S208 Programmable Timing Control HubTM for Next Gen P4TM Processor Electrical Characteristics - 48MHz DOT Clock TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 5-10 pF (unless otherwise specified) PARAMETER Long Accuracy Clock period Output High Voltage Output Low Voltage Output High Current Output Low Current Edge Rate Edge Rate Rise Time Fall Time Duty Cycle tr1 tf1 dt1 SYMBOL ppm Tperiod VOH VOL IOH IOL CONDITIONS MIN TYP MAX 200 20.8340 0.55 -33 38 4 4 1 1 UNITS ppm ns V V mA mA mA mA V/ns V/ns ns ns Notes 1,2 2 see Tperiod min-max -200 values 66.66MHz output nominal 20.8257 IOH = -1 mA 2.4 IOL = 1 mA V OH @ MIN = 1.0 V -33 VOH @ MAX = 3.135 V VOL @ MIN = 1.95 V 30 VOL @ MAX = 0.4 V Rising edge rate 2 Falling edge rate 2 VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V 0.5 0.5 1 1 1 1 1 1 VT = 1.5 V 45 55 % 125us period jitter 2 ns Long Term Jitter (8kHz frequency modulation amplitude) 1 Guaranteed by design, not 100% tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that Ref output is at 14.31818MHz IDTTM Programmable Timing Control HubTM for Next Gen P4TM Processor 0743G—01/26/10 8 ICS932S208 Programmable Timing Control HubTM for Next Gen P4TM Processor Electrical Characteristics - VCH, 48MHz, USB TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER Long Accuracy Clock period Output High Voltage Output Low Voltage SYMBOL ppm Tperiod VOH VOL CONDITIONS MIN TYP MAX UNITS Notes 1,2 2 see Tperiod min-max values -200 200 ppm 66.66MHz output nominal 20.8257 20.8340 ns IOH = -1 mA 2.4 V IOL = 1 mA 0.55 V V OH @ MIN = 1.0 V -33 mA IOH Output High Current VOH@ MAX = 3.135 V -33 mA VOL @MIN = 1.95 V 30 mA IOL Output Low Current VOL @ MAX = 0.4 V 38 mA Rising edge rate 1 2 V/ns Edge Rate Edge Rate Falling edge rate 1 2 V/ns tr1 VOL = 0.4 V, VOH = 2.4 V Rise Time 1 2 ns VOH = 2.4 V, VOL = 0.4 V tf1 1 2 ns Fall Time VT = 1.5 V dt1 45 55 % Duty Cycle 125us period jitter 6 ns Long Term Jitter (8kHz frequency modulation amplitude) 1 Guaranteed by design, not 100% tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that Ref output is at 14.31818MHz 1 1 1 1 1 1 IDTTM Programmable Timing Control HubTM for Next Gen P4TM Processor 0743G—01/26/10 9 ICS932S208 Programmable Timing Control HubTM for Next Gen P4TM Processor Electrical Characteristics - REF-14.318MHz TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER Long Accuracy Clock period Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Skew Duty Cycle Jitter 1 SYMBOL ppm Tperiod VOH 1 VOL IOH IOL 1 1 1 CONDITIONS MIN TYP MAX 300 69.8550 0.4 -23 27 2 2 500 55 1000 UNITS ppm ns V V mA mA ns ns ps % ps 1 tr1 1 tf1 1 tsk1 1 dt1 tjcyc-cyc 1 1 see Tperiod min-max values -300 14.318MHz output nominal 69.8270 IOH = -1 mA 2.4 IOL = 1 mA V OH @MIN = 1.0 V, V -29 OH@MAX = 3.135 V VOL @MIN = 1.95 V, VOL 29 @MAX = 0.4 V VOL = 0.4 V, VOH = 2.4 V 1 VOH = 2.4 V, VOL = 0.4 V 1 VT = 1.5 V VT = 1.5 V 45 VT = 1.5 V Guaranteed by design, not 100% tested in production. Group to Group Skews at Common Transition Edges GROUP SYMBOL 200MHZ CPU to 3V661 SCPU200-3V66 3V66 to PCI DOT-USB DOT-VCH S3V66-PCI SDOT_USB SDOT_VCH CONDITIONS 3V66 (4:0) leads 200MHZ CPU 3V66 (4:0) leads 33MHz PCI 180 degrees out of phase in phase MIN -2.0 1.50 0.00 0.00 TYP -1.5 MAX -1.0 3.50 1.00 1.00 UNITS ns ns ns ns 1. 3V66 MHz CL = 0pf, Rseries = 33 ohm. CPU CL = 2 pf, Rseries = 33 ohm, Rshunt = 49.9 ohms. Measured at the pins of the 932S208. IDTTM Programmable Timing Control HubTM for Next Gen P4TM Processor 0743G—01/26/10 10 ICS932S208 Programmable Timing Control HubTM for Next Gen P4TM Processor General I2C serial interface information for the ICS932S208 How to Write: Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) sends the data byte count = X ICS clock will acknowledge Controller (host) starts sending Byte N through Byte N + X -1 (see Note 2) • ICS clock will acknowledge each byte one at a time • Controller (host) sends a Stop bit • • • • • • • • How to Read: • • • • • • • • • • • • • • Controller (host) will send start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) will send a separate start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the data byte count = X ICS clock sends Byte N + X -1 ICS clock sends Byte 0 through byte X (if X(H) was written to byte 8). Controller (host) will need to acknowledge each byte Controllor (host) will send a not acknowledge bit Controller (host) will send a stop bit Index Block Write Operation Controller (Host) starT bit T Slave Address D2(H) WR WRite Beginning Byte = N ACK Data Byte Count = X ACK Beginning Byte N ACK X Byte ICS (Slave/Receiver) Index Block Read Operation Controller (Host) T starT bit Slave Address D2(H) WR WRite Beginning Byte = N ACK RT Repeat starT Slave Address D3(H) RD ReaD ACK Data Byte Count = X ACK Beginning Byte N ACK X Byte ICS (Slave/Receiver) ACK ACK Byte N + X - 1 ACK P stoP bit Byte N + X - 1 N P Not acknowledge stoP bit IDTTM Programmable Timing Control HubTM for Next Gen P4TM Processor 0743G—01/26/10 11 ICS932S208 Programmable Timing Control HubTM for Next Gen P4TM Processor I C Table: Read-Back Register Byte 0 Pin # Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 - 2 Name RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED FSB FSA Control Function RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED Freq Select 1 Read Back Freq Select 0 Read Back Type R R 0 1 RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED PWD X X X X X X X X READBACK of CPU(3:0) Frequency I C Table: Spreading and Device Behavior Control Register Pin # Name Control Function Byte 1 SRC Free-Running 38, 37 SRC/SRC# Bit 7 Control 38, 37 SRC Output Control Bit 6 RESERVED RESERVED Bit 5 RESERVED RESERVED Bit 4 RESERVED RESERVED Bit 3 47, 46 CPUT2/CPUC2 Output Control Bit 2 44, 43 CPUT1/CPUC1 Output Control Bit 1 41, 40 CPUT0/CPUC0 Output Enable Bit 0 2 Type RW RW RW RW RW 0 FREE-RUN 1 STOPPABLE PWD 0 1 X X X 1 1 1 Disable Enable RESERVED RESERVED RESERVED Disable Enable Disable Enable Disable Enable I C Table: Output Control Register Pin # Byte 2 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 38, 37 38, 37 47, 46 44, 43 41, 40 - 2 Name SRC_PD# Drive Mode SRC_Stop# Drive Mode CPUT2_PD# Drive Mode CPUT1_PD# Drive Mode CPUT0_PD# Drive Mode RESERVED RESERVED RESERVED Control Function 0: Driven in PD# 0: Driven in PCI_Stop# Type RW RW RW 0 Driven Driven Driven Driven Driven 1 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z PWD 0 0 0 0 0 X X X 0:driven in PD# 1: Tri-stated RW RW RESERVED RESERVED RESERVED - RESERVED RESERVED RESERVED IDTTM Programmable Timing Control HubTM for Next Gen P4TM Processor 0743G—01/26/10 12 ICS932S208 Programmable Timing Control HubTM for Next Gen P4TM Processor I C Table: Output Control Register Byte 3 Pin # Bit 7 7,8,9,12,13,14,15, 18,19,20,37,38, 20 19 18 15 14 13 12 2 Name Control Function PCI_Stop# Control 0:all stoppable PCI are stopped Output Output Output Output Output Output Output Control Control Control Control Control Control Control Type RW 0 Enable 1 Disable PWD 1 PCI_Stop# Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PCICLK6 PCICLK5 PCICLK4 PCICLK3 PCICLK2 PCICLK1 PCICLK0 RW RW RW RW RW RW RW Disable Disable Disable Disable Disable Disable Disable Enable Enable Enable Enable Enable Enable Enable 1 1 1 1 1 1 1 I C Table: Output Control Register Byte 4 Pin # Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 31 31 9 8 7 9 8 7 2 Name Control Function 0=2x drive Output Control PCI FREE-RUN NING CONTROL Output Control Output Control Output Control Type RW RW RW RW RW RW RW RW 0 2x drive Disable FREE-RUN FREE-RUN FREE-RUN Disable Disable Disable 1 normal Enable STOPPABLE STOPPABLE STOPPABLE Enable Enable Enable PWD 1 1 0 0 0 1 1 1 48MHz_USB 2x output drive 48MHz_USB PCIF2 PCIF1 PCIF0 PCICLK_F2 PCICLK_F1 PCICLK_F0 I C Table: Output Control Register Byte 5 Pin # Name 32 48MHZ_DOT Bit 7 50/49 CPUT3/CPUC3 Bit 6 3V66_4/VCH 29 Bit 5 Select 29 3V66_4/VCH Bit 4 27 3V66_3 Bit 3 26 3V66_2 Bit 2 23 3V66_1 Bit 1 22 3V66_0 Bit 0 2 Control Function Output Control Output Control Output Select Output Output Output Output Output Control Control Control Control Control Type RW RW RW RW RW RW RW RW 0 Disable Disable 3V66 Disable Disable Disable Disable Disable 1 Enable Enable VCH Enable Enable Enable Enable Enable PWD 1 1 0 1 1 1 1 1 IDTTM Programmable Timing Control HubTM for Next Gen P4TM Processor 0743G—01/26/10 13 ICS932S208 Programmable Timing Control HubTM for Next Gen P4TM Processor I C Table: Output Control and Fix Frequency Register Pin # Name Control Function Byte 6 1,2,7,8,9,12,13,14, 15,18,19,20,22,23,2 6,27,29,31,32,37,38 ,40,41,43,44,46,47 40,41,43,44,46,47 37,38 2 Type 0 1 PWD Bit 7 Test Clock Mode Test Clock Mode RW Disable Enable 0 Bit 6 Bit 5 Bit 4 Bit 3 RESERVED FS Testmode SRC100# RESERVED FS_A and FS_B Operation SRC Frequency Select Spread Spectrum Enable Output Control Output Control RW RW - Normal 100MHz Spread OFF Disable Disable Test Mode 200MHz Spread ON Enable Enable 0 0 0 0 Bit 2 7,8,9,12,13,14,15,1 8,19,20,22,23,26,27 ,29,31,32,37,38,40, 41,43,44,46,47 2 1 SSEN RW 0 Bit 1 Bit 0 REF1 REF0 RW RW 1 1 I C Table: Vendor & Revision ID Register Pin # Name Byte 7 RID3 Bit 7 RID2 Bit 6 RID1 Bit 5 RID0 Bit 4 VID3 Bit 3 VID2 Bit 2 VID1 Bit 1 VID0 Bit 0 2 Control Function REVISION ID VENDOR ID Type R R R R R R R R 0 - 1 - PWD X X X X 0 0 0 1 IDTTM Programmable Timing Control HubTM for Next Gen P4TM Processor 0743G—01/26/10 14 ICS932S208 Programmable Timing Control HubTM for Next Gen P4TM Processor PCI Stop Functionality The PCI_STOP# signal is on an active low input controlling PCI and SRC outputs. If PCIF (2:0) and SRC clocks can be set to be free-running through I2C programming. Outputs set to be free-running will ignore both the PCI_STOP pin and the PCI_STOP register bit. PCI_STOP# 1 0 CPU Normal Normal CPU # Normal Normal SRC Normal Iref * 6 or Float SRC# Normal Low 3V66 66MHz 66MHz PCIF/PCI 33MHz Low USB/DOT 48MHz 48MHz REF 14.318MHz 14.318MHz Note PCI_STOP# Assertion (transition from '1' to '0') The clock samples the PCI_STOP# signal on a rising edge of PCIF clock. After detecting the PCI_STOP# assertion low, all PCI[6:0] and stoppable PCIF[2:0] clocks will latch low on their next high to low transition. After the PCI clocks are latched low, the SRC clock, (if set to stoppable) will latch high at Iref * 6 (or tristate if Byte 2 Bit 6 = 1) upon its next low to high transition and the SRC# will latch low as shown below. Tsu PCI_STOP# PCIF[2:0] 33MHz PCI[6:0] 33MHz SRC 100MHz SRC# 100MHz PCI_STOP# - De-assertion The de-assertion of the PCI_Stop# signal is to be sampled on the rising edge of the PCIF free running clock domain. After detecting PCI_Stop# de-assertion, all PCI[6:0], stoppable PCIF[2:0] and stoppable SRC clocks will resume in a glitch free manner. Tsu Tdrive_SRC PCI_STOP# PCIF[2:0] 33MHz PCI[6:0] 33MHz SRC 100MHz SRC# 100MHz IDTTM Programmable Timing Control HubTM for Next Gen P4TM Processor 0743G—01/26/10 15 ICS932S208 Programmable Timing Control HubTM for Next Gen P4TM Processor PD#, Power Down PD# is an asynchronous active low input used to shut off all clocks cleanly prior to clock power. When PD# is asserted low all clocks will be driven low before turning off the VCO. In PD# de-assertion all clocks will start without glitches. PWRDWN# 1 0 CPU Normal Iref * 2 or Float CPU # Normal Float SRC Normal Iref * 2 or Float SRC# Normal Float 3V66 66MHz Low PCIF/PCI 33MHz Low USB/DOT 48MHz Low REF 14.318MHz Low Note Notes: 1. Refer to tristate control of CPU and SRC clocks in section 7.7 for tristate timing and operation. 2. Refer to Control Registers in section 16 for CPU_Stop, SRC_Stop and PwrDwn SMBus tristate control addresses. PD# Assertion PD# should be sampled low by 2 consecutive CPU# rising edges before stopping clocks. All single ended clocks will be held low on their next high to low transition. All differential clocks will be held high on the next high to low transition of the complimentary clock. If the control register determining to drive mode is set to 'tri-state', the differential pair will be stopped in tri-state mode, undriven. When the drive mode but corresponding to the CPU or SRC clock of interest is set to '0' the true clock will be driven high at 2 x Iref and the complementary clock will be tristated. If the control register is programmed to '1' both clocks will be tristated. PWRDWN# CPU, 133MHz CPU#, 133MHz SRC, 100MHz SRC#, 100MHz 3V66, 66MHz USB, 48MHz PCI, 33MHz REF, 14.31818 IDTTM Programmable Timing Control HubTM for Next Gen P4TM Processor 0743G—01/26/10 16 ICS932S208 Programmable Timing Control HubTM for Next Gen P4TM Processor PD# De-assertion The time from the de-assertion of PD# or until power supply ramps to get stable clocks will be less than 1.8ms. If the drive mode control bit for PD# tristate is programmed to '1' the stopped differential pair must first be driven high to a minimum of 200mV in less than 300µs of PD# deassertion. Tstable