932S208DGLFT

DATASHEET Programmable Timing Control HubTM for Next Gen P4TM Processor Features/Benefits: • Supports tight ppm accuracy clocks for Serial-ATA • Supports spread spectrum modulation, 0 to -0.5% down spread and +/- 0.25% center spread Recommended Application: CK409B clock, Intel Yellow Cover part, Server Applications Output Features: • 4 - 0.7V current-mode differential CPU pairs • 1 - 0.7V current-mode differential SRC pair • 7 - PCI (33MHz) • 3 - PCICLK_F, (33MHz) free-running • 1 - USB, 48MHz • 1 - DOT, 48MHz • 2 - REF, 14.318MHz • 4 - 3V66, 66.66MHz • 1 - VCH/3V66, selectable 48MHz or 66MHz PCI MHz 33.33 Ref/N3 33.33 33.33 33.33 Hi-Z 33.33 33.33 33.33 33.33 • Uses external 14.318MHz crystal REF USB/DOT MHz MHz 14.318 48.00 Ref/N4 Ref/N5 14.318 48.00 14.318 48.00 14.318 48.00 Hi-Z Hi-Z 14.318 48.00 14.318 48.00 14.318 48.00 14.318 48.00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 ICS932S208 3V66 MHz 66.66 Ref/N2 66.66 66.66 66.66 Hi-Z 66.66 66.66 66.66 66.66 Supports CPU clks up to 400MHz in test mode REF0 REF1 VDDREF X1 X2 GND PCICLK_F0 PCICLK_F1 PCICLK_F2 VDDPCI GND PCICLK0 PCICLK1 PCICLK2 PCICLK3 VDDPCI GND PCICLK4 PCICLK5 PCICLK6 PD# 3V66_0 3V66_1 VDD3V66 GND 3V66_2 3V66_3 SCLK Functionality SRC MHz 100/200 Ref/N1 100/200 100/200 100/200 Hi-Z 100/200 100/200 100/200 100/200 • Pin Configuration Key Specifications: • CPU/SRC outputs cycle-cycle jitter < 125ps • 3V66 outputs cycle-cycle jitter < 250ps • PCI outputs cycle-cycle jitter < 250ps • CPU outputs skew: < 100ps • +/- 300ppm frequency accuracy on CPU & SRC clocks CPU B6b5 FS_A FS_B MHz 0 0 100 0 MID Ref/N0 0 1 200 0 1 0 133 1 1 166 1 MID Hi-Z 0 0 200 0 1 400 1 1 0 266 1 1 333 ICS932S208 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 FS_B VDDA GNDA GND IREF FS_A CPUCLKT3 CPUCLKC3 VDDCPU CPUCLKT2 CPUCLKC2 GND CPUCLKT1 CPUCLKC1 VDDCPU CPUCLKT0 CPUCLKC0 GND SRCCLKT SRCCLKC VDD Vtt_PWRGD# VDD48 GND 48MHz_DOT 48MHz_USB SDATA 3V66_4/VCH 56-pin SSOP & TSSOP IDT® Programmable Timing Control HubTM for Next Gen P4TM Processor 0743H—03/15/13 1 ICS932S208 Programmable Timing Control HubTM for Next Gen P4TM Processor Pin Description PIN # PIN NAME PIN TYPE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 REF0 REF1 VDDREF X1 X2 GND PCICLK_F0 PCICLK_F1 PCICLK_F2 VDDPCI GND PCICLK0 PCICLK1 PCICLK2 PCICLK3 VDDPCI GND PCICLK4 PCICLK5 PCICLK6 OUT OUT PWR IN OUT PWR OUT OUT OUT PWR PWR OUT OUT OUT OUT PWR PWR OUT OUT OUT 21 PD# IN 22 23 24 25 26 27 28 3V66_0 3V66_1 VDD3V66 GND 3V66_2 3V66_3 SCLK OUT OUT PWR PWR OUT OUT IN DESCRIPTION 14.318 MHz reference clock. 14.318 MHz reference clock. Ref, XTAL power supply, nominal 3.3V Crystal input, Nominally 14.318MHz. Crystal output, Nominally 14.318MHz Ground pin. Free running PCI clock not affected by PCI_STOP# . Free running PCI clock not affected by PCI_STOP# . Free running PCI clock not affected by PCI_STOP# . Power supply for PCI clocks, nominal 3.3V Ground pin. PCI clock output. PCI clock output. PCI clock output. PCI clock output. Power supply for PCI clocks, nominal 3.3V Ground pin. PCI clock output. PCI clock output. PCI clock output. Asynchronous active low input pin used to power down the device into a low power state. The internal clocks are disabled and the VCO and the crystal are stopped. The latency of the power down will not be greater than 1.8ms. Internal pull-up of 150K nominal. 3.3V 66.66MHz clock output 3.3V 66.66MHz clock output Power pin for the 3V66 clocks. Ground pin. 3.3V 66.66MHz clock output 3.3V 66.66MHz clock output Clock pin of I2C circuitry 5V tolerant IDT® Programmable Timing Control HubTM for Next Gen P4TM Processor 0743H—03/15/13 2 ICS932S208 Programmable Timing Control HubTM for Next Gen P4TM Processor Pin Description (continued) PIN # PIN NAME PIN TYPE 29 3V66_4/VCH OUT 30 31 32 33 34 SDATA 48MHz_USB 48MHz_DOT GND VDD48 I/O OUT OUT PWR PWR 35 Vtt_PWRGD# IN 36 VDD PWR 37 SRCCLKC OUT 38 SRCCLKT OUT 39 GND PWR 40 CPUCLKC0 OUT 41 CPUCLKT0 OUT 42 VDDCPU PWR 43 CPUCLKC1 OUT 44 CPUCLKT1 OUT 45 GND PWR 46 CPUCLKC2 OUT 47 CPUCLKT2 OUT 48 VDDCPU PWR 49 CPUCLKC3 OUT 50 CPUCLKT3 OUT 51 FS_A IN 52 IREF OUT 53 54 55 56 GND GNDA VDDA FS_B PWR PWR PWR IN DESCRIPTION 66.66MHz clock output for AGP support. AGP-PCI should be aligned with a skew window tolerance of 500ps. VCH is 48MHz clock output for video controller hub. Data pin for I2C circuitry 5V tolerant 48MHz clock output. 48MHz clock output. Ground pin. Power pin for the 48MHz output.3.3V This 3.3V LVTTL input is a level sensitive strobe used to determine when latch inputs are valid and are ready to be sampled. This is an active low input. Power supply for SRC clocks, nominal 3.3V Complement clock of differential pair for S-ATA support. +/- 300ppm accuracy required. True clock of differential pair for S-ATA support. +/- 300ppm accuracy required. Ground pin. Complimentary clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. True clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. Supply for CPU clocks, 3.3V nominal Complimentary clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. True clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. Ground pin. Complimentary clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. True clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. Supply for CPU clocks, 3.3V nominal Complimentary clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. True clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. Frequency select pin, see Frequency table for functionality This pin establishes the reference current for the differential currentmode output pairs. This pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. 475 ohms is the standard value. Ground pin. Ground pin for core. 3.3V power for the PLL core. Frequency select pin, see Frequency table for functionality IDT® Programmable Timing Control HubTM for Next Gen P4TM Processor 0743H—03/15/13 3 ICS932S208 Programmable Timing Control HubTM for Next Gen P4TM Processor General Description ICS932S208 follows Intel CK409B Yellow Cover specification. This clock synthesizer provides a single chip solution for next generation P4 Intel processors and Intel chipsets. ICS932S208 is driven with a 14.318MHz crystal. It generates CPU outputs up to 200MHz. It also provides a tight ppm accuracy output for Serial ATA support. Block Diagram Frequency Dividers PLL2 X1 X2 48MHz, USB, DOT XTAL REF (1:0) CPUCLKT (3:0) CPUCLKC (3:0) SRCCLKT0 Programmable Spread PLL1 SCLK SDATA Vtt_PWRGD# PD# Programmable Frequency Dividers STOP Logic SRCCLKC0 3V66(4:0) PCICLK (6:0) Control Logic PCICLKF (2:0) FS_A I REF FS_B Power Groups Pin Number VDD GND 3 6 24 25 10,16 11,17 36 39 55 54 34 33 N/A 53 48, 42 45 Description Xtal, Ref 3V66 [0:4] PCICLK outputs SRCCLK outputs Master clock, CPU Analog 48MHz, PLL IREF CPUCLK clocks IDT® Programmable Timing Control HubTM for Next Gen P4TM Processor 0743H—03/15/13 4 ICS932S208 Programmable Timing Control HubTM for Next Gen P4TM Processor Absolute Maximum Ratings Symbol VDD_A VDD_In Ts Tambient Tcase ESD prot Parameter 3.3V Core Supply Voltage 3.3V Logic Input Supply Voltage Storage Temperature Ambient Operating Temp Case Temperature Input ESD protection human body model Min Max VDD + 0.5V VDD + 0.5V 150 70 115 GND - 0.5 -65 0 2000 Units V V ° C °C °C V Electrical Characteristics - Input/Supply/Common Output Parameters TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5% PARAMETER Input High Voltage Input MID Voltage Input Low Voltage Input High Current SYMBOL VIH VMID VIL IIH IIL1 Input Low Current IIL2 Operating Supply Current IDD3.3OP Powerdown Current IDD3.3PD 3 Input Frequency 1 Pin Inductance Fi Lpin CIN COUT CINX CONDITIONS 3.3 V +/-5% 3.3 V +/-5% 3.3 V +/-5% VIN = VDD VIN = 0 V; Inputs with no pull-up resistors VIN = 0 V; Inputs with pull-up resistors MIN 2 1 VSS - 0.3 -5 TYP MAX UNITS NOTES VDD + 0.3 V 1.8 V 0.8 V 5 uA -5 uA -200 uA Full Active, CL = Full load; 350 mA all diff pairs driven all differential pairs tri-stated VDD = 3.3 V 35 12 mA mA MHz nH pF pF pF 3 1 1 1 1 ms 1,2 kHz 1 ns 1 us 1 ns ns 1 2 us 1 ns ns 1 2 14.31818 7 5 6 5 Logic Inputs Output pin capacitance X1 & X2 pins From V DD Power-Up or de1,2 TSTAB 1.8 Clk Stabilization assertion of PD# to 1st clock Triangular Modulation 30 33 Modulation Frequency SRC output enable after Tdrive_SRC 15 PCI_Stop# de-assertion CPU output enable after Tdrive_PD# 300 PD# de-assertion Tfall_Pd# PD# fall time of 5 Trise_Pd# PD# rise time of 5 CPU output enable after 10 Tdrive_CPU_Stop# CPU_Stop# de-assertion Tfall_CPU_Stop# PD# fall time of 5 Trise_CPU_Stop# PD# rise time of 5 1 Guaranteed by design, not 100% tested in production. 2 See timing diagrams for timing requirements. 3 Input frequency should be measured at the REF output pin and tuned to ideal 14.31818MHz to meet ppm frequency accuracy on PLL outputs. 1 Input Capacitance IDT® Programmable Timing Control HubTM for Next Gen P4TM Processor 0743H—03/15/13 5 ICS932S208 Programmable Timing Control HubTM for Next Gen P4TM Processor Electrical Characteristics - CPU & SRC 0.7V Current Mode Differential Pair TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL =2pF PARAMETER Current Source Output Impedance Output High Voltage Output Low Voltage SYMBOL CONDITIONS MIN Zo VO = Vx 3000 VOH3 VOL3 IOH = -1 mA IOL = 1 mA 2.4 Voltage High VHigh Statistical measurement on single ended signal using oscilloscope math function. Measurement on single ended signal using absolute value. 660 1 Voltage Low VLow Max Voltage Min Voltage Crossing Voltage (abs) Vovs Vuds Vcross(abs) Crossing Voltage (var) d-Vcross Long Accuracy ppm Average period Tperiod Absolute min period Tabsmin Rise Time Fall Time Rise Time Variation Fall Time Variation tr tf d-tr d-tf Variation of crossing over all edges see Tperiod min-max values 200MHz nominal 200MHz spread 166.66MHz nominal 166.66MHz spread 133.33MHz nominal 133.33MHz spread 100.00MHz nominal 100.00MHz spread 200MHz nominal 166.66MHz nominal/spread 133.33MHz nominal/spread 100.00MHz nominal/spread VOL = 0.175V, VOH = 0.525V VOH = 0.525V VOL = 0.175V TYP MAX UNITS NOTES  1 V 0.4 850 1 mV -150 150 1150 -300 250 -300 4.9985 4.9985 5.9982 5.9982 7.4978 7.4978 9.9970 9.9970 4.8735 5.8732 7.3728 9.8720 175 175 1 550 mV 1 1 1 140 mV 1 300 5.0015 5.0266 6.0018 6.0320 7.5023 5.4000 10.0030 10.0533 ppm ns ns ns ns ns ns ns ns ns ns ns ns ps ps ps ps 1,2 2 2 2 2 2 2 2 2 1,2 1,2 1,2 1,2 1 1 1 1 700 700 125 125 mV Measurement from differential 45 55 % wavefrom VT = 50% tsk3 100 ps Skew Measurement from differential tjcyc-cyc 125 ps Jitter, Cycle to cycle wavefrom 1 Guaranteed by design, not 100% tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that Ref output is at 14.31818MHz SRC clock outputs run at only 100MHz or 200MHz, specs for 133.33 and 166.66 do not apply to SRC clock pair. Duty Cycle dt3 IDT® Programmable Timing Control HubTM for Next Gen P4TM Processor 1 1 1 0743H—03/15/13 6 ICS932S208 Programmable Timing Control HubTM for Next Gen P4TM Processor Electrical Characteristics - 3V66 Mode: 3V66 [4:0] TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 10-30 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS ppm see Tperiod min-max values Long Accuracy 66.66MHz output nominal Tperiod Clock period 66.66MHz output spread VOH IOH = -1 mA Output High Voltage IOL = 1 mA VOL Output Low Voltage V OH @ MIN = 1.0 V IOH Output High Current VOH @ MAX = 3.135 V VOL @ MIN = 1.95 V IOL Output Low Current VOL @ MAX = 0.4 V Edge Rate Rising edge rate Falling edge rate Edge Rate tr1 VOL = 0.4 V, VOH = 2.4 V Rise Time tf1 VOH = 2.4 V, VOL = 0.4 V Fall Time VT = 1.5 V dt1 Duty Cycle MIN -300 14.9955 14.9955 2.4 TYP MAX 300 15.0045 15.0799 Notes 1,2 2 2 38 4 4 2 2 55 UNITS ppm ns ns V V mA mA mA mA V/ns V/ns ns ns % 0.55 -33 -33 30 1 1 0.5 0.5 45 1 1 1 1 1 Skew tsk1 VT = 1.5 V 250 ps 1 Jitter tjcyc-cyc VT = 1.5 V 3V66 250 ps 1 1 Guaranteed by design, not 100% tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that Ref output is at 14.31818MHz Electrical Characteristics - PCICLK/PCICLK_F TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 10-30 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS MIN Long Accuracy ppm Clock period Tperiod Output High Voltage Output Low Voltage VOH VOL see Tperiod min-max values 33.33MHz output nominal 33.33MHz output spread IOH = -1 mA IOL = 1 mA V OH @MIN = 1.0 V VOH@ MAX = 3.135 V VOL @ MIN = 1.95 V VOL @ MAX = 0.4 V -300 29.9910 29.9910 2.4 Rising edge rate Falling edge rate VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V 3V66 1 1 0.5 0.5 45 Output High Current Output Low Current Edge Rate Edge Rate Rise Time Fall Time Duty Cycle Skew Jitter IOH IOL tr1 tf1 dt1 tsk1 tjcyc-cyc TYP MAX UNITS Notes 300 30.0090 30.1598 ppm ns ns V V mA mA mA mA V/ns V/ns ns ns % ps ps 1,2 2 2 0.55 -33 -33 30 38 4 4 2 2 55 500 250 1 1 1 1 1 1 1 1 Guaranteed by design, not 100% tested in production. All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that Ref output is at 14.31818MHz 2 IDT® Programmable Timing Control HubTM for Next Gen P4TM Processor 0743H—03/15/13 7 ICS932S208 Programmable Timing Control HubTM for Next Gen P4TM Processor Electrical Characteristics - 48MHz DOT Clock TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 5-10 pF (unless otherwise specified) PARAMETER SYMBOL Long Accuracy ppm Clock period Output High Voltage Output Low Voltage Tperiod VOH VOL Output High Current IOH Output Low Current IOL Edge Rate Edge Rate CONDITIONS MIN see Tperiod min-max -200 values 66.66MHz output nominal 20.8257 IOH = -1 mA 2.4 IOL = 1 mA V OH @ MIN = 1.0 V -33 VOH @ MAX = 3.135 V VOL @ MIN = 1.95 V 30 VOL @ MAX = 0.4 V Rising edge rate 2 Falling edge rate 2 TYP MAX UNITS Notes 200 ppm 1,2 20.8340 2 38 4 4 ns V V mA mA mA mA V/ns V/ns 1 1 0.55 -33 Rise Time tr1 VOL = 0.4 V, VOH = 2.4 V 0.5 1 ns 1 Fall Time tf1 VOH = 2.4 V, VOL = 0.4 V 0.5 1 ns 1 VT = 1.5 V 45 55 % 125us period jitter Long Term Jitter 2 ns (8kHz frequency modulation amplitude) 1 Guaranteed by design, not 100% tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that Ref output is at 14.31818MHz 1 Duty Cycle dt1 IDT® Programmable Timing Control HubTM for Next Gen P4TM Processor 1 0743H—03/15/13 8 ICS932S208 Programmable Timing Control HubTM for Next Gen P4TM Processor Electrical Characteristics - VCH, 48MHz, USB TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER SYMBOL Long Accuracy Clock period Output High Voltage Output Low Voltage ppm Tperiod VOH VOL CONDITIONS MIN TYP MAX UNITS Notes see Tperiod min-max values -200 200 ppm 66.66MHz output nominal 20.8257 20.8340 ns IOH = -1 mA 2.4 V IOL = 1 mA 0.55 V V OH @ MIN = 1.0 V -33 mA IOH Output High Current VOH@ MAX = 3.135 V -33 mA VOL @MIN = 1.95 V 30 mA IOL Output Low Current VOL @ MAX = 0.4 V 38 mA Rising edge rate 1 2 V/ns Edge Rate Edge Rate Falling edge rate 1 2 V/ns VOL = 0.4 V, VOH = 2.4 V tr1 1 2 ns Rise Time tf1 VOH = 2.4 V, VOL = 0.4 V Fall Time 1 2 ns VT = 1.5 V dt1 45 55 % Duty Cycle 125us period jitter Long Term Jitter 6 ns (8kHz frequency modulation amplitude) 1 Guaranteed by design, not 100% tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that Ref output is at 14.31818MHz IDT® Programmable Timing Control HubTM for Next Gen P4TM Processor 1,2 2 1 1 1 1 1 1 0743H—03/15/13 9 ICS932S208 Programmable Timing Control HubTM for Next Gen P4TM Processor Electrical Characteristics - REF-14.318MHz TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 10-20 pF (unless otherwise specified) 1 PARAMETER SYMBOL Long Accuracy Clock period Output High Voltage Output Low Voltage ppm Tperiod Output High Current IOH1 Output Low Current IOL Rise Time Fall Time Skew Duty Cycle tr1 1 tf1 1 tsk1 dt11 Jitter tjcyc-cyc1 1 VOH1 VOL1 1 1 CONDITIONS MIN TYP see Tperiod min-max values -300 14.318MHz output nominal 69.8270 IOH = -1 mA 2.4 IOL = 1 mA V OH @MIN = 1.0 V, V -29 OH@MAX = 3.135 V VOL @MIN = 1.95 V, VOL 29 @MAX = 0.4 V VOL = 0.4 V, VOH = 2.4 V 1 VOH = 2.4 V, VOL = 0.4 V 1 VT = 1.5 V VT = 1.5 V 45 VT = 1.5 V MAX UNITS 300 69.8550 0.4 ppm ns V V -23 mA 27 mA 2 2 500 55 ns ns ps % 1000 ps Guaranteed by design, not 100% tested in production. Group to Group Skews at Common Transition Edges GROUP SYMBOL 1 200MHZ CPU to 3V66 SCPU200-3V66 3V66 to PCI DOT-USB DOT-VCH S3V66-PCI SDOT_USB SDOT_VCH CONDITIONS 3V66 (4:0) leads 200MHZ CPU 3V66 (4:0) leads 33MHz PCI 180 degrees out of phase in phase MIN TYP MAX UNITS -2.0 -1.5 -1.0 ns 3.50 1.00 1.00 ns ns ns 1.50 0.00 0.00 1. 3V66 MHz CL = 0pf, Rseries = 33 ohm. CPU CL = 2 pf, Rseries = 33 ohm, Rshunt = 49.9 ohms. Measured at the pins of the 932S208. IDT® Programmable Timing Control HubTM for Next Gen P4TM Processor 0743H—03/15/13 10 ICS932S208 Programmable Timing Control HubTM for Next Gen P4TM Processor General I2C serial interface information for the ICS932S208 How to Write: How to Read: Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) sends the data byte count = X ICS clock will acknowledge Controller (host) starts sending Byte N through Byte N + X -1 (see Note 2) • ICS clock will acknowledge each byte one at a time • Controller (host) sends a Stop bit • • • • • • • • • • • • • • • • • • • • • • Controller (host) will send start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) will send a separate start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the data byte count = X ICS clock sends Byte N + X -1 ICS clock sends Byte 0 through byte X (if X(H) was written to byte 8). Controller (host) will need to acknowledge each byte Controllor (host) will send a not acknowledge bit Controller (host) will send a stop bit Index Block Read Operation Index Block Write Operation Controller (Host) starT bit T Slave Address D2(H) WR WRite Controller (Host) T starT bit Slave Address D2(H) WR WRite ICS (Slave/Receiver) ICS (Slave/Receiver) ACK ACK Beginning Byte = N Beginning Byte = N ACK ACK RT Repeat starT Slave Address D3(H) RD ReaD Data Byte Count = X ACK Beginning Byte N ACK X Byte ACK Data Byte Count = X ACK Beginning Byte N Byte N + X - 1 ACK X Byte ACK P stoP bit Byte N + X - 1 N P IDT® Programmable Timing Control HubTM for Next Gen P4TM Processor Not acknowledge stoP bit 0743H—03/15/13 11 ICS932S208 Programmable Timing Control HubTM for Next Gen P4TM Processor 2 I C Table: Read-Back Register Pin # Byte 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Name RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED Bit 1 - FSB Bit 0 - FSA Control Function RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED Freq Select 1 Read Back Freq Select 0 Read Back Type R R 0 1 RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED READBACK of CPU(3:0) Frequency PWD X X X X X X X X 2 I C Table: Spreading and Device Behavior Control Register Pin # Name Control Function Byte 1 SRC Free-Running 38, 37 SRC/SRC# Bit 7 Control SRC Output Control 38, 37 Bit 6 RESERVED RESERVED Bit 5 RESERVED RESERVED Bit 4 RESERVED RESERVED Bit 3 CPUT2/CPUC2 Output Control 47, 46 Bit 2 CPUT1/CPUC1 Output Control 44, 43 Bit 1 CPUT0/CPUC0 Output Enable 41, 40 Bit 0 Type 0 1 PWD RW FREE-RUN STOPPABLE 0 RW RW RW RW Disable Enable RESERVED RESERVED RESERVED Disable Enable Disable Enable Disable Enable 1 X X X 1 1 1 2 I C Table: Output Control Register Pin # Byte 2 Control Function Type 0 1 PWD Bit 7 38, 37 0: Driven in PD# RW Driven Hi-Z 0 Bit 6 38, 37 0: Driven in PCI_Stop# RW Driven Hi-Z 0 Bit 5 47, 46 RW Driven Hi-Z 0 Bit 4 44, 43 RW Driven Hi-Z 0 Bit 3 41, 40 RW Driven Hi-Z 0 Bit 2 Bit 1 Bit 0 - Name SRC_PD# Drive Mode SRC_Stop# Drive Mode CPUT2_PD# Drive Mode CPUT1_PD# Drive Mode CPUT0_PD# Drive Mode RESERVED RESERVED RESERVED 0:driven in PD# 1: Tri-stated RESERVED RESERVED RESERVED IDT® Programmable Timing Control HubTM for Next Gen P4TM Processor - RESERVED RESERVED RESERVED X X X 0743H—03/15/13 12 ICS932S208 Programmable Timing Control HubTM for Next Gen P4TM Processor 2 I C Table: Output Control Register Byte 3 Pin # Name Control Function Type 0 1 PWD PCI_Stop# Control 0:all stoppable PCI are stopped RW Enable Disable 1 RW RW RW RW RW RW RW Disable Disable Disable Disable Disable Disable Disable Enable Enable Enable Enable Enable Enable Enable 1 1 1 1 1 1 1 Bit 7 7,8,9,12,13,14,15, 18,19,20,37,38, PCI_Stop# Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 20 19 18 15 14 13 12 PCICLK6 PCICLK5 PCICLK4 PCICLK3 PCICLK2 PCICLK1 PCICLK0 I C Table: Output Control Register Pin # Byte 4 Name Control Function Type 0 1 PWD 48MHz_USB 2x output drive 48MHz_USB PCIF2 PCIF1 PCIF0 PCICLK_F2 PCICLK_F1 PCICLK_F0 0=2x drive RW 2x drive normal 1 Output Control Output Control Output Control Output Control RW RW RW RW RW RW RW Disable FREE-RUN FREE-RUN FREE-RUN Disable Disable Disable Enable STOPPABLE STOPPABLE STOPPABLE Enable Enable Enable 1 0 0 0 1 1 1 Control Function Output Control Output Control Type RW RW 0 Disable Disable 1 Enable Enable PWD 1 1 Output Select RW 3V66 VCH 0 Output Output Output Output Output RW RW RW RW RW Disable Disable Disable Disable Disable Enable Enable Enable Enable Enable 1 1 1 1 1 Output Output Output Output Output Output Output Control Control Control Control Control Control Control 2 Bit 7 31 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 31 9 8 7 9 8 7 PCI FREE-RUN NING CONTROL 2 I C Table: Output Control Register Byte 5 Pin # Name 32 48MHZ_DOT Bit 7 50/49 CPUT3/CPUC3 Bit 6 3V66_4/VCH 29 Bit 5 Select 29 3V66_4/VCH Bit 4 27 3V66_3 Bit 3 26 3V66_2 Bit 2 23 3V66_1 Bit 1 3V66_0 22 Bit 0 Control Control Control Control Control IDT® Programmable Timing Control HubTM for Next Gen P4TM Processor 0743H—03/15/13 13 ICS932S208 Programmable Timing Control HubTM for Next Gen P4TM Processor 2 I C Table: Output Control and Fix Frequency Register Byte 6 Pin # Name Control Function Bit 7 1,2,7,8,9,12,13,14, 15,18,19,20,22,23,2 6,27,29,31,32,37,38 ,40,41,43,44,46,47 Test Clock Mode Bit 6 - RESERVED Bit 5 40,41,43,44,46,47 FS Testmode Bit 4 37,38 SRC100# RESERVED Bit 3 Type 0 1 PWD Test Clock Mode RW Disable Enable 0 FS_A and FS_B Operation SRC Frequency Select - - - - 0 RW Normal Test Mode 0 RW 100MHz 200MHz 0 - - - 0 Bit 2 7,8,9,12,13,14,15,1 8,19,20,22,23,26,27 ,29,31,32,37,38,40, 41,43,44,46,47 SSEN Spread Spectrum Enable RW Spread OFF Spread ON 0 Bit 1 Bit 0 2 1 REF1 REF0 Output Control Output Control RW RW Disable Disable Enable Enable 1 1 Control Function Type R R R R R R R R 0 - 1 - PWD X X X X 0 0 0 1 2 I C Table: Vendor & Revision ID Register Byte 7 Pin # Name RID3 Bit 7 RID2 Bit 6 RID1 Bit 5 RID0 Bit 4 VID3 Bit 3 VID2 Bit 2 VID1 Bit 1 VID0 Bit 0 REVISION ID VENDOR ID IDT® Programmable Timing Control HubTM for Next Gen P4TM Processor 0743H—03/15/13 14 ICS932S208 Programmable Timing Control HubTM for Next Gen P4TM Processor PCI Stop Functionality The PCI_STOP# signal is on an active low input controlling PCI and SRC outputs. If PCIF (2:0) and SRC clocks can be set to be free-running through I2C programming. Outputs set to be free-running will ignore both the PCI_STOP pin and the PCI_STOP register bit. PCI_STOP# CPU CPU # SRC SRC# 3V66 PCIF/PCI USB/DOT REF 1 Normal Normal Normal Normal 66MHz 33MHz 48MHz 14.318MHz 0 Normal Normal Iref * 6 or Float Low 66MHz Low 48MHz 14.318MHz Note PCI_STOP# Assertion (transition from '1' to '0') The clock samples the PCI_STOP# signal on a rising edge of PCIF clock. After detecting the PCI_STOP# assertion low, all PCI[6:0] and stoppable PCIF[2:0] clocks will latch low on their next high to low transition. After the PCI clocks are latched low, the SRC clock, (if set to stoppable) will latch high at Iref * 6 (or tristate if Byte 2 Bit 6 = 1) upon its next low to high transition and the SRC# will latch low as shown below. Tsu PCI_STOP# PCIF[2:0] 33MHz PCI[6:0] 33MHz SRC 100MHz SRC# 100MHz PCI_STOP# - De-assertion The de-assertion of the PCI_Stop# signal is to be sampled on the rising edge of the PCIF free running clock domain. After detecting PCI_Stop# de-assertion, all PCI[6:0], stoppable PCIF[2:0] and stoppable SRC clocks will resume in a glitch free manner. Tsu Tdrive_SRC PCI_STOP# PCIF[2:0] 33MHz PCI[6:0] 33MHz SRC 100MHz SRC# 100MHz IDT® Programmable Timing Control HubTM for Next Gen P4TM Processor 0743H—03/15/13 15 ICS932S208 Programmable Timing Control HubTM for Next Gen P4TM Processor PD#, Power Down PD# is an asynchronous active low input used to shut off all clocks cleanly prior to clock power. When PD# is asserted low all clocks will be driven low before turning off the VCO. In PD# de-assertion all clocks will start without glitches. PWRDWN# CPU CPU # SRC SRC# 3V66 PCIF/PCI USB/DOT REF 1 Normal Normal Normal Normal 66MHz 33MHz 48MHz 14.318MHz 0 Iref * 2 or Float Float Iref * 2 or Float Float Low Low Low Low Note Notes: 1. Refer to tristate control of CPU and SRC clocks in section 7.7 for tristate timing and operation. 2. Refer to Control Registers in section 16 for CPU_Stop, SRC_Stop and PwrDwn SMBus tristate control addresses. PD# Assertion PD# should be sampled low by 2 consecutive CPU# rising edges before stopping clocks. All single ended clocks will be held low on their next high to low transition. All differential clocks will be held high on the next high to low transition of the complimentary clock. If the control register determining to drive mode is set to 'tri-state', the differential pair will be stopped in tri-state mode, undriven. When the drive mode but corresponding to the CPU or SRC clock of interest is set to '0' the true clock will be driven high at 2 x Iref and the complementary clock will be tristated. If the control register is programmed to '1' both clocks will be tristated. PWRDWN# CPU, 133MHz CPU#, 133MHz SRC, 100MHz SRC#, 100MHz 3V66, 66MHz USB, 48MHz PCI, 33MHz REF, 14.31818 IDT® Programmable Timing Control HubTM for Next Gen P4TM Processor 0743H—03/15/13 16 ICS932S208 Programmable Timing Control HubTM for Next Gen P4TM Processor PD# De-assertion The time from the de-assertion of PD# or until power supply ramps to get stable clocks will be less than 1.8ms. If the drive mode control bit for PD# tristate is programmed to '1' the stopped differential pair must first be driven high to a minimum of 200mV in less than 300μs of PD# deassertion. Tstable