9DB403DGILFT

DATASHEET Four Output Differential Buffer for PCIe Gen 1 and Gen 2 Description The ICS9DB403 is compatible with the Intel DB400v2 Differential Buffer Specification. This buffer provides 4 PCI-Express Gen2 clocks. The ICS9DB403 is driven by a differential output pair from a CK410B+, CK505 or CK509B main clock generator. ICS9DB403D Features/Benefits • • Spread spectrum modulation tolerant, 0 to -0.5% down spread and +/- 0.25% center spread. Supports undriven differential outputs in PD# and SRC_STOP# modes for power management. Output Features • • • • • 4 - 0.7V current-mode differential output pairs Supports zero delay buffer mode and fanout mode Bandwidth programming available 50-100 MHz operation in PLL mode 50-400 MHz operation in Bypass mode Key Specifications • • • • • • • Outputs cycle-cycle jitter < 50ps Outputs skew: 50ps Phase jitter: PCIe Gen1 < 86ps peak to peak Phase jitter: PCIe Gen2 < 3.0/3.1ps rms 28-pin SSOP/TSSOP pacakge Available in RoHS compliant packaging Supports Commercial (0 to +70°C) and Industrial (-40 to +85°C) temperature ranges Functional Block Diagram 24 -OE(6, 1) OE(6,5,2,1) SRC_IN SRC_IN# SPREAD COMPATIBLE PLL 4 M U X STOP LOGIC DIF(6,5,2,1) PD BYPASS#/PLL SDATA SCLK CONTROL LOGIC IREF Note: Polarities shown for OE_INV = 0. IDTTM/ICSTM Four Output Differential Buffer for PCIe and Gen 1 and Gen 2 ICS9DB403D REV L 10/07/09 1 ICS9DB403D Four Output Differential Buffer for PCIe for Gen 1 and Gen 2 Pin Configuration VDD SRC_IN SRC_IN# GND VDD DIF_1 DIF_1# OE_1 DIF_2 DIF_2# VDD BYPASS#/PLL SCLK SDATA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 OE_INV = 0 VDDA GNDA IREF OE_INV VDD DIF_6 DIF_6# OE_6 DIF_5 DIF_5# VDD HIGH_BW# DIF_STOP# PD# VDD SRC_IN SRC_IN# GND VDD DIF_1 DIF_1# OE1# DIF_2 DIF_2# VDD BYPASS#/PLL SCLK SDATA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 OE_INV = 1 VDDA GNDA IREF OE_INV VDD DIF_6 DIF_6# OE6# DIF_5 DIF_5# VDD HIGH_BW# DIF_STOP PD ICS9DB403D (same as ICS9DB104) 28-pin SSOP & TSSOP Polarity Inversion Pin List Table OE_INV Pins 8 15 16 21 0 OE_1 PD# DIF_STOP# OE_6 1 OE1# PD DIF_STOP OE6# Power Groups Pin Number VDD GND 1 4 5,11,18, 24 4 N/A 27 28 27 Description SRC_IN/SRC_IN# DIF(1,2,5,6) IREF Analog VDD & GND for PLL core IDTTM/ICSTM Four Output Differential Buffer for PCIe Gen 1 and Gen 2 ICS9DB403D (same as ICS9DB401) ICS9DB403D REV L 10/07/09 2 ICS9DB403D Four Output Differential Buffer for PCIe for Gen 1 and Gen 2 Pin Decription When OE_INV = 0 PIN # PIN NAME PIN TYPE 1 VDD PWR 2 SRC_IN IN 3 SRC_IN# IN 4 GND PWR 5 VDD PWR 6 DIF_1 OUT 7 DIF_1# OUT 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 OE_1 DIF_2 DIF_2# VDD BYPASS#/PLL SCLK SDATA PD# DIF_STOP# HIGH_BW# VDD DIF_5# DIF_5 OE_6 DIF_6# DIF_6 VDD OE_INV IREF GNDA VDDA IN OUT OUT PWR IN IN I/O IN IN IN PWR OUT OUT IN OUT OUT PWR IN OUT PWR PWR DESCRIPTION Power supply, nominal 3.3V 0.7 V Differential SRC TRUE input 0.7 V Differential SRC COMPLEMENTARY input Ground pin. Power supply, nominal 3.3V 0.7V differential true clock output 0.7V differential Complementary clock output Active high input for enabling output 1. 0 = tri-state outputs, 1= enable outputs 0.7V differential true clock output 0.7V differential Complementary clock output Power supply, nominal 3.3V Input to select Bypass(fan-out) or PLL (ZDB) mode 0 = Bypass mode, 1= PLL mode Clock pin of SMBus circuitry, 5V tolerant. Data pin for SMBus circuitry, 3.3V tolerant. Asynchronous active low input pin used to power down the device. The internal clocks are disabled and the VCO and the crystal osc. (if any) are stopped. Active low input to stop differential output clocks. 3.3V input for selecting PLL Band Width 0 = High, 1= Low Power supply, nominal 3.3V 0.7V differential Complementary clock output 0.7V differential true clock output Active high input for enabling output 6. 0 = tri-state outputs, 1= enable outputs 0.7V differential Complementary clock output 0.7V differential true clock output Power supply, nominal 3.3V This latched input selects the polarity of the OE pins. 0 = OE pins active high, 1 = OE pins active low (OE#) This pin establishes the reference current for the differential current-mode output pairs. This pin requires a fixed precision resistor tied to g round in order to establish the appropriate current. 475 ohms is the standard value. Ground pin for the PLL core. 3.3V power for the PLL core. IDTTM/ICSTM Four Output Differential Buffer for PCIe Gen 1 and Gen 2 ICS9DB403D REV L 10/07/09 3 ICS9DB403D Four Output Differential Buffer for PCIe for Gen 1 and Gen 2 Pin Decription When OE_INV = 1 PIN # PIN NAME PIN TYPE 1 VDD PWR 2 SRC_IN IN 3 SRC_IN# IN 4 GND PWR 5 VDD PWR 6 DIF_1 OUT 7 DIF_1# OUT 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 OE1# DIF_2 DIF_2# VDD BYPASS#/PLL SCLK SDATA PD DIF_STOP HIGH_BW# VDD DIF_5# DIF_5 OE6# DIF_6# DIF_6 VDD OE_INV IN OUT OUT PWR IN IN I/O IN IN IN PWR OUT OUT IN OUT OUT PWR IN 26 27 28 IREF GNDA VDDA OUT PWR PWR DESCRIPTION Power supply, nominal 3.3V 0.7 V Differential SRC TRUE input 0.7 V Differential SRC COMPLEMENTARY input Ground pin. Power supply, nominal 3.3V 0.7V differential true clock output 0.7V differential Complementary clock output Active low input for enabling DIF pair 1. 1 = tri-state outputs, 0 = enable outputs 0.7V differential true clock output 0.7V differential Complementary clock output Power supply, nominal 3.3V Input to select Bypass(fan-out) or PLL (ZDB) mode 0 = Bypass mode, 1= PLL mode Clock pin of SMBus circuitry, 5V tolerant. Data pin for SMBus circuitry, 3.3V tolerant. Asynchronous active high input pin used to power down the device. The internal clocks are disabled and the VCO is stopped. Active High input to stop differential output clocks. 3.3V input for selecting PLL Band Width 0 = High, 1= Low Power supply, nominal 3.3V 0.7V differential Complementary clock output 0.7V differential true clock output Active low input for enabling DIF pair 6. 1 = tri-state outputs, 0 = enable outputs 0.7V differential Complementary clock output 0.7V differential true clock output Power supply, nominal 3.3V This latched input selects the polarity of the OE pins. 0 = OE pins active high, 1 = OE pins active low (OE#) This pin establishes the reference current for the differential currentmode output pairs. This pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. 475 ohms is the standard value. Ground pin for the PLL core. 3.3V power for the PLL core. IDTTM/ICSTM Four Output Differential Buffer for PCIe Gen 1 and Gen 2 ICS9DB403D REV L 10/07/09 4 ICS9DB403D Four Output Differential Buffer for PCIe for Gen 1 and Gen 2 Absolute Max Symbol VDD_A VDD_In VIL VIH Ts Tambient Tcase ESD prot Parameter 3.3V Core Supply Voltage 3.3V Logic Supply Voltage Input Low Voltage Input High Voltage Storage Temperature Commerical Operating Range Industrial Operating Range Case Temperature Input ESD protection human body model Min Max 4.6 4.6 VDD+0.5V -65 0 -40 150 70 85 115 Units V V V V C °C °C °C V ° GND-0.5 2000 Electrical Characteristics - Clock Input Parameters TA = Tambient for the desired operating range, Supply Voltage VDD = 3.3 V +/-5% PARAMETER Input High Voltage DIF_IN Input Low Voltage DIF_IN Input Common Mode Voltage - DIF_IN Input Amplitude - DIF_IN Input Slew Rate - DIF_IN Input Leakage Current Input Duty Cycle Input Jitter - Cycle to Cycle 1 2 SYMBOL VIHDIF VILDIF VCOM VSWING dv/dt I IN dtin J DIFIn CONDITIONS Differential inputs (single-ended measurement) Differential inputs (single-ended measurement) Common Mode Input Voltage Peak to Peak value Measured differentially VIN = VDD , VIN = GND Measurement from differential wavefrom Differential Measurement MIN 600 VSS - 300 300 300 0.4 -5 45 0 TYP 800 0 MAX 1150 300 1000 1450 8 5 55 125 UNITS NOTES mV mV mV mV V/ns uA % ps 1 1 1 1 1,2 1 1 1 Guaranteed by design and characterization, not 100% tested in production. Slew rate measured through Vswing min centered around differential zero IDTTM/ICSTM Four Output Differential Buffer for PCIe Gen 1 and Gen 2 ICS9DB403D REV L 10/07/09 5 ICS9DB403D Four Output Differential Buffer for PCIe for Gen 1 and Gen 2 Electrical Characteristics - Input/Supply/Common Output Parameters TA = Tambient for the desired operating range, Supply Voltage VDD = 3.3 V +/-5% PARAMETER SYMBOL CONDITIONS VIHSE Input High Voltage Single Ended Inputs, 3.3 V +/-5% VILSE Input Low Voltage IIHSE VIN = VDD Input High Current Input Low Current IIL1 IIL2 IDD3.3OPC 9DB803 Supply Current IDD3.3OPI 9DB803 Powerdown Current IDD3.3PDC IDD3.3PDI IDD3.3OPC 9DB403 Supply Current IDD3.3OPI 9DB403 Powerdown Current Input Frequency Pin Inductance Capacitance PLL Bandwidth PLL Jitter Peaking Clk Stabilization Input SS Modulation Frequency OE# Latency Tdrive_SRC_STOP# Tdrive_PD# IDD3.3PDC IDD3.3PDI FiPLL FiBYPASS Lpin CIN CINSRC_IN COUT BW tJPEAK TSTAB fMODIN tLATOE# tDRVSTP tDRVPD VIN = 0 V; Inputs with no pull-up resistors VIN = 0 V; Inputs with pull-up resistors Full Active, CL = Full load; Commerical Temp Range Full Active, CL = Full load; Industrial Temp Range all diff pairs driven, C-Temp all differential pairs tri-stated, C-Temp all diff pairs driven, I-temp all differential pairs tri-stated, I-temp Full Active, CL = Full load; Commerical Temp Range Full Active, CL = Full load; Industrial Temp Range all diff pairs driven, C-Temp all differential pairs tri-stated, C-Temp all diff pairs driven, I-Temp all differential pairs tri-stated, I-Temp PCIe Mode (Bypass#/PLL= 1) Bypass Mode ((Bypass#/PLL= 0) Logic Inputs, except SRC_IN SRC_IN differential clock inputs Output pin capacitance -3dB point in High BW Mode -3dB point in Low BW Mode Peak Pass band Gain From VDD Power-Up and after input clock stabilization or de-assertion of PD# to 1st clock Allowable Frequency (Triangular Modulation) DIF start after OE# assertion DIF stop after OE# deassertion DIF output enable after SRC_Stop# de-assertion DIF output enable after PD# de-assertion Fall time of PD# and SRC_STOP# Rise time of PD# and SRC_STOP# Maximum input voltage @ IPULLUP MIN 2 GND - 0.3 -5 -5 -200 175 190 50 4 55 6 105 115 25 2 30 3 100.00 200 225 60 6 65 8 125 150 30 3 35 4 110 400 7 5 2.7 6 4 1.4 2 1 30 1 33 3 10 300 5 5 5.5 0.4 4 1000 300 100 TYP MAX VDD + 0.3 0.8 5 UNITS NOTES V 1 V 1 uA 1 uA uA mA mA mA mA mA mA mA mA mA mA mA mA MHz MHz nH pF pF pF MHz MHz dB ms kHz cycles ns us ns ns V V mA ns ns kHz 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1,4 1 1 1 1 1,2 1 1,3 1,3 1,3 1 2 1 1 1 1 1 1,5 50 33 1.5 1.5 2 0.7 3 1 1.5 tF Tfall tR Trise VMAX SMBus Voltage VOL Low-level Output Voltage Current sinking at VOL IPULLUP SCLK/SDATA (Max VIL - 0.15) to tRSMB Clock/Data Rise Time (Min VIH + 0.15) (Min VIH + 0.15) to SCLK/SDATA tFSMB (Max VIL - 0.15) Clock/Data Fall Time SMBus Operating fMAXSMB Maximum SMBus operating frequency Frequency 1 Guaranteed by design and characterization, not 100% tested in production. 2 See timing diagrams for timing requirements. 3 Time from deassertion until outputs are >200 mV 4 SRC_IN input 5 The differential input clock must be running for the SMBus to be active IDTTM/ICSTM Four Output Differential Buffer for PCIe Gen 1 and Gen 2 ICS9DB403D REV L 10/07/09 6 ICS9DB403D Four Output Differential Buffer for PCIe for Gen 1 and Gen 2 Electrical Characteristics - DIF 0.7V Current Mode Differential Pair TA = Tambient; VDD = 3.3 V +/-5%; CL = 2pF, RS=33Ω, RP=49.9Ω, RREF=475Ω PARAMETER Current Source Output Impedance Voltage High Voltage Low Max Voltage Min Voltage Crossing Voltage (abs) Crossing Voltage (var) Rise Time Fall Time Rise Time Variation Fall Time Variation Duty Cycle Skew, Input to Output Skew, Output to Output Jitter, Cycle to cycle SYMBOL Zo1 VHigh VLow Vovs Vuds Vcross(abs) d-Vcross tr tf d-tr d-tf dt3 tpdBYP tpdPLL t sk3 tjcyc-cyc Statistical measurement on single ended signal using oscilloscope math function. Measurement on single ended signal using absolute value. Variation of crossing over all edges VOL = 0.175V, VOH = 0.525V VOH = 0.525V V OL = 0.175V CONDITIONS MIN 3000 660 -150 -300 250 850 mV 150 1150 550 140 175 175 700 700 125 125 55 4500 250 50 50 50 7 0 10 0.1 mV mV mV ps ps ps ps % ps ps ps ps ps ps (pk2pk) ps (rms) ps (rms) 1,2 1 1 1 1 1 1 1 1 1 1 1 1 1,3 1,3 1,4,5 1,4,5 TYP MAX UNITS NOTES Ω 1 1,2 Measurement from differential wavefrom Bypass Mode, VT = 50% PLL Mode VT = 50% VT = 50% PLL mode Additiv e J itter in By pass Mode PCIe Gen1 phase jitter (Additive in Bypass Mode) PCIe Gen 2 Low Band phase jitter (Additive in Bypass Mode) PCIe Gen 2 High Band phase jitter (Additive in Bypass Mode) PCIe Gen 1 phase jitter 45 2500 -250 tjphaseBYP Jitter, Phase 0.3 40 1.5 2.7/ 2.2 0.5 86 3 3.1 1,4,5 tjphasePLL PCIe Gen 2 Low Band phase jitter PCIe Gen 2 High Band phase jitter ps 1,4,5 (pk2pk) ps 1,4,5 (rms) ps 1,4,5,6 (rms) 1 2 Guaranteed by design and characterization, not 100% tested in production. IREF = VDD/(3xRR). For RR = 475Ω (1%), I REF = 2.32mA. I OH = 6 x I REF and V OH = 0.7V @ ZO=50Ω. 3 Measured from differential waveform 4 See http://www.pcisig.com for complete specs 5 Device driven by 932S421C or equivalent. 6 First number is High Bandwidth Mode, second number is Low Bandwidth Mode IDTTM/ICSTM Four Output Differential Buffer for PCIe Gen 1 and Gen 2 ICS9DB403D REV L 10/07/09 7 ICS9DB403D Four Output Differential Buffer for PCIe for Gen 1 and Gen 2 Clock Periods Differential Outputs with Spread Spectrum Enabled Measurement Window Symbol 1 Clock LgAbsolute Period Minimum Absolute Period 9.87400 7.41425 5.91440 4.91450 3.66463 2.91470 2.41475 1us -SSC Short-term Avera ge Minimum Absolute Period 9.99900 7.49925 5.99940 4.99950 3.74963 2.99970 2.49975 0.1s -ppm error Long-Term Avera ge Minimum Absolute Period 9.99900 7.49925 5.99940 4.99950 3.74963 2.99970 2.49975 0.1s 0ppm Period Nominal 10.00000 7.50000 6.00000 5.00000 3.75000 3.00000 2.50000 0.1s 1us + ppm error +SSC Long-Term Short-term Avera ge Avera ge Maximum 10.00100 7.50075 6.00060 5.00050 3.75038 3.00030 2.50025 Maximum 10.05130 7.53845 6.03076 5.02563 3.76922 3.01538 2.51282 1 Clock Lg+ Period Maximum 10.17630 7.62345 6.11576 5.11063 3.85422 3.10038 2.59782 Units ns ns ns ns ns ns ns Notes 1,2,3 1,2,4 1,2,4 1,2,4 1,2,4 1,2,4 1,2,4 Definition DIF 100 DIF 133 DIF 166 DIF 200 DIF 266 DIF 333 DIF 400 Clock Periods Differential Outputs with Spread Spectrum Disabled Measurement Window Symbol 1 Clock LgAbsolute Period Minimum Absolute Period 9.87400 7.41425 5.91440 4.91450 3.66463 2.91470 2.41475 1us -SSC Short-term Avera ge Minimum Absolute Period 0.1s -ppm error Long-Term Avera ge Minimum Absolute Period 9.99900 7.49925 5.99940 4.99950 3.74963 2.99970 2.49975 0.1s 0ppm Period Nominal 10.00000 7.50000 6.00000 5.00000 3.75000 3.00000 2.50000 0.1s 1us + ppm error +SSC Long-Term Short-term Avera ge Avera ge Maximum 10.00100 7.50075 6.00060 5.00050 3.75038 3.00030 2.50025 Maximum 1 Clock Lg+ Period Maximum 10.17630 7.62345 6.11576 5.11063 3.85422 3.10038 2.59782 Units ns ns ns ns ns ns ns Notes 1,2,3 1,2,4 1,2,4 1,2,4 1,2,4 1,2,4 1,2,4 Signal Name 1 2 3 4 Definition DIF 100 DIF 133 DIF 166 DIF 200 DIF 266 DIF 333 DIF 400 Guaranteed by design and characterization, not 100% tested in production. All Long Term Accuracy specifications are guaranteed with the assumption that the input clock complies with CK409/CK410/CK505 accuracy requirements. The 9DB403/803 itself does not contribute to ppm error. Driven by SRC output of main clock, PLL or Bypass mode Driven by CPU output of CK410/CK505 main clock, Bypass mode only IDTTM/ICSTM Four Output Differential Buffer for PCIe Gen 1 and Gen 2 Signal Name ICS9DB403D REV L 10/07/09 8 ICS9DB403D Four Output Differential Buffer for PCIe for Gen 1 and Gen 2 SRC Reference Clock Common Recommendations for Differential Routing Dimension or Value L1 length, Route as non-coupled 50 ohm trace. 0.5 max L2 length, Route as non-coupled 50 ohm trace. 0.2 max L3 length, Route as non-coupled 50 ohm trace. 0.2 max Rs 33 Rt 49.9 Down Device Differential Routing L4 length, Route as coupled microstrip 100 ohm differential trace. L4 length, Route as coupled stripline 100 ohm differential trace. Differential Routing to PCI Express Connector L4 length, Route as coupled microstrip 100 ohm differential trace. L4 length, Route as coupled stripline 100 ohm differential trace. Dimension or Value 2 min to 16 max 1.8 min to 14.4 max Dimension or Value 0.25 to 14 max 0.225 min to 12.6 max Unit inch inch inch ohm ohm Unit inch inch Unit inch inch Figure 1 1 1 1 1 Figure 1 1 Figure 2 2 Figure 1 Down device routing. L1 Rs L1’ Rs HSCL Output Buffer L2 L2’ Rt L3’ Rt L3 L4 L4’ PCI Ex Board Down Device REF_CLK Input Figure 1 Figure 2 PCI Express Connector Routing. L1 L1’ Rs L2 L2’ L4 L4’ Rt L3’ Rt L3 PCI Ex Add In Board REF_CLK Input Rs HSCL Output Buffer Figure 2 IDTTM/ICSTM Four Output Differential Buffer for PCIe Gen 1 and Gen 2 ICS9DB403D REV L 10/07/09 9 ICS9DB403D Four Output Differential Buffer for PCIe for Gen 1 and Gen 2 Alternative termination for LVDS and other common differential signals. Figure 3. Vdiff Vp-p 0.45 v 0.22v 0.58 0.28 0.80 0.40 0.60 0.3 R1a = R1b = R1 Figure_3. Vcm 1.08 0.6 0.6 1.2 R1 33 33 33 33 R2 150 78.7 78.7 174 R3 100 137 none 140 R4 100 100 100 100 Note ICS874003i-02 input compatible Standard LVDS L1 L1’ R1a L2 L2’ R3 L4 L4’ R4 R1b HSCL Output Buffer R2a L3’ R2b L3 Down Device REF_CLK Input R2a = R2b = R2 Cable connected AC coupled application, figure 4 Component R5a,R5b R6a,R6b Cc Vcm Value 8.2K 5% 1K 5% 0.1 uF 0.350 volts Note 3.3 Volts R5a L4 L4’ Cc Cc R5b R6a R6b PCIe Device REF_CLK Input Figure_4. IDTTM/ICSTM Four Output Differential Buffer for PCIe Gen 1 and Gen 2 ICS9DB403D REV L 10/07/09 10 ICS9DB403D Four Output Differential Buffer for PCIe for Gen 1 and Gen 2 General SMBus serial interface information for the ICS9DB403D How to Write: Controller (host) sends a start bit. Controller (host) sends the write address DC (h) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) sends the data byte count = X ICS clock will acknowledge Controller (host) starts sending Byte N through Byte N + X -1 • ICS clock will acknowledge each byte one at a time • Controller (host) sends a Stop bit • • • • • • • • How to Read: • • • • • • • • • • • • • • Controller (host) will send start bit. Controller (host) sends the write address DC (h) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) will send a separate start bit. Controller (host) sends the read address DD (h) ICS clock will acknowledge ICS clock will send the data byte count = X ICS clock sends Byte N + X -1 ICS clock sends Byte 0 through byte X (if X(h) was written to byte 8). Controller (host) will need to acknowledge each byte Controllor (host) will send a not acknowledge bit Controller (host) will send a stop bit Index Block Write Operation Controller (Host) starT bit T Slave Address DC(h) WRite WR Beginning Byte = N ACK Data Byte Count = X ACK Beginning Byte N ACK X Byte ICS (Slave/Receiver) Index Block Read Operation Controller (Host) T starT bit Slave Address DC(h) WR WRite Beginning Byte = N ACK RT Repeat starT Slave Address DD(h) RD ReaD ACK Data Byte Count = X ACK Beginning Byte N X Byte ACK ICS (Slave/Receiver) ACK ACK Byte N + X - 1 ACK P stoP bit Byte N + X - 1 N P IDTTM/ICSTM Four Output Differential Buffer for PCIe Gen 1 and Gen 2 Not acknowledge stoP bit ICS9DB403D REV L 10/07/09 11 ICS9DB403D Four Output Differential Buffer for PCIe for Gen 1 and Gen 2 SMBus Table: Frequency Select Register, READ/WRITE ADDRESS (DC/DD) Pin # Name Control Function Type Byte 0 PD_Mode PD# drive mode RW Bit 7 STOP_Mode SRC_Stop# drive mode RW Bit 6 PD_Polarity Select PD polarity RW Bit 5 Reserved Reserved RW Bit 4 Reserved Reserved RW Bit 3 PLL_BW# Select PLL BW RW Bit 2 BYPASS# BYPASS#/PLL RW Bit 1 SRC_DIV# SRC Divide by 2 Select RW Bit 0 0 1 driven Hi-Z driven Hi-Z Low High Reserved Reserved High B W Low BW fan-out ZDB x/2 1x Default 0 0 0 X X 1 1 1 SMBus Table: Output Control Register Byte 1 Pin # Name Control Function Type 0 1 Default Reserved Reserved Reserved RW 1 Bit 7 22,23 DIF_6 Output Enable RW Disable Enable 1 Bit 6 19,20 DIF_5 Output Enable RW Disable Enable 1 Bit 5 Reserved Reserved RW 1 Reserved Bit 4 Reserved Reserved RW 1 Reserved Bit 3 9,10 DIF_2 Output Enable RW Disable Enable 1 Bit 2 DIF_1 Output Enable RW Disable Enable 1 6,7 Bit 1 Reserved Reserved RW 1 Reserved Bit 0 NOTE: The SMBus Output Enable Bit must be '1' AND the respective OE pin must be active for the output to run! SMBus Table: OE Pin Byte 2 Pin # Bit 7 22,23 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 6,7 Bit 1 Bit 0 Control Register Name Reserved DIF_6 Reserved Reserved Reserved Reserved DIF_1 Reserved Control Function Reserved DIF_6 Stoppable with OE6 Reserved Reserved Reserved Reserved DIF_1 Stoppable with OE1 Reserved Type RW RW RW RW RW RW RW RW 1 Default 0 Reserved Free-run Stoppable 0 0 Reserved 0 Reserved 0 Reserved 0 Reserved Free-run Stoppable 0 0 Reserved 0 SMBus Table: Reserved Register Pin # Name Byte 3 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Control Function Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Type 0 1 Default X X X X X X X X IDTTM/ICSTM Four Output Differential Buffer for PCIe Gen 1 and Gen 2 ICS9DB403D REV L 10/07/09 12 ICS9DB403D Four Output Differential Buffer for PCIe for Gen 1 and Gen 2 SMBus Table: Vendor & Revision ID Register Pin # Name Control Function Byte 4 RID3 Bit 7 RID2 Bit 6 REVISION ID RID1 Bit 5 RID0 Bit 4 VID3 Bit 3 VID2 Bit 2 VENDOR ID VID1 Bit 1 VID0 Bit 0 SMBus Table: DEVICE ID Byte 5 Pin # Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SMBus Table: Byte Count Register Byte 6 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Name BC7 BC6 BC5 BC4 BC3 BC2 BC1 BC0 Control Function Type R R R R R R R R 0 - 1 - Default 0 0 1 1 0 0 0 1 Control Function Device ID 7 (MSB) Device ID 6 Device ID 5 Device ID 4 Device ID 3 Device ID 2 Device ID 1 Device ID 0 Type RW RW RW RW RW RW RW RW 0 1 Device ID is 83 Hex for 9DB803 and 43 Hex for 9DB403 Default 0 X X 0 0 0 1 1 Type RW RW RW RW RW RW RW RW 0 - 1 - Default 0 0 0 0 0 1 1 1 Writing to this register configures how many bytes will be read back. IDTTM/ICSTM Four Output Differential Buffer for PCIe Gen 1 and Gen 2 ICS9DB403D REV L 10/07/09 13 ICS9DB403D Four Output Differential Buffer for PCIe for Gen 1 and Gen 2 Note: Polarities in timing diagrams are shown OE_INV = 0. They are similar to OE_INV = 1. PD#, Power Down The PD# pin cleanly shuts off all clocks and places the device into a power saving mode. PD# must be asserted before shutting off the input clock or power to insure an orderly shutdown. PD is asynchronous active-low input for both powering down the device and powering up the device. When PD# is asserted, all clocks will be driven high, or tri-stated (depending on the PD# drive mode and Output control bits) before the PLL is shut down. PD# Assertion When PD# is sampled low by two consecutive rising edges of DIF#, all DIF outputs must be held High, or tri-stated (depending on the PD# drive mode and Output control bits) on the next High-Low transition of the DIF# outputs. When the PD# drive mode bit is set to ‘0’, all clock outputs will be held with DIF driven High with 2 x IREF and DIF# tri-stated. If the PD# drive mode bit is set to ‘1’, both DIF and DIF# are tri-stated. PWRDWN# DIF DIF# PD# De-assertion Power-up latency is less than 1 ms. This is the time from de-assertion of the PD# pin, or VDD reaching 3.3V, or the time from valid SRC_IN clocks until the time that stable clocks are output from the device (PLL Locked). If the PD# drive mode bit is set to ‘1’, all the DIF outputs must driven to a voltage of >200 mV within 300 us of PD# de-assertion. Tstable 200 mV) within 10 ns of de-assertion. SRC_STOP_1 (SRC_Stop = Driven, PD = Driven) 1mS SRC_Stop# PWRDWN# DIF (Free Running) DIF# (Free Running) DIF (Stoppable) DIF# (Stoppable) SRC_STOP_2 (SRC_Stop =Tristate, PD = Driven) 1mS SRC_Stop# PWRDWN# DIF (Free Running) DIF# (Free Running) DIF (Stoppable) DIF# (Stoppable) IDTTM/ICSTM Four Output Differential Buffer for PCIe Gen 1 and Gen 2 ICS9DB403D REV L 10/07/09 15 ICS9DB403D Four Output Differential Buffer for PCIe for Gen 1 and Gen 2 SRC_STOP_3 (SRC_Stop = Driven, PD = Tristate) 1mS SRC_Stop# PWRDWN# DIF (Free Running) DIF# (Free Running) DIF (Stoppable) DIF# (Stoppable) SRC_STOP_4 (SRC_Stop = Tristate, PD = Tristate) 1mS SRC_Stop# PWRDWN# DIF (Free Running) DIF# (Free Running) DIF (Stoppable) DIF# (Stoppable) IDTTM/ICSTM Four Output Differential Buffer for PCIe Gen 1 and Gen 2 ICS9DB403D REV L 10/07/09 16 ICS9DB403D Four Output Differential Buffer for PCIe for Gen 1 and Gen 2 28-pin SSOP Package Dimensions 209 mil SSOP SYMBOL A A1 A2 b c D E E1 e L N α VARIATIONS D (inch) 28 MIN 9.90 MAX 10.50 MIN .390 MAX .413 In Millimeters COMMON DIMENSIONS MIN MAX -2.00 0.05 -1.65 1.85 0.22 0.38 0.09 0.25 SEE VARIATIONS 7.40 8.20 5.00 5.60 0.65 BASIC 0.55 0.95 0° 8° In Inches COMMON DIMENSIONS MIN MAX -.079 .002 -.065 .073 .009 .015 .0035 .010 SEE VARIATIONS .291 .323 .197 .220 0.0256 BASIC .022 .037 0° 8° Reference Doc.: JEDEC Publication 95, MO-150 209 mil SSOP 10-0033 IDTTM/ICSTM Four Output Differential Buffer for PCIe Gen 1 and Gen 2 ICS9DB403D REV L 10/07/09 17 ICS9DB403D Four Output Differential Buffer for PCIe for Gen 1 and Gen 2 28-pin TSSOP Package Dimensions N c 4.40 mm. Body, 0.65 mm. Pitch TSSOP (173 mil) L (25.6 mil) In Inches COMMON DIMENSIONS MIN MAX -.047 .002 .006 .032 .041 .007 .012 .0035 .008 SEE VARIATIONS 0.252 BASIC .169 .177 0.0256 BASIC .018 .030 SEE VARIATIONS 0° 8° -.004 SYMBOL A A1 A2 b c D E E1 e L N α aaa VARIATIONS N 28 INDEX AREA E1 E 12 D a A2 A1 A In Millimeters COMMON DIMENSIONS MIN MAX -1.20 0.05 0.15 0.80 1.05 0.19 0.30 0.09 0.20 SEE VARIATIONS 6.40 BASIC 4.30 4.50 0.65 BASIC 0.45 0.75 SEE VARIATIONS 0° 8° -0.10 -Ce b SEATING PLANE D mm. MIN 9.60 MAX 9.80 MIN .378 D (inch) MAX .386 aaa C Reference Doc.: JEDEC Publication 95, MO-153 10-0035 Ordering Information Part / Order Number 9DB403DGLF 9DB403DGLFT 9DB403DGILF 9DB403DGILFT 9DB403DFLF 9DB403DFLFT 9DB403DFILF 9DB403DFILFT Marking 9DB403DGLF 9DB403DGLF 9DB403DGILF 9DB403DGILF 9DB403DFLF 9DB403DFLF 9DB403DFILF 9DB403DFILF Shipping Packaging Tubes Tape and Reel Tubes Tape and Reel Tubes Tape and Reel Tubes Tape and Reel Package 28-pin TSSOP 28-pin TSSOP 28-pin TSSOP 28-pin TSSOP 28-pin SSOP 28-pin SSOP 28-pin SSOP 28-pin SSOP Temperature 0 to +70° C 0 to +70° C -40 to +85° C -40 to +85° C 0 to +70° C 0 to +70° C -40 to +85° C -40 to +85° C "LF" denotes Pb-free package, RoHS compliant "D" is the revision designator (will not correlate to datasheet revision) IDTTM/ICSTM Four Output Differential Buffer for PCIe Gen 1 and Gen 2 ICS9DB403D REV L 10/07/09 18 ICS9DB403D Four Output Differential Buffer for PCIe Gen 1 and Gen 2 Revision History Rev. A B Issue Date Description 1. Updated electrical characteristics for final data sheet 8/15/2006 2. Corrected references to 8 outputs (should be 4) 5/22/2007 Updated Polarity Inversion Table. 1. Corrected SMBus table to eliminate non-existant outputs. This effects bytes 1 and 2. 1/16/2008 2. Changed PWD notation to Default in SMBus descriptions 2/29/2008 Added Input Clock Specs 3/18/2008 Fixed ty po in Input Clock Parameters 4/9/2008 Updated Input Clock Specs 8/19/2008 Corrected typos on Bytes 1 and 2. 1. Updated Electrical Characteristics to add propagation delay and phase noise information. 2. Corrected SMBus to reference pin numbers for 403 instead of 803 device. 3. Removed references to OE controls that are not present on 403. 4. Added SMBus electrical characteristics 5. Added foot note about DIF input running in order for the SMBus interface to work 6. Added foot note to Byte 1 about functionality of OE bits and OE pins. 8/26/2008 7. Corrected Block Diagram with proper OE pins indicated. 11/26/2008 Updated SMBus table - By te0:B yte3. 2/6/2009 Added Industrial temp. specs and ordering information. 7/13/2009 Updated general description and block diagram 1. Clarified that Vih and Vil values were for Single ended inputs 2. Added separate Idd values for the 9DB403 10/7/2009 3. Added Differential Clock input parameters. Page # 2 C D E F G 11 6 6 6 11 H I J K Various 11 Various 1 L Various Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 For Tech Support 408-284-6578 pcclockhelp@idt.com Corporate Headquarters Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.) Asia Pacific and Japan Integrated Device Technology Singapore (1997) Pte. Ltd. Reg. No. 199707558G 435 Orchard Road #20-03 Wisma Atria Singapore 238877 +65 6 887 5505 Europe IDT Europe, Limited Prime House Barnett Wood Lane Leatherhead, Surrey United Kingdom KT22 7DE +44 1372 363 339 TM © 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA 19