DATASHEET
ICS9DB803D
EIGHT OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1 AND GEN2
General Description
Features/Benefits
The ICS9DB803D is compatible with the Intel DB800v2
Differential Buffer Specification. This buffer provides 8
PCI-Express Gen2 clocks. The ICS9DB803D is driven by a
differential output pair from a CK410B+, CK505 or CK509B
main clock generator.
• Spread spectrum modulation tolerant, 0 to -0.5% down
• Supports undriven differential outputs in PD# and
SRC_STOP# modes for power management
Key Specifications
Recommended Application
DB800v2 compatible part with PCIe Gen1 and Gen2
Support
Output Features
•
•
•
•
•
spread and +/- 0.25% center spread
•
•
•
•
Outputs cycle-cycle jitter < 50ps
Output to Output skew 200 mV
4
SRC_IN input
5
The differential input clock must be running for the SMBus to be active
IDT® EIGHT OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1 AND GEN2
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Electrical Characteristics–DIF 0.7V Current Mode Differential Pair
TA =Tambient; VDD = 3.3 V +/-5%; CL =2pF, RS=33Ω, RP=49.9Ω, RREF=475Ω
PARAMETER
SYMBOL
Current Source Output
Impedance
Zo1
Voltage High
VHigh
Voltage Low
VLow
Max Voltage
Min Voltage
Crossing Voltage (abs)
Vovs
Vuds
Vcross(abs)
Crossing Voltage (var)
d-Vcross
Rise Time
Fall Time
Rise Time Variation
Fall Time Variation
tr
tf
d-tr
d-tf
Duty Cycle
dt3
Skew, Output to Output
tpdBYP
tpdPLL
tsk3
Jitter, Cycle to cycle
tjcyc-cyc
Skew, Input to Output
tjphaseBYP
Jitter, Phase
t jphasePLL
CONDITIONS
MIN
TYP
MAX
Ω
3000
Statistical measurement on single
ended signal using oscilloscope
math function.
Measurement on single ended
signal using absolute value.
660
850
1
1,2
mV
-150
150
1150
1,2
550
mV
1
1
1
140
mV
1
175
175
700
700
125
125
ps
ps
ps
ps
1
1
1
1
45
55
%
1
2500
-250
4500
250
50
50
50
ps
ps
ps
ps
ps
ps
(pk2pk)
1
1
1
1,3
1,3
-300
250
Variation of crossing over all
edges
VOL = 0.175V, VOH = 0.525V
VOH = 0.525V VOL = 0.175V
Measurement from differential
wavefrom
Bypass Mode, VT = 50%
PLL Mode VT = 50%
VT = 50%
PLL mode
Additive Jitter in Bypass Mode
PCIe Gen1 phase jitter
(Additive in Bypass Mode)
UNITS NOTES
mV
7
10
1,4,5
PCIe Gen 2 Low Band phase jitter
(Additive in Bypass Mode)
0
0.1
ps
(rms)
1,4,5
PCIe Gen 2 High Band phase jitter
(Additive in Bypass Mode)
0.3
0.5
ps
(rms)
1,4,5
PCIe Gen 1 phase jitter
40
86
PCIe Gen 2 Low Band phase jitter
1.5
3
PCIe Gen 2 High Band phase jitter
2.7/
2.2
3.1
ps
1,4,5
(pk2pk)
ps
1,4,5
(rms)
ps
1,4,5,6
(rms)
1
Guaranteed by design and characterization, not 100% tested in production.
IREF = VDD/(3xRR). For RR = 475Ω (1%), IREF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ ZO=50Ω.
3 Measured from differential waveform
4
See http://www.pcisig.com for complete specs
5
Device driven by 932S421C or equivalent.
6
First number is High Bandwidth Mode, second number is Low Bandwidth Mode
2
IDT® EIGHT OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1 AND GEN2
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EIGHT OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1 AND GEN2
Clock Periods–Differential Outputs with Spread Spectrum Enabled
Measurement
Window
Symbol
Signal Name
Definition
DIF 100
DIF 133
DIF 166
DIF 200
DIF 266
DIF 333
DIF 400
1 Clock
LgAbsolute
Period
Minimum
Absolute
Period
9.87400
7.41425
5.91440
4.91450
3.66463
2.91470
2.41475
1us
-SSC
Short-term
Average
Minimum
Absolute
Period
9.99900
7.49925
5.99940
4.99950
3.74963
2.99970
2.49975
0.1s
-ppm error
Long-Term
Average
Minimum
Absolute
Period
9.99900
7.49925
5.99940
4.99950
3.74963
2.99970
2.49975
0.1s
0ppm
Period
0.1s
1us
+ ppm error
+SSC
Long-Term Short-term
Average
Average
1 Clock
Lg+
Period
Nominal
Maximum
Maximum
Maximum
10.00000
7.50000
6.00000
5.00000
3.75000
3.00000
2.50000
10.00100
7.50075
6.00060
5.00050
3.75038
3.00030
2.50025
10.05130
7.53845
6.03076
5.02563
3.76922
3.01538
2.51282
10.17630
7.62345
6.11576
5.11063
3.85422
3.10038
2.59782
Units
ns
ns
ns
ns
ns
ns
ns
Notes
1,2,3
1,2,4
1,2,4
1,2,4
1,2,4
1,2,4
1,2,4
Units
ns
ns
ns
ns
ns
ns
ns
Notes
1,2,3
1,2,4
1,2,4
1,2,4
1,2,4
1,2,4
1,2,4
Clock Periods–Differential Outputs with Spread Spectrum Disabled
Measurement
Window
Symbol
Signal Name
Definition
DIF 100
DIF 133
DIF 166
DIF 200
DIF 266
DIF 333
DIF 400
1 Clock
LgAbsolute
Period
Minimum
Absolute
Period
9.87400
7.41425
5.91440
4.91450
3.66463
2.91470
2.41475
1us
-SSC
Short-term
Average
Minimum
Absolute
Period
0.1s
-ppm error
Long-Term
Average
Minimum
Absolute
Period
9.99900
7.49925
5.99940
4.99950
3.74963
2.99970
2.49975
0.1s
0ppm
Period
0.1s
1us
+ ppm error
+SSC
Long-Term Short-term
Average
Average
Nominal
Maximum
10.00000
7.50000
6.00000
5.00000
3.75000
3.00000
2.50000
10.00100
7.50075
6.00060
5.00050
3.75038
3.00030
2.50025
Maximum
1 Clock
Lg+
Period
Maximum
10.17630
7.62345
6.11576
5.11063
3.85422
3.10038
2.59782
1
Guaranteed by design and characterization, not 100% tested in production.
2
All Long Term Accuracy specifications are guaranteed with the assumption that the input clock complies with
CK409/CK410/CK505 accuracy requirements. The 9DB403/803 itself does not contribute to ppm error.
3
4
Driven by SRC output of main clock, PLL or Bypass mode
Driven by CPU output of CK410/CK505 main clock, Bypass mode only
IDT® EIGHT OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1 AND GEN2
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SRC Reference Clock
Common Recommendations for Differential Routing
Dimension or Value
L1 length, route as non-coupled 50ohm trace
0.5 max
L2 length, route as non-coupled 50ohm trace
0.2 max
L3 length, route as non-coupled 50ohm trace
0.2 max
Rs
33
Rt
49.9
Unit
inch
inch
inch
ohm
ohm
Figure
1
1
1
1
1
Down Device Differential Routing
L4 length, route as coupled microstrip 100ohm differential trace 2 min to 16 max
L4 length, route as coupled stripline 100ohm differential trace
1.8 min to 14.4 max
inch
inch
1
1
Differential Routing to PCI Express Connector
L4 length, route as coupled microstrip 100ohm differential trace 0.25 to 14 max
L4 length, route as coupled stripline 100ohm differential trace
0.225 min to 12.6 max
inch
inch
2
2
Figure 1: Down Device Routing
L2
L1
Rs
L4
L4'
L2'
L1'
Rs
HCSL Output Buffer
Rt
Rt
L3'
PCI Express
Down Device
REF_CLK Input
L3
Figure 2: PCI Express Connector Routing
L2
L1
Rs
L4
L4'
L2'
L1'
HCSL Output Buffer
Rs
Rt
Rt
L3'
IDT® EIGHT OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1 AND GEN2
PCI Express
Add-in Board
REF_CLK Input
L3
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EIGHT OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1 AND GEN2
Alternative Termination for LVDS and other Common Differential Signals (figure 3)
Vdiff
Vp-p
Vcm
R1
R2
R3
R4
Note
0.45v
0.22v
1.08
33
150
100
100
0.58
0.28
0.6
33
78.7
137
100
0.80
0.40
0.6
33
78.7
none
100
ICS874003i-02 input compatible
0.60
0.3
1.2
33
174
140
100
Standard LVDS
R1a = R1b = R1
R2a = R2b = R2
Figure 3
L2
L1
R3
R1a
L4
R4
L4'
L2'
L1'
R1b
HCSL Output Buffer
R2a
R2b
L3'
Down Device
REF_CLK Input
L3
Cable Connected AC Coupled Application (figure 4)
Component
Value
Note
R5a, R5b
8.2K 5%
R6a, R6b
1K 5%
Cc
0.1 µF
Vcm
0.350 volts
Figure 4
3.3 Volts
R5a
R5b
R6a
R6b
Cc
L4
L4'
Cc
IDT® EIGHT OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1 AND GEN2
PCIe Device
REF_CLK Input
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EIGHT OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1 AND GEN2
General SMBus Serial Interface Information
How to Write
How to Read
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Controller (host) sends a start bit
Controller (host) sends the write address
IDT clock will acknowledge
Controller (host) sends the beginning byte location = N
IDT clock will acknowledge
Controller (host) sends the byte count = X
IDT clock will acknowledge
Controller (host) starts sending Byte N through Byte
N+X-1
IDT clock will acknowledge each byte one at a time
Controller (host) sends a Stop bit
Index Block Write Operation
Controller (Host)
T
Index Block Read Operation
IDT (Slave/Receiver)
Controller (Host)
starT bit
T
Slave Address
WR
•
•
•
Controller (host) will send a start bit
Controller (host) sends the write address
IDT clock will acknowledge
Controller (host) sends the beginning byte location = N
IDT clock will acknowledge
Controller (host) will send a separate start bit
Controller (host) sends the read address
IDT clock will acknowledge
IDT clock will send the data byte count = X
IDT clock sends Byte N+X-1
IDT clock sends Byte 0 through Byte X (if X(H) was
written to Byte 8)
Controller (host) will need to acknowledge each byte
Controller (host) will send a not acknowledge bit
Controller (host) will send a stop bit
IDT (Slave/Receiver)
starT bit
Slave Address
WRite
ACK
WR
WRite
ACK
Beginning Byte = N
ACK
Beginning Byte = N
ACK
Data Byte Count = X
ACK
RT
Slave Address
Beginning Byte N
ACK
O
O
RD
ReaD
ACK
X Byte
O
Repeat starT
O
Data Byte Count=X
O
O
ACK
ACK
ACK
Beginning Byte N
Byte N + X - 1
stoP bit
O
X Byte
P
O
O
O
O
O
Read Address
Write Address
DD(H)
DC(H)
IDT® EIGHT OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1 AND GEN2
Byte N + X - 1
N
Not acknowledge
P
stoP bit
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EIGHT OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1 AND GEN2
SMBus Table: Frequency Select Register, READ/WRITE ADDRESS (DC/DD)
Byte 0
Pin #
Name
Control Function
Type
PD_Mode
PD# drive mode
RW
Bit 7
STOP_Mode
DIF_Stop# drive mode
RW
Bit 6
Reserved
Reserved
RW
Bit 5
Reserved
Reserved
RW
Bit 4
Reserved
Reserved
RW
Bit 3
PLL_BW#
Select PLL BW
RW
Bit 2
BYPASS#
BYPASS#/PLL
RW
Bit 1
SRC_DIV#
SRC Divide by 2 Select
RW
Bit 0
0
1
driven
Hi-Z
driven
Hi-Z
Reserved
Reserved
Reserved
High BW Low BW
fan-out
ZDB
x/2
1x
SMBus Table: Output Control Register
Byte 1
Pin #
Name
DIF_7
Bit 7
DIF_6
Bit 6
DIF_5
Bit 5
DIF_4
Bit 4
DIF_3
Bit 3
DIF_2
Bit 2
DIF_1
Bit 1
DIF_0
Bit 0
Control Function
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Disable
SMBus Table: OE Pin Control Register
Byte 2
Pin #
Name
DIF_7
Bit 7
DIF_6
Bit 6
DIF_5
Bit 5
DIF_4
Bit 4
DIF_3
Bit 3
DIF_2
Bit 2
DIF_1
Bit 1
DIF_0
Bit 0
Control Register
Control Function
DIF_7 Stoppable with DIFSTOP
DIF_6 Stoppable with DIFSTOP
DIF_5 Stoppable with DIFSTOP
DIF_4 Stoppable with DIFSTOP
DIF_3 Stoppable with DIFSTOP
DIF_2 Stoppable with DIFSTOP
DIF_1 Stoppable with DIFSTOP
DIF_0 Stoppable with DIFSTOP
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
Free-run
Free-run
Free-run
Free-run
Free-run
Free-run
Free-run
Free-run
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
SMBus Table: Reserved Register
Byte 3
Pin #
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Control Function
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
IDT® EIGHT OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1 AND GEN2
14
1
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
PWD
0
0
X
X
X
1
1
1
PWD
1
1
1
1
1
1
1
1
1
PWD
Stoppable
0
Stoppable
0
Stoppable
0
Stoppable
0
Stoppable
0
Stoppable
0
Stoppable
0
Stoppable
0
1
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
ICS9DB803D
PWD
X
X
X
X
X
X
X
X
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EIGHT OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1 AND GEN2
SMBus Table: Vendor & Revision ID Register
Byte 4
Pin #
Name
Control Function
RID3
Bit 7
RID2
Bit 6
REVISION ID
RID1
Bit 5
RID0
Bit 4
VID3
Bit 3
VID2
Bit 2
VENDOR ID
VID1
Bit 1
VID0
Bit 0
Type
R
R
R
R
R
R
R
R
0
-
1
-
PWD
X
X
X
X
0
0
0
1
SMBus Table: DEVICE ID
Byte 5
Pin #
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
1
PWD
0
X
X
0
0
0
1
1
Control Function
Device ID 7 (MSB)
Device ID 6
Device ID 5
Device ID 4
Device ID 3
Device ID 2
Device ID 1
Device ID 0
Device ID is 83 Hex
for 9DB803 and 43
Hex for 9DB403
SMBus Table: Byte Count Register
Byte 6
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
-
Name
BC7
BC6
BC5
BC4
BC3
BC2
BC1
BC0
Control
Function
Type
0
1
PWD
Writing to this register configures how
many bytes will be read back.
RW
RW
RW
RW
RW
RW
RW
RW
-
-
0
0
0
0
0
1
1
1
IDT® EIGHT OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1 AND GEN2
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Note: Polarities in timing diagrams are shown OE_INV = 0. They are similar to OE_INV = 1.
PD#, Power Down
The PD# pin cleanly shuts off all clocks and places the device into a power saving mode. PD# must be asserted before
shutting off the input clock or power to insure an orderly shutdown. PD is asynchronous active-low input for both powering
down the device and powering up the device. When PD# is asserted, all clocks will be driven high, or tri-stated (depending
on the PD# drive mode and Output control bits) before the PLL is shut down.
PD# Assertion
When PD# is sampled low by two consecutive rising edges of DIF#, all DIF outputs must be held High, or tri-stated
(depending on the PD# drive mode and Output control bits) on the next High-Low transition of the DIF# outputs. When the
PD# drive mode bit is set to ‘0’, all clock outputs will be held with DIF driven High with 2 x IREF and DIF# tri-stated. If the
PD# drive mode bit is set to ‘1’, both DIF and DIF# are tri-stated.
PD# De-assertion
Power-up latency is less than 1 ms. This is the time from de-assertion of the PD# pin, or VDD reaching 3.3V, or the time from
valid SRC_IN clocks until the time that stable clocks are output from the device (PLL Locked). If the PD# drive mode bit is
set to ‘1’, all the DIF outputs must driven to a voltage of >200 mV within 300 us of PD# de-assertion.
IDT® EIGHT OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1 AND GEN2
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SRC_STOP#
The SRC_STOP# signal is an active-low asynchronous input that cleanly stops and starts the DIF outputs. A valid clock must
be present on SRC_IN for this input to work properly. The SRC_STOP# signal is de-bounced and must remain stable for two
consecutive rising edges of DIF# to be recognized as a valid assertion or de-assertion.
SRC_STOP# - Assertion
Asserting SRC_STOP# causes all DIF outputs to stop after their next transition (if the control register settings allow the
output to stop). When the SRC_STOP# drive bit is ‘0’, the final state of all stopped DIF outputs is DIF = High and DIF# =
Low. There is no change in output drive current. DIF is driven with 6xIREF. DIF# is not driven, but pulled low by the
termination. When the SRC_STOP# drive bit is ‘1’, the final state of all DIF output pins is Low. Both DIF and DIF# are not
driven.
SRC_STOP# - De-assertion (transition from '0' to '1')
All stopped differential outputs resume normal operation in a glitch-free manner. The de-assertion latency to active outputs
is 2-6 DIF clock periods, with all DIF outputs resuming simultaneously. If the SRC_STOP# drive control bit is ‘1’ (tri-state),
all stopped DIF outputs must be driven High (>200 mV) within 10 ns of de-assertion.
SRC_STOP_1 (SRC_Stop = Driven, PD = Driven)
SRC_STOP_2 (SRC_Stop =Tristate, PD = Driven)
IDT® EIGHT OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1 AND GEN2
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SRC_STOP_3 (SRC_Stop = Driven, PD = Tristate)
SRC_STOP_4 (SRC_Stop = Tristate, PD = Tristate)
IDT® EIGHT OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1 AND GEN2
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Package Outline and Package Dimensions (48-pin TSSOP)
Package dimensions are kept current with JEDEC Publication No. 95
48
Millimeters
Symbol
E1
INDEX
AREA
E
1 2
D
A
A2
Min
A
A1
A2
b
c
D
E
E1
e
L
aaa
Max
-1.20
0.05
0.15
0.80
1.05
0.17
0.27
0.09
0.20
12.40
12.60
8.10 BASIC
6.00
6.20
0.50 Basic
0.45
0.75
0
8
-0.10
Inches*
Min
Max
-0.047
0.002
0.006
0.032
0.041
0.007
0.011
0.0035 0.008
0.488
0.496
0.319 BASIC
0.236
0.244
0.020 Basic
0.018
0.030
0
8
-0.004
*For reference only. Controlling dimensions in mm.
A1
c
- Ce
b
SEATING
PLANE
L
aaa C
IDT® EIGHT OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1 AND GEN2
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EIGHT OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1 AND GEN2
Package Outline and Package Dimensions (48-pin SSOP)
Package dimensions are kept current with JEDEC Publication No. 95
48
Millimeters
Symbol
E1
INDEX
AREA
E
1 2
D
A
A2
Min
A
A1
b
c
D
E
E1
e
h
L
Inches*
Max
Min
2.41
2.80
0.20
0.40
0.20
0.34
0.13
0.25
15.75
16.00
10.03
10.68
7.40
7.60
0.635 BASIC
0.38
0.64
0.50
1.02
0
8
Max
.095
.110
.008
.016
.008
.0135
.005
.010
.620
.630
.395
.420
.291
.299
0.025 BASIC
.015
.025
.020
.040
0
8
*For reference only. Controlling dimensions in mm.
A1
c
- Ce
b
SEATING
PLANE
L
aaa C
Ordering Information
Part / Order Number
9DB803DGLF
9DB803DGLFT
9DB803DGILF
9DB803DGILFT
9DB803DFLF
9DB803DFLFT
9DB803DFILF
9DB803DFILFT
Marking
9DB803DGLF
9DB803DGLF
9DB803DGILF
9DB803DGILF
9DB803DFLF
9DB803DFLF
9DB803DFILF
9DB803DFILF
Shipping Packaging
Tubes
Tape and Reel
Tubes
Tape and Reel
Tubes
Tape and Reel
Tubes
Tape and Reel
Package
48-pin TSSOP
48-pin TSSOP
48-pin TSSOP
48-pin TSSOP
48-pin SSOP
48-pin SSOP
48-pin SSOP
48-pin SSOP
Temperature
0 to +70° C
0 to +70° C
-40 to +85° C
-40 to +85° C
0 to +70° C
0 to +70° C
-40 to +85° C
-40 to +85° C
"LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
“D” is the device revision designator (will not correlate with the datasheet revision).
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes
no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No
other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications
such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not
recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT
does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
IDT® EIGHT OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1 AND GEN2
20
ICS9DB803D
REV N 071013
ICS9DB803D
EIGHT OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1 AND GEN2
Revision History
Rev.
A
B
C
D
E
F
G
Issue Date
8/15/2006
H
J
Issuer
10/7/2009
1/27/2011
Description
Updated electrical characteristics for final data sheet
Added Input Clock Specs
Updated Input Clock Specs
Fixed typo in Input Clock Parameters
Updated Electrical Char tables
Updated Input Clock Specs
Corrected part ordering information
1. Clarified that Vih and Vil values were for Single ended inputs
2. Added Differential Clock input parameters.
3. Updated Electrical Characteristics to add propagation delay and
phase noise information.
4. Added SMBus electrical characteristics
5. Added foot note about DIF input running in order for the SMBus
interface to work
6. Added foot note to Byte 1 about functionality of OE bits and OE
pins.
7. Updated/Reformatted General Description
Updated Termination Figure 4
Various
12
K
L
5/9/2011
8/27/2012
1. Update pin 2 pin-name and pin description from VDD to VDDR. This
highlights that optimal peformance is obtained by treating VDDR as in
analog pin. This is a document update only, there is no silicon change.
Updated Vswing conditions to include "single-ended measurement"
Various
7
M
9/18/2012
N
7/10/2013
2/29/2008
3/18/2008
3/28/2008
4/10/2008
1/13/2009
R. Wei
Page #
-
Updated Byte 2, bits 0~7 per char review. Outputs can be programmed
with Byte 2 to be Stoppable or Free-Run with DIF_Stop pin, not the OE
pins.
Typo discovered on front page "Output Features" section. Was: “50 –
110MHz operation in PLL mode”; changed to: "50 – 100MHz operation
in PLL mode”
IDT® EIGHT OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1 AND GEN2
21
14
1
ICS9DB803D
REV N 071013
ICS9DB803D
EIGHT OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1 AND GEN2
SYNTHESIZERS
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