9FGP204BKLFT

DATASHEET Frequency Timing Generator for Peripherals Recommended Application: Peripheral Clock for Intel Server Output Features: • 1 - 0.7V current-mode differential CPU pair • 6 - 50MHz RMII outputs • 2 - 125MHz RGMII outputs • 1 - DOT 96MHz output • 1 - 33.33MHz output • 1 - 32.768KHz output • 2 - 25MHz REF outputs Key Specifications: • Exact synthesis on CPU, RGMII, RMII & 33.33MHz clocks • +/- 100ppm frequency accuracy on other clocks Features/Benefits: • Selectable SMBus Address - D0/D1 or C0/C1 • Spread Spectrum capability on CPU and DOT 96MHz clocks • SMBus Control: - M/N and spread programming on CPU and DOT 96MHz clocks via SMBus - Differential outputs can be disabled via pins or SMBus Pin Configuration VttPwr_GD/PD# 9 FGP204 GNDRGMII VDDRGMII SMBDAT 40 39 38 37 36 35 34 33 32 31 GND VDD96 DOT96SST DOT96SSC OE_96 OE_CPU CPUCLKT0 CPUCLKC0 VDDCPU GNDCPU 1 2 3 4 5 6 7 8 9 10 IREF VDD32K 32.768KHz 30 29 28 27 26 25 24 23 22 21 X1_25 GNDREF X2_25 GNDRMII RMII2 RMII3 GNDRMII VDDRMII RMII4 RMII5 VDD33 33.33MHZ/**SMBADR GND33 9FGP204 11 12 13 14 15 16 17 18 19 20 25MHz_0 25MHZ_1 VDDREF GND32K 40-MLF * Internal Pull-Up Resistor ** Internal Pull-Dow n Resistor Functionality CPU FS2 CPU FS1 CPU FS0 CPUCLK DOT96SS MHz MHz Byte0 Bit2 Byte0 Bit1 Byte0 Bit0 0 0 0 266.67 96.00 0 0 1 133.33 96.00 0 1 0 200.00 96.00 0 1 1 166.67 96.00 1 0 0 333.33 96.00 1 0 1 100.00 96.00 1 1 0 400.00 96.00 1 1 1 Reserved 96.00 Power up default is highlighted. 33.33 MHz 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 RMII MHz 50.00 50.00 50.00 50.00 50.00 50.00 50.00 50.00 RGMII MHz 125.00 125.00 125.00 125.00 125.00 125.00 125.00 125.00 25 MHz 25.00 25.00 25.00 25.00 25.00 25.00 25.00 25.00 32.768 KHz 32.768 32.768 32.768 32.768 32.768 32.768 32.768 32.768 SMBus Address Selection SMBADR *SMBADR = 0 D0/D1 * Default value SMBADR = 1 C0/C1 IDT® Frequency Timing Generator for Peripherals VDDRMII SMBCLK RGMII0 RGMII1 RMII0 RMII1 1604B—08/29/11 1 9FGP204 Frequency Timing Generator for Peripherals Pin Description PIN # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 PIN NAME GND VDD96 DOT96SST DOT96SSC OE_96 OE_CPU CPUCLKT0 CPUCLKC0 VDDCPU GNDCPU IREF VDD32K 32.768KHz GND32K VDDREF 25MHz_0 25MHZ_1 GNDREF X1_25 X2_25 GND33 33.33MHZ/**SMBADR VDD33 RMII5 RMII4 VDDRMII GNDRMII RMII3 RMII2 GNDRMII VDDRMII RMII1 RMII0 VDDRGMII GNDRGMII RGMII1 RGMII0 SMBCLK SMBDAT VttPwr_GD/PD# PIN TYPE PWR PWR OUT OUT IN IN OUT OUT PWR PWR OUT PWR OUT PWR PWR OUT OUT PWR IN OUT PWR I/O PWR OUT OUT PWR PWR OUT OUT PWR PWR OUT OUT PWR PWR OUT OUT IN I/O IN DESCRIPTION Ground pin. Power pin for the DOT96 clocks, nominal 3.3V True clock of differential pair for 96.00MHz spread spectrum capable DOT clock. These are current mode outputs. External resistors are required for voltage bias. Complementary clock of differential pair for 96.00MHz spread spectrum capable DOT clock. These are current mode outputs. External resistors are required for voltage bias. Active high input for enabling 96Hz outputs. 1 = enable output(s), 0 =disable output(s) Active high input for enabling CPU DIFF pairs. 1 = enable output(s), 0 =disable output(s) True clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. Complementary clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. Supply for CPU clocks, 3.3V nominal Ground pin for the CPU outputs This pin establishes the reference for the differential current-mode output pairs. It requires a fixed precision resistor to ground. 475ohm is the standard value for 100ohm differential impedance. Other impedances require different values. See data sheet. Power pin for the 32.768KHz outputs, nominal 3.3V 32.768KHz clock output Ground pin for the 32.768KHz outputs Ref, XTAL power supply, nominal 3.3V 25MHz clock output, 3.3V 25MHz clock output, 3.3V Ground pin for the REF outputs. Crystal input, Nominally 25.00MHz. Crystal output. Ground pin for the 33.33MHz outputs 33.33MHz clock output / SMBus address select bit. Power pin for the 33.33MHz outputs, nominal 3.3V 3.3V 50MHz RMII clock output 3.3V 50MHz RMII clock output 3.3V power pin for the RMII clocks. Ground pin for the RMII outputs 3.3V 50MHz RMII clock output 3.3V 50MHz RMII clock output Ground pin for the RMII outputs 3.3V power pin for the RMII clocks. 3.3V 50MHz RMII clock output 3.3V 50MHz RMII clock output 3.3V power pin for the RGMII clocks and PLL Ground pin for the RGMII outputs 3.3V 125MHz RGMII clock output 3.3V 125MHz RGMII clock output Clock pin of SMBUS circuitry, 5V tolerant Data pin of SMBUS circuitry, 5V tolerant This 3.3V LVTTL input is a level sensitive strobe used to determine when latch inputs are valid and are ready to be sampled. This is an active high input. / Asynchronous active low input pin used to power down the device into a low power state. IDT® Frequency Timing Generator for Peripherals 1604B—08/29/11 2 9FGP204 Frequency Timing Generator for Peripherals General Description The 9FGP204 is a peripheral clock for Intel Servers. It is driven with a 25MHz crystal and generates a variety of clocks, including 125MHz RGMII. An SMBus interface allows full control of the device. Block Diagram 25MHz(1:0) X1_25 X2_25 XTAL CPU PLL (SPREAD CAPABLE) CPUCLK VttPwr_GD/PD# OE_CPU OE_96 CONTROL LOGIC SMBADR SMBDAT SMBCLK DOT PLL (SPREAD CAPABLE) DOT96SS 33.33MHz FIXED PLL DIVIDERS 2 6 RGMII(1:0) RMII(5:0) DIVIDERS 32.768KHz Power Supply Pins Pin Number Description VDD GND 9 10 CPUCLK output and PLL 2 1 DOT96SS output and PLL 34 35 125 MHz RGMII outputs and PLL 26,31 27,30 50 MHz RMII outputs 23 21 33.33MHz output 12 14 32.768KHz output 15 18 XTAL, REF outputs Note: All VDD should be connected to a common power rail with proper filtering and decoupling. Pins 2, 9 and 34 should be treated as analog pins for decoupling purposes. IDT® Frequency Timing Generator for Peripherals 1604B—08/29/11 3 9FGP204 Frequency Timing Generator for Peripherals ICS9FGP202A ICS9FGP204 Zo Rs CL=5pF SEPP Output Buffer (Single Ended Push Pull) Test Load L1 Zo Rs L2 CL=5pF Zo Rs SEPP Output Buffer (Single Ended Push Pull) CL=5pF NOTE: L1 must equal L2 +/- 25 mils Drive Strength for all the single-ended outputs can be controlled by the SMBus Bytes 4 and 5 as shown in the Default Drive Strength Table. Default Drive Strength Table Default Drive RGMII 1 Load RMII 1 Load 33.33MHz 2 Loads 25Mhz 2 Loads 32.768KHz 2 Loads Optional Drive NA 2 Loads 1 Load 1 Load 1 Load Series Termination Resistor Values EXCEPT RGMII Series Resistor Series Resistor Output Drive (Rs) for driving 1 (Rs) for driving 2 Load Loads Strength 1 Load 22 ohms N/A 2 Loads 33 ohms 8.2 ohms Note: All values are for Zo = 50Ω Series Termination Resistor Values - RGMII Series Resistor Series Resistor (Rs) for driving 1 (Rs) for driving 2 Output Drive Load Loads Strength 1 Load 27 ohms N/A Note: All values are for Zo = 50Ω IDT® Frequency Timing Generator for Peripherals 1604B—08/29/11 4 9FGP204 Frequency Timing Generator for Peripherals Truth Table 1: VttPwr_GD/PD# and OE_96 VttPwr_GD/PD# OE_96 Clocks Pin 40 Pin 5 0 0 All clocks are powered down 0 1 All clocks are powered down 1 0 All clocks are enabled except DOT96SS 1 1 *All clocks are enabled including DOT96SS *Assuming DOT96 Output Enable from SMBus Byte2 Bit0 sets to enable (default) Truth Table 2: VttPwr_GD/PD# and OE_CPU VttPwr_GD/PD# OE_CPU Clocks Pin 40 Pin 6 0 0 All clocks are powered down 0 1 All clocks are powered down 1 0 All clocks are enabled except CPUCLK 1 1 *All clocks are enabled including CPUCLK *Assuming CPUCLK Output Enable from SMBus Byte2 Bit1 sets to enable (default) Table 1: CPU Spread and Frequency Selection CPU SS_EN Byte 0 Bit 3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 CPU FS2 Byte 0 Bit 2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 CPU FS1 Byte 0 Bit 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 CPU FS0 Byte 0 Bit 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CPU MHz 266.67 133.33 200.00 166.67 333.33 100.00 400.00 200.00 266.67 133.33 200.00 166.67 333.33 100.00 400.00 200.00 Down Spread % 0% 0% 0% 0% 0% 0% 0% 0% 0.5% 0.5% 0.5% 0.5% 0.5% 0.5% 0.5% 0.5% IDT® Frequency Timing Generator for Peripherals 1604B—08/29/11 5 9FGP204 Frequency Timing Generator for Peripherals Table2: DOT96 Spread and Frequency Selection Table DOT96 SS_EN Byte 0 bit 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FS3 Byte 3 bit 3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 FS2 Byte 3 bit 2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 FS1 Byte 3 bit 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 FS0 Byte 3 bit 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 DOT96SS MHz 96.00 96.00 96.00 96.00 96.00 96.00 96.00 96.00 96.00 96.00 96.00 96.00 96.00 96.00 96.00 96.00 96.00 96.00 96.00 96.00 96.00 96.00 96.00 96.00 96.00 96.00 96.00 96.00 96.00 96.00 96.00 96.00 Spread % 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +/-0.25 +/-0.5 +/-0.75 +/-1.0 -0.25 -0.50 -0.75 -1.0 -1.25 -1.50 -1.75 -2.0 -2.25 -2.5 -2.75 -3.00 Center Center Center Center Down Down Down Down Down Down Down Down Down Down Down Down IDT® Frequency Timing Generator for Peripherals 1604B—08/29/11 6 9FGP204 Frequency Timing Generator for Peripherals Absolute Maximum Ratings PARAMETER 3.3V Supply Voltage Maximum difference across all VDD pins Storage Temperature Ambient Operating Temp Junction Temperature Input ESD protection HBM 1 SYMBOL VDDxxx VDDdelta Ts Tambient Tj ESD prot CONDITIONS - MIN GND 0.5 TYP 3.3V MAX GND + 4.5 0.5 UNITS V V ° Notes 1 1 1 1 1 1 -65 0 2000 150 70 125 C °C °C V Guaranteed by design and characterization, not 100% tested in production. Electrical Characteristics - Input/Supply/Common Output Parameters PARAMETER Input High Voltage Input Low Voltage Input High Current SYMBOL VIH VIL IIH IIL1 Input Low Current IIL2 Low Threshold InputHigh Voltage Low Threshold InputLow Voltage Operating Current Powerdown Current Input Frequency Pin Inductance Input Capacitance VIH_FS VIL_FS IDD3.3OP IDD3.3PD Fi Lpin CIN COUT CINX Clk Stabilization Modulation Frequency Tdrive_PD Tfall_PD Trise_PD SMBus Voltage VDD @ IPULLUP 4 (Max VIL - 0.15) to (Min VIH + 0.15) (Min VIH + 0.15) to (Max VIL - 0.15) 5 1000 300 Low-level Output Voltage VOL Current sinking at IPULLUP VOL = 0.4 V SCLK/SDATA TRI2C Clock/Data Rise Time SCLK/SDATA TFI2C Clock/Data Fall Time *TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5% 1 2 CONDITIONS* 3.3 V +/-5% 3.3 V +/-5% VIN = VDD VIN = 0 V; Inputs with no pull-up resistors VIN = 0 V; Inputs with pull-up resistors 3.3 V +/-5% 3.3 V +/-5% all outputs driven, CPU@100M all diff pairs driven all differential pairs tri-stated VDD = 3.3 V Logic Inputs Output pin capacitance X1 & X2 pins From VDD Power-Up or deassertion of PD to 1st clock Triangular Modulation CPU output enable after PD de-assertion PD fall time of PD rise time of MIN 2 VSS - 0.3 -5 -5 -200 0.7 VSS - 0.3 TYP MAX VDD + 0.3 0.8 5 UNITS V V uA uA uA Notes 1 1 1 1 1 1 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VDD + 0.3 0.35 204 20 5 25.00000 7 4 5 5 0.5 2.5 33 260 300 5 5 225 30 8 V V mA mA mA MHz nH pF pF pF ms kHz us ns ns V V mA ns ns TSTAB 30 2.7 5.5 0.4 Guaranteed by design and characterization, not 100% tested in production. Input frequency should be measured at the REF pin and tuned to ideal 25.00MHz to meet ppm frequency accuracy on PLL outputs. 1604B—08/29/11 IDT® Frequency Timing Generator for Peripherals 7 9FGP204 Frequency Timing Generator for Peripherals Electrical Characteristics - CPU 0.7V Current Mode Differential Pair PARAMETER Current Source Output Impedance Voltage High Voltage Low Max Voltage Min Voltage Crossing Voltage (abs) Crossing Voltage (var) Long Accuracy Average period Absolute min/max period Rise Time Fall Time Rise Time Variation Fall Time Variation SYMBOL Zo VHigh VLow Vovs Vuds Vx(abs) d-Vx ppm Tperiod Tabsmin/max tr tf d-tr d-tf Variation of crossing over all edges see Tperiod min-max values 100.00MHz nominal 100.00MHz spread 100.00MHz nominal/spread VOL = 0.175V, VOH = 0.525V VOH = 0.525V VOL = 0.175V VOL = 0.175V, VOH = 0.525V CONDITIONS* VO = Vx Statistical measurement on single ended signal Measurement on single ended signal using absolute value. MIN 3000 660 -150 -300 250 731 70 800 8 366 16 -100 9.9990 10.0240 9.9490 175 175 376 335 104 92 12.7 1 45 2 49.8 45 0 10.0000 10.0250 550 140 100 10.0001 10.0251 10.1011 700 700 125 125 20 4 55 50 850 150 1150 TYP MAX UNITS NOTES Ω mV mV mV mV mV mV ppm ns ns ns ps ps ps ps % V/ns % ps 1 1,3 1,3 1 1 1 1 1,2 2 2 1,2 1,4 1,4 1 1 1 1,5 1 1 VOH = 0.525V VOL = 0.175V Single-ended measurement, Rise/Fall Matching tRFM averaging on Differential Measurment Slew Rate tSLEW Measurement from differential Duty Cycle dt3 wavefrom Measurement from differential Jitter, Cycle to cycle tjcyc-cyc wavefrom, CPUCLK *TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2Ω, RP=49.9Ω, IREF = 475Ω 1 2 3 4 5 Guaranteed by design and characterization, not 100% tested in production. All Long Term Accuracy and Clock Period specifications are guaranteed assuming that 25MHz_x is tuned to exactly 25.000MHz IREF = VDD/(3xRR). For RR = 475Ω ( 1%), IRE F = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ ZO=50Ω. Rise/fall time measured on single-ended waveform per CK410 specification. Slew rate measured on differential waveform per CK505 specification. IDT® Frequency Timing Generator for Peripherals 1604B—08/29/11 8 9FGP204 Frequency Timing Generator for Peripherals Electrical Characteristics - DOT96SS 0.7V Current Mode Differential Pair PARAMETER Current Source Output Impedance Voltage High Voltage Low Max Voltage Min Voltage Crossing Voltage (abs) Crossing Voltage (var) Long Accuracy Average period Absolute min period Rise Time Fall Time Rise Time Variation Fall Time Variation SYMBOL Zo VHigh VLow Vovs Vuds Vx(abs) d-Vcross ppm Tperiod Tabsmin tr tf d-tr d-tf Variation of crossing over all edges see Tperiod min-max values 96.00MHz nominal 96.00MHz -0.5% spread 96.00MHz nominal/-0.5% spread VOL = 0.175V, VOH = 0.525V VOH = 0.525V VOL = 0.175V VOL = 0.175V, VOH = 0.525V CONDITIONS* VO = Vx Statistical measurement on single ended signal Measurement on single ended signal using absolute value. MIN 3000 660 -150 -300 250 725 51 764 5 372 550 140 -100 10.4156 10.4417 10.1917 175 175 361 375 107 107 15 1 45 2 51.3 54 -41 10.4166 10.4427 100 10.4176 10.4437 10.6937 700 700 125 125 20 4 55 250 850 150 1150 TYP MAX UNITS Ω mV mV mV mV mV mV ppm ns ns ns ps ps ps ps % V/ns % ps Notes 1 1,3 1,3 1 1 1 1 1,2 2 2 1,2 1,4 1,4 1 1 1 1,5 1 1 VOH = 0.525V VOL = 0.175V Single-ended measurement, Rise/Fall Matching tRFM averaging on Slew Rate tSLEW Differential Measurment Measurement from differential Duty Cycle dt3 wavefrom Measurement from differential Jitter, Cycle to cycle tjcyc-cyc wavefrom *TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2Ω, RP=49.9Ω, IREF = 475Ω 1 2 3 4 5 Guaranteed by design and characterization, not 100% tested in production. All Long Term Accuracy and Clock Period specifications are guaranteed assuming that 25MHz_x is tuned to exactly 25.000MHz IREF = VDD/(3xRR). For RR = 475Ω ( 1%), IRE F = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ ZO=50Ω. Rise/fall time measured on single-ended waveform per CK410 specification. Slew rate measured on differential waveform per CK505 specification. Electrical Characteristics - REF - 25MHz PARAMETER Long Accuracy Clock period Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Skew Duty Cycle Jitter, Cycle-cycle 1 2 SYMBOL ppm T period VOH VOL IOH IOL tr1 tf1 tsk1 dt1 tj c y c-c y c CONDITIONS see Tperiod min-max values 25.00MHz output nominal IOH = - 1 mA IOL = 1 mA V OH @MIN = 1.0 V VOH@MAX = 3.135 V VOL @ MIN = 1.95 V VOL @ MAX = 0.4 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V MIN -50 39.998 2.4 TYP 0 40.000 MAX 50 40.002 0.4 UNITS ppm ns V V mA mA mA mA ns ns ps % ps Notes 1,2 2 1 1 1 1 1 1 1 1 1 1 1 -29 -23 29 27 1 1 45 1.14 1.32 16 53.2 75 2 2 500 55 200 *TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%, CL = 5 pF with Rs as shown in the termination table (unless otherwise specified) Guaranteed by design and characterization, not 100% tested in production. All Long Term Accuracy and Clock Period specifications are guaranteed assuming that 25MHz_x is tuned to exactly 25.000MHz 1604B—08/29/11 IDT® Frequency Timing Generator for Peripherals 9 9FGP204 Frequency Timing Generator for Peripherals Electrical Characteristics - RGMII - 125MHz PARAMETER Long Accuracy Clock period Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Group Skew Jitter, Long Term Jitter, Cycle to cycle Jitter, Peak 1 2 3 SYMBOL ppm Tperiod VOH VOL IOH IOL tr tf dt1 tskew RGMII CONDITIONS* see Tperiod min-max values 125.00MHz output nominal IOH = - 1 mA IOL = 1 mA V OH @MIN = 1.0 V VOH@MAX = 3.135 V VOL @ MIN = 1.95 V VOL @ MAX = 0.4 V VOL=20%xVdd, VOH=80%xVdd VOL=20%xVdd, VOH=80%xVdd VT = 1.5 V VT = 1.5 V, VT = 1.5 V, 10 : sec interval VT = 1.5 V VT = 1.5 V MIN -50 7.9996 2.4 TYP 0 8.000 MAX 50 8.0004 0.4 UNITS NOTES 1,2 ppm ns V V mA mA mA mA ns ns % ps ps ps ps 1 1 1 1 1 1 1 1 1 1 1 1 1 1,3 -33 -33 30 38 0.66 0.70 45 52.9 15 141 75 68 0.75 0.75 55 100 500 250 100 tj abs tj c y c-c y c tjpeak *TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%, CL = 5 pF with Rs as shown in the termination table (unless otherwise specified) Guaranteed by design and characterization, not 100% tested in production. All Long Term Accuracy and Clock Period specifications are guaranteed assuming that 25MHz_x is tuned to exactly 25.000MHz 1/2 of the peak-to-peak jitter. (Lg+ + |Lg-|)/2 Electrical Characteristics - RMII - 50MHz PARAMETER Long Accuracy Clock period Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Group Skew Jitter, Long Term Jitter, Peak 1 2 3 SYMBOL ppm Tperiod VOH VOL IOH IOL tr tf dt1 tskew_RMII(5:0) tj abs tjpeak CONDITIONS* see Tperiod min-max values 50.00MHz output nominal IOH = - 1 mA IOL = 1 mA V OH @MIN = 1.0 V VOH@MAX = 3.135 V VOL @ MIN = 1.95 V VOL @ MAX = 0.4 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V, across all 6 outputs VT = 1.5 V, 10 8 sec interval VT = 1.5 V MIN -50 19.9990 2.4 TYP 0 20.0000 MAX 50 20.001 0.4 UNITS NOTES 1,2 ppm ns V V mA mA mA mA ns ns % ps ps ps 1 1 1 1 1 1 1 1 1 1 1 1 1,3 -33 -33 30 38 1 1 35 1.1 1.1 51.5 60 127 88 3 3 65 200 500 100 *TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%, CL = 5 pF with Rs as shown in the termination table (unless otherwise specified) Guaranteed by design and characterization, not 100% tested in production. All Long Term Accuracy and Clock Period specifications are guaranteed assuming that 25MHz_x is tuned to exactly 25.000MHz 1/2 of the peak-to-peak jitter. (Lg+ + |Lg-|)/2 IDT® Frequency Timing Generator for Peripherals 1604B—08/29/11 10 9FGP204 Frequency Timing Generator for Peripherals Electrical Characteristics - 33.33MHz PARAMETER Long Accuracy Clock period Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Jitter, Cycle to cycle 1 SYMBOL ppm Tperiod VOH VOL IOH IOL tr tf dt1 tj c y c-c y c CONDITIONS* see Tperiod min-max values 33.33MHz output non-spread IOH = - 1 mA IOL = 1 mA V OH @MIN = 1.0 V VOH@MAX = 3.135 V VOL @ MIN = 1.95 V VOL @ MAX = 0.4 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V MIN -100 29.9970 2.4 TYP 0 30.0000 MAX 100 30.0030 0.4 UNITS NOTES 1 ppm ns V V mA mA mA mA ns ns % ps 1 1 1 1 1 1 1 1 1 1 1 -33 -33 30 38 0.5 0.5 45 0.87 1.35 50.7 104 2 2 55 350 *TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%, CL = 5 pF with Rs as shown in the termination table (unless otherwise specified) Guaranteed by design and characterization, not 100% tested in production. Electrical Characteristics - 32.768KHz PARAMETER Long Accuracy Clock period Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Jitter, Cycle to cycle 1 SYMBOL ppm Tperiod VOH VOL IOH IOL tr tf dt1 tj c y c-c y c CONDITIONS* see Tperiod min-max values 32.768KHz output nominal IOH = - 1 mA IOL = 1 mA V OH @MIN = 1.0 V VOH@MAX = 3.135 V VOL @ MIN = 1.95 V VOL @ MAX = 0.4 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V MIN -100 30.5149 2.4 TYP -79 30.5180 MAX 100 30.5211 0.4 UNITS NOTES 1 ppm us V V mA mA mA mA ns ns % ps 1 1 1 1 1 1 1 1 1 1 1 -33 -33 30 38 1 1 45 1.39 1.6 49.5 220 4 4 55 500 *TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%, CL = 5 pF with Rs as shown in the termination table (unless otherwise specified) Guaranteed by design and characterization, not 100% tested in production. IDT® Frequency Timing Generator for Peripherals 1604B—08/29/11 11 9FGP204 Frequency Timing Generator for Peripherals General SMBus serial interface information for the 9FGP204 How to Write: Controller (host) sends a start bit. Controller (host) sends the write address D0 (H) ICS clock will acknowledge Controller (host) sends the beginning byte location = N ICS clock will acknowledge Controller (host) sends the data byte count = X ICS clock will acknowledge Controller (host) starts sending Byte N through Byte N + X -1 • ICS clock will acknowledge each byte one at a time • Controller (host) sends a Stop bit • • • • • • • • How to Read: • • • • • • • • • • • • • • Controller (host) will send start bit. Controller (host) sends the write address D0 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) will send a separate start bit. Controller (host) sends the read address D1 (H) ICS clock will acknowledge ICS clock will send the data byte count = X ICS clock sends Byte N + X -1 ICS clock sends Byte 0 through byte X (if X(H) was written to byte 8). Controller (host) will need to acknowledge each byte Controller (host) will send a not acknowledge bit Controller (host) will send a stop bit Index Block Write Operation Controller (Host) starT bit T S lave Address *D0(H) WR WRite Beginning Byte = N ACK Data Byte Count = X ACK Beginning Byte N ACK X Byte ICS (Slave/Receiver) Index Block Read Operation Controller (Host) T starT bit S lave Address *D0(H) WR WRite Beginning Byte = N ACK RT Repeat starT Slave Address *D1(H) RD ReaD ACK Data Byte Count = X ACK Beginning Byte N ACK ICS (Slave/Receiver) ACK ACK Byte N + X - 1 ACK P stoP bit X Byte Byte N + X - 1 N P Not acknowledge stoP bit * The SMBus address depends on the latched value of pin 22. Please see SMBus Address Selection table on page 1. IDT® Frequency Timing Generator for Peripherals 1604B—08/29/11 12 9FGP204 Frequency Timing Generator for Peripherals SMBus Table: CPU Frequency Select and Spread Spectrum Control Register Pin # Name Control Function Byte 0 Reserved Reserved Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reserved Reserved DOT96 SS_EN CPU SS_EN CPU FS2 CPU FS1 CPU FS0 Reserved Reserved DOT96 Spread Spectrum Enable CPU Spread Spectrum Enable CPU Freq Select Bit 2 CPU Freq Select Bit 1 CPU Freq Select Bit 0 Type RW Rev 0.20 RW RW RW RW RW RW 0 Reserved Reserved 1 PWD 0 0 0 0 0 1 0 1 Reserved Disable Enable See Table 1: CPU Frequency Selection Table SMBus Table: RMII Output Control Register Pin # Byte 1 Name 24 RMII_5 Enable Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 25 28 29 32 33 36 37 RMII_4 Enable RMII_3 Enable RMII_2 Enable RMII_1 Enable RMII_0 Enable RGMII_1 Enable RGMII_0 Enable Control Function RMII_7 Output Control RMII_6 Output Control RMII_5 Output Control RMII_4 Output Control RMII_3 Output Control RMII_2 Output Control RGMII_1 Output Control RGMII_0 Output Control Type RW RW RW RW RW RW RW RW 0 Disable Disable Disable Disable Disable Disable Disable Disable 1 Enable Enable Enable Enable Enable Enable Enable Enable PWD 1 1 1 1 1 1 1 1 SMBus Table: DOT, CPU, 32.768KHz, 25MHz and 33.33MHz Outputs Control Register Pin # Byte 2 Name Control Function 7,8 CPUCLK PD Drive Mode Driven in PD Bit 7 DOT96SS PD Drive 3,4 Driven in PD Bit 6 Mode 22 33.33MHz Enable 33.33MHz Output Control Bit 5 17 25MHz_1 Enable 25MHz_1 Output Control Bit 4 16 25MHz_0 Enable 25MHz_0 Output Control Bit 3 13 32.768kHz Enable 32.768KHz Output Control Bit 2 6 CPUCLK Enable CPUCLK Output Control Bit 1 5 DOT96SS Enable DOT96SS Output Control Bit 0 SMBus Table: DOT96 Frequency Select and Spread Spectrum Control Register Pin # Byte 3 Name Control Function Reserved Reserved Bit 7 Reserved Reserved Bit 6 Reserved Reserved Bit 5 Reserved Reserved Bit 4 DOT96SS FS3 DOT96 Freq Select Bit Bit 3 DOT96SS FS2 DOT96 Freq Select Bit Bit 2 DOT96SS FS1 DOT96 Freq Select Bit Bit 1 DOT96SS FS0 DOT96 Freq Select Bit Bit 0 SMBus Table: RMII Strength Control Register Pin # Byte 4 Name 24 RMII_5 Str Bit 7 25 RMII_4 Str Bit 6 28 RMII_3 Str Bit 5 29 RMII_2 Str Bit 4 32 RMII_1 Str Bit 3 33 RMII_0 Str Bit 2 Reserved Bit 1 Reserved Bit 0 Type RW RW RW RW RW RW RW RW 0 Driven Driven Disable Disable Disable Disable Disable Disable 1 Hi-Z Hi-Z Enable Enable Enable Enable Enable Enable PWD 0 0 1 1 1 1 1 1 3 2 1 0 Type RW RW RW RW RW RW RW RW 0 Reserved Reserved Reserved Reserved 1 See Table 2: DOT Frequency Selection Table PWD 0 0 0 0 0 0 0 0 Control Function RMII_7 Strength Control RMII_6 Strength Control RMII_5 Strength Control RMII_4 Strength Control RMII_3 Strength Control RMII_2 Strength Control Reserved Reserved Type RW RW RW RW RW RW RW RW 0 1 1-Load (1X) 2-Loads 1-Load (1X) 2-Loads 1-Load (1X) 2-Loads 1-Load (1X) 2-Loads 1-Load (1X) 2-Loads 1-Load (1X) 2-Loads Reserved Reserved (2X) (2X) (2X) (2X) (2X) (2X) PWD 0 0 0 0 0 0 0 0 IDT® Frequency Timing Generator for Peripherals 1604B—08/29/11 13 9FGP204 Frequency Timing Generator for Peripherals SMBus Table: 32.768KHz, 25Mhz and 33.33MHz Strength Control Register Byte 5 Pin # Name Control Function Reserved Reserved Bit 7 Reserved Reserved Bit 6 22 33.33MHz Str 33.33MHz Strength Control Bit 5 17 25MHz_1 Str 25MHz_1 Strength Control Bit 4 16 25MHz_0 Str 25MHz_1 Strength Control Bit 3 13 32.768kHz Str 32.768kHz Strength Control Bit 2 Reserved Reserved Bit 1 Reserved Reserved Bit 0 SMBus Table: Vendor & Revision ID Register Pin # Name Byte 6 RID3 Bit 7 RID2 Bit 6 RID1 Bit 5 RID0 Bit 4 VID3 Bit 3 VID2 Bit 2 VID1 Bit 1 VID0 Bit 0 SMBus Table: Device ID Pin # Byte 7 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type RW RW RW RW RW RW RW RW 0 Reserved Reserved 1-Load (1X) 1-Load (1X) 1-Load (1X) 1-Load (1X) Reserved Reserved 1 2-Loads 2-Loads 2-Loads 2-Loads (2X) (2X) (2X) (2X) PWD 0 0 1 1 1 1 0 0 Control Function REVISION ID VENDOR ID Type R R R R R R R R 0 A rev = 0000 B rev = 0001 1 ICS/IDT = 0001 PWD X X X X 0 0 0 1 Name Device ID 7 (MSB) Device ID 6 Device ID 5 Device ID 4 Device ID 3 Device ID 2 Device ID 1 Device ID 0 (LSB) Control Function Device ID Type RW RW RW RW RW RW RW RW 0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 1 PWD 0 0 1 0 0 1 0 0 SMBus Table: Byte Count Register Pin # Name Byte 8 BC7 Bit 7 BC6 Bit 6 BC5 Bit 5 BC4 Bit 4 BC3 Bit 3 BC2 Bit 2 BC1 Bit 1 BC0 Bit 0 SMBus Table: Reserved Pin # Byte 9 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Control Function Writing to this register configures how many bytes will be read back. Type RW RW RW RW RW RW RW RW 0 - 1 - PWD 0 0 0 0 1 0 0 1 Name Control Function Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Type 0 1 PWD 0 0 0 0 0 0 0 0 IDT® Frequency Timing Generator for Peripherals 1604B—08/29/11 14 9FGP204 Frequency Timing Generator for Peripherals SMBus Table: PLLs M/N Programming Enable Register Byte 10 Name Control Function Pin # M/N_EN PLLs M/N Programming Enable Bit 7 Reserved Bit 6 Reserved Bit 5 Reserved Bit 4 Reserved Bit 3 Reserved Bit 2 Reserved Bit 1 Reserved Bit 0 SMBus Table: CPU PLL VCO Frequency Control Register Name Control Function Byte 11 Pin # N Div8 N Divider Prog bit 8 Bit 7 N Div 9 N Divider Prog bit 9 Bit 6 M Div5 Bit 5 M Div4 Bit 4 M Div3 Bit 3 M Divider Programming bits M Div2 Bit 2 M Div1 Bit 1 M Div0 Bit 0 SMBus Table: CPU PLL VCO Frequency Control Register Pin # Name Control Function Byte 12 N Div7 Bit 7 N Div6 Bit 6 N Div5 Bit 5 N Div4 Bit 4 N Divider Programming b(7:0) N Div3 Bit 3 N Div2 Bit 2 N Div1 Bit 1 N Div0 Bit 0 SMBus Table: CPU PLL Spread Spectrum Control Register Pin # Name Control Function Byte 13 SSP7 Bit 7 SSP6 Bit 6 SSP5 Bit 5 Spread Spectrum Programming SSP4 Bit 4 b(7:0) SSP3 Bit 3 SSP2 Bit 2 SSP1 Bit 1 SSP0 Bit 0 SMBus Table: CPU PLL Spread Spectrum Control Register Pin # Name Control Function Byte 14 Reserved Bit 7 SSP14 Bit 6 SSP13 Bit 5 SSP12 Bit 4 Spread Spectrum Programming SSP11 Bit 3 b(14:8) SSP10 Bit 2 SSP9 Bit 1 SSP8 Bit 0 Type RW 0 Disable 1 Enable PWD 0 0 0 0 0 0 0 0 Type RW RW RW RW RW RW RW RW 0 1 The decimal representation of M and N Divier in Byte 11 and 12 will configure the VCO frequency. Default at power up = latch-in or Byte 0 Rom table. VCO Frequency = 25 x [NDiv(9:0)+8] / [MDiv(5:0)+2] PWD X X X X X X X X Type RW RW RW RW RW RW RW RW 0 1 The decimal representation of M and N Divier in Byte 11 and 12 will configure the VCO frequency. Default at power up = latch-in or Byte 0 Rom table. VCO Frequency = 25 x [NDiv(9:0)+8] / [MDiv(5:0)+2] PWD X X X X X X X X Type RW RW RW RW RW RW RW RW 0 1 These Spread Spectrum bits in Byte 13 and 14 will program the spread pecentage. It is recommended to use ICS Spread % table for spread programming. PWD X X X X X X X X Type RW RW RW RW RW RW RW 0 1 These Spread Spectrum bits in Byte 13 and 14 will program the spread pecentage. It is recommended to use ICS Spread % table for spread programming. PWD 0 X X X X X X X IDT® Frequency Timing Generator for Peripherals 1604B—08/29/11 15 9FGP204 Frequency Timing Generator for Peripherals SMBus Table: DOT PLL VCO Frequency Control Register Byte 15 Name Control Function Pin # N Div8 N Divider Prog bit 8 Bit 7 N Div9 N Divider Prog bit 9 Bit 6 M Div5 Bit 5 M Div4 Bit 4 M Div3 Bit 3 M Divider Programming bits M Div2 Bit 2 M Div1 Bit 1 M Div0 Bit 0 SMBus Table: DOT PLL VCO Frequency Control Register Name Control Function Pin # Byte 16 N Div7 Bit 7 N Div6 Bit 6 N Div5 Bit 5 N Div4 Bit 4 N Divider Programming b(7:0) N Div3 Bit 3 N Div2 Bit 2 N Div1 Bit 1 N Div0 Bit 0 SMBus Table: DOT PLL Spread Spectrum Control Register Pin # Name Control Function Byte 17 SSP7 Bit 7 SSP6 Bit 6 SSP5 Bit 5 Spread Spectrum Programming SSP4 Bit 4 b(7:0) SSP3 Bit 3 SSP2 Bit 2 SSP1 Bit 1 SSP0 Bit 0 SMBus Table: DOT PLL Spread Spectrum Control Register Pin # Name Control Function Byte 18 Reserved Bit 7 SSP14 Bit 6 SSP13 Bit 5 SSP12 Bit 4 Spread Spectrum Programming SSP11 Bit 3 b(14:8) SSP10 Bit 2 SSP9 Bit 1 SSP8 Bit 0 Bytes 19:21 are reserved. Type RW RW RW RW RW RW RW RW 0 1 The decimal representation of M and N Divier in Byte 17 and 18 will configure the VCO frequency. Default at power up = Byte 0 Rom table. VCO Frequency = 25 x [NDiv(9:0)+8] / [MDiv(5:0)+2] PWD X X X X X X X X Type RW RW RW RW RW RW RW RW 0 1 The decimal representation of M and N Divier in Byte 17 and 18 will configure the VCO frequency. Default at power up = Byte 0 Rom table. VCO Frequency = 25 x [NDiv(9:0)+8] / [MDiv(5:0)+2] PWD X X X X X X X X Type RW RW RW RW RW RW RW RW 0 1 These Spread Spectrum bits in Byte 19 and 20 will program the spread pecentage. It is recommended to use ICS Spread % table for spread programming. PWD X X X X X X X X Type RW RW RW RW RW RW RW 0 1 These Spread Spectrum bits in Byte 19 and 20 will program the spread pecentage. It is recommended to use ICS Spread % table for spread programming. PWD 0 X X X X X X X IDT® Frequency Timing Generator for Peripherals 1604B—08/29/11 16 9FGP204 Frequency Timing Generator for Peripherals Seating Plane Index Area N 1 2 E Top View Anvil Singulation or Sawn Singulation E2 E2 2 (Ref.) (N D -1)x e A1 A3 L (Ref.) ND & NE Even N 1 2 (NE -1)x e (Ref.) (Typ.) e 2 If N & N D E are Even b A (Ref.) e D2 2 D2 D ND & NE Odd C Thermal Base 0.08 C THERMALLY ENHANCED, VERY THIN, FINE PITCH QUAD FLAT / NO LEAD PLASTIC PACKAGE (JEDEC reference only) (IDT package) DIMENSIONS SYMBOL A A1 A3 b e MIN. 0.8 0 0.1 8 MAX. 1.0 0.05 0.25 Reference 0.3 0.50 BASIC DIMENSIONS SYMBOL N ND NE D x E BASIC D2 MIN. / MAX. E2 MIN. / MAX. L MIN. / MAX. 40L VJJD-2 / -5 40 10 10 6.00 x 6.00 1.75 / 4.80 1.75 / 4.80 0.30 / 0.50 TOLERANCE 40 10 10 6.00 x 6.00 2.75 / 3.0 2.75 / 3.0 0.3 / 0.5 Ordering Information Part / Order Number 9FGP204BKLF 9FGP204BKLFT Shipping Packaging Trays Tape and Reel Package 40-pin MLF 40-pin MLF Temperature 0 to +70° C 0 to +70° C Parts that are ordered with an “LF” to the suffix are the Pb-Free configuration and are RoHS compliant. IDT® Frequency Timing Generator for Peripherals 1604B—08/29/11 17 9FGP204 Frequency Timing Generator for Peripherals Revision History Rev. 0.1 0.2 0.3 Issue Date 6/8/2009 11/9/2009 1/29/2010 Who RDW RDW RDW Description Page # Initial Release Updated SMBus Byte 4 bits 0, 1 to reserved 1. Updated Series Termination values 2. Added separate Table for RGMII output. 1. Updated Series Termination values and highlighted values are for Zo = 50 ohms. 2. Raised Idd MAX to 225mA from 200 mA 3. Adding Rise/Fall Matching spec to CPU and DOT96SS Electrical Tables. 4, 7, 8, 4. Removed All CPU frequencies except 100 from CPU Electrical 9, 10, 11 Table. 5. Updated Min/Max clock periods to reflect new 50 ps cycle to cycle jitter limit on CPU output. 4. Updated electrical tables with typical values from char report. 3 1. Removed OE pins for RMII from the block diagram. A B 4/7/2010 8/29/2011 RDW RDW Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 For Tech Support 408-284-6578 pcclockhelp@idt.com Corporate Headquarters Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.) Asia Pacific and Japan IDT Singapore Pte. Ltd. 1 Kallang Sector #07-01/06 KolamAyer Industrial Park Singapore 349276 Phone: 65-6-744-3356 Fax: 65-6-744-1764 Europe IDT Europe Limited 321 Kingston Road Leatherhead, Surrey KT22 7TU England Phone: 44-1372-363339 Fax: 44-1372-378851 © 2010 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, ICS, and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA 18