9UMS9001AKLF

PC MAIN CLOCK - CK540 Recommended Application: Calistoga Based Ultra-Mobile PC (UMPC) 9 UMS9001 Features/Benefits: • • • • • • • • Supports Dothan ULV CPUs with 100 and 133 MHz CPU outputs Dedicated TEST/SEL and TEST/MODE pins saves isolation resistors on pins PCI_SRC and CPU STOP inputs for power manangment Fully integrated Vreg Integrated series resistors on differential outputs Supports split rail operation for maximum power savings Also runs from single 3.3V rail 1.05V-3.3V support for differential VDDIO Output Features: • • • • • • • • 2 - CPU Low Power differential push-pull pairs 1 - ITP low power differential push-pull pair 4 - SRC low power differential push-pull pairs 1 - LCD100 SSCD low power differential push-pull pair 1 - DOT96 low power differential push-pull pair 3 - PCI, 33MHz 1 - USB, 48MHz 1 - REF, 14.31818MHz Pin Configuration CK_PWRGD#/PD VDDCPUPLL_3.3 CPUITPC_LPRS CPUITPT_LPRS CPU0C_LPRS CPU1C_LPRS CPU0T_LPRS CPU1T_LPRS CPU_STOP# VDDIO_CPU GNDCPU GNDREF FSLC 56 55 54 53 52 51 50 49 48 47 46 45 44 43 X2 X1 VDDREFIO_3.3 REF0 1 2 3 4 SDATA 5 SCLK 6 TEST_SEL 7 TEST_MODE 8 PCI_STOP# 9 VDDIO_PCI3.3 10 PCI0 11 PCI1 12 PCI_F2 13 GNDPCI 14 GND48 VDD48IO_3.3 USB_48MHz 42 41 40 39 38 CLKREQ2# CLKREQ3# VDDCORE_3.3 SRC3T_LPRS SRC3C_LPRS SRC2T_LPRS SRC2C_LPRS VDDIO_SRC GNDSRC SRC1T_LPRS SRC1C_LPRS SRC0T_LPRS SRC0C_LPRS CKLREQ0# FSLB 37 36 35 34 33 32 31 30 29 CLKREQ1# ICS9UMS9001 15 16 17 18 19 20 21 22 23 24 25 26 27 28 VDDIO_LCD GND GND VDDLCDPLL_3.3 VDD48PLL_3.3 DOT96C_LPRS DOT96T_LPRS LCD100C_LPRS LCD100T_LPRS VDDIO_96Mhz 56-pin MLF IDT PC MAIN CLOCK - CK540 ® 1247B—07/19/10 1 9UMS9001 PC MAIN CLOCK - CK540 Advance Information Pin Description PIN # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 X2 X1 VDDREFIO_3.3 REF0 SDATA SCLK TEST_SEL TEST_MODE PCI_STOP# VDDIO_PCI3.3 PCI0 PCI1 PCI_F2 GNDPCI GND48 USB_48MHz VDD48IO_3.3 VDD48PLL_3.3 VDDIO_96Mhz DOT96C_LPRS DOT96T_LPRS GND GND LCD100C_LPRS LCD100T_LPRS VDDIO_LCD VDDLCDPLL_3.3 CLKREQ1# PIN NAME TYPE OUT Crystal output, nominally 14.318MHz. IN Crystal input, Nominally 14.318MHz. DESCRIPTION PWR Power pin for the REF output and crystal oscillator. 3.3V nominal. OUT 3.3V 14.318MHz reference clock I/O IN IN IN IN Data pin for SMBus circuitry, 5V tolerant. Clock pin of SMBus circuitry, 5V tolerant. 3.3V input that puts the part in test mode. This is a realtime input. See the Test Clarification Table for details. When Test mode is selected, this chooses either hi-Z or REF/N for the outputs. 3.3V tolerant input that stops all PCI and SRC clocks, except those set to be free running. PWR 3.3V power supply for the PCI outputs OUT 3.3V PCI clock output. OUT 3.3V PCI clock output. OUT Free running 3.3V PCI clock output PWR Ground for PCI output clocks. PWR Ground for the USB clock. OUT Fixed 3.3V 48MHz USB clock output PWR 3.3V Power supply for the 48MHz output PWR 3.3V Power supply for the 48/96MHz PLL PWR Power supply for DOT96 output. VDD_IO = 1.05 to 3.3V +/-5%. Complement side of low-power CK505-type 96MHz differential clock. Rs is integrated (No external OUT series resistor required). True side of low-power CK505-type 96MHz differential clock. Rs is integrated (No external series OUT resistor required). PWR Ground for 96MHz output PWR Ground for LCD 100 MHz output. OUT OUT Complement side of low-power CK505-type LCD100MHz spreading differential clock. Rs is integrated (No external series resistor required). True side of low-power CK505-type LCD100MHz spreading differential clock. Rs is integrated (No external series resistor required). PWR Power supply for LCD100 output. VDD_IO = 1.05 to 3.3V +/-5%. PWR 3.3V Power supply for the LCD100 Spreading PLL IN Clock request input for SRC output pair 1. See the SRC, LCD, DOT Power Management Table for details IDT® PC MAIN CLOCK - CK540 1247B—07/19/10 2 9UMS9001 PC MAIN CLOCK - CK540 Advance Information Pin Description (continued) PIN # 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 PIN NAME CKLREQ0# SRC0C_LPRS SRC0T_LPRS SRC1C_LPRS SRC1T_LPRS GNDSRC VDDIO_SRC SRC2C_LPRS SRC2T_LPRS SRC3C_LPRS SRC3T_LPRS VDDCORE_3.3 CLKREQ3# CLKREQ2# FSLB CPU_STOP# CPUITPC_LPRS CPUITPT_LPRS CPU1C_LPRS CPU1T_LPRS VDDIO_CPU GNDCPU CPU0C_LPRS CPU0T_LPRS VDDCPUPLL_3.3 CK_PWRGD#/PD TYPE IN OUT OUT OUT OUT PWR DESCRIPTION Clock request input for SRC output pair 0. See the SRC, LCD, DOT Power Management Table for details Complement side of low-power CK505-type SRC0 differential clock. Rs is integrated (No external series resistor required). True side of low-power CK505-type SRC0 differential clock. Rs is integrated (No external series resistor required). Complement side of low-power CK505-type SRC1 differential clock. Rs is integrated (No external series resistor required). True side of low-power CK505-type SRC1 differential clock. Rs is integrated (No external series resistor required). Ground for SRC clocks PWR Power supply for SRC outputs. VDD_IO = 1.05 to 3.3V +/-5%. Complement side of low-power CK505-type SRC2 differential clock. Rs is integrated (No external OUT series resistor required). True side of low-power CK505-type SRC2 differential clock. Rs is integrated (No external series OUT resistor required). Complement side of low-power CK505-type SRC3 differential clock. Rs is integrated (No external OUT series resistor required). True side of low-power CK505-type SRC3 differential clock. Rs is integrated (No external series OUT resistor required). PWR 3.3V Power supply for 3.3V core Clock request input for SRC output pair 2. See the SRC, LCD, DOT Power Management Table for IN details Clock request input for SRC output pair 2. See the SRC, LCD, DOT Power Management Table for IN details Low threshold Frequency Select input. See Table 1: CPU Frequency Select Table and the Vih_fs and IN Vil_fs specifications. IN Stops all CPU clocks except those set to be free running. Complement side of low-power CK505-type CPUITP differential clock. Rs is integrated (No external OUT series resistor required). Note that this pin is NOT muxed with an SRC output. True side of low-power CK505-type CPUITP differential clock. Rs is integrated (No external series OUT resistor required). Complement side of low-power CK505-type CPU1 differential clock. Rs is integrated (No external OUT series resistor required). Note that this pin is NOT muxed with an SRC output. True side of low-power CK505-type CPU1 differential clock. Rs is integrated (No external series OUT resistor required). PWR Power supply for CPU outputs. VDD_IO = 1.05 to 3.3V +/-5%. PWR Ground Pin for CPU Outputs Complement side of low-power CK505-type CPU1 differential clock. Rs is integrated (No external OUT series resistor required). Note that this pin is NOT muxed with an SRC output. True side of low-power CK505-type CPU1 differential clock. Rs is integrated (No external series OUT resistor required). PWR 3.3V Power Supply for CPU PLL. Notifies 9UMS9001 to sample latched inputs or enter power down mode. 1 = Power down mode IN Falling Edge = Sample latched inputs 0 = Normal operation Low threshold Frequency Select input. See Table 1: CPU Frequency Select Table and the Vih_fs and IN Vil_fs specifications. PWR Ground pin for crystal oscillator circuit and REF output 55 56 FSLC GNDREF IDT® PC MAIN CLOCK - CK540 1247B—07/19/10 3 9UMS9001 PC MAIN CLOCK - CK540 Advance Information Functional Block Diagram X1 X2 REF OSC PCI CPU/SRC/ PC SS-PLL SRC(3:0) CPU(2:0) LCD SS PLL LCD Fixed EXACT 48MHz FSLC FSLB CKPWRGD#/PD PCI_STOP# CPU_STOP# CLKREQ(3:0)# ITP_EN TESTSEL TESTMODE DOT96MHZ 48MHZ Control Logic Power Groups VDD3.3V 53 53 35 40 26 27 19 17, 18 3 10 Pin Number VDDIO 1.05~3.3V 49 GND 50 CPUCLK Description Low power outputs Analog Master Clock, Analog Low power outputs SRCCLK Analog Low power outputs LCDCLK PLL DOT 96Mhz Low power outputs USB 48 Xtal, REF PCICLK 34 23 22 15 56 14 IDT® PC MAIN CLOCK - CK540 1247B—07/19/10 4 9UMS9001 PC MAIN CLOCK - CK540 Advance Information Table 1: CPU Frequency Select Table FSLC B0b7 0 0 1 1 1 FSLB B0b6 0 1 0 1 1 CPU MHz SRC MHz PCI MHz 33.33 33.33 REF MHz 14.318 14.318 USB MHz 48.00 48.00 DOT MHz 96.00 96.00 133.33 100.00 Reserved 100.00 100.00 200.00 1. FSLC is a low-threshold input.Please see VIL_FS and VIH_FS s pecifications in the Input/Supply/Common Output Parameters Table for correct values. Also refer to the Test Clarification Table. Table 2: LCD Quick Configuration B1b3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 B1b2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 B1b1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 B1b0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Pin 24/25 MHz 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 Spread Comment % 0.25% Down Spread LCDCLK 0.5% Down Spread LCDCLK 1% Down Spread LCDCLK 1.25% Down Spread LCDCLK 1.5% Down Spread LCDCLK 2% Down Spread LCDCLK 2.5% Down Spread LCDCLK 3.0% Down Spread LCDCLK 0.25% Center Spread LCDCLK 0.5% Center Spread LCDCLK 1% Center Spread LCDCLK 1.25% Center Spread LCDCLK 1.5% Center Spread LCDCLK 2% Center Spread LCDCLK 2.5% Center Spread LCDCLK 3.0% Center Spread LCDCLK Table 3: IO_Vout select table B5b2 B5b1 B5b0 IO_Vout 0.3V 0 0 0 0.4V 0 0 1 0.5V 0 1 0 0.6V 0 1 1 0.7V 1 0 0 0.8V 1 0 1 0.9V 1 1 0 1.0V 1 1 1 IDT® PC MAIN CLOCK - CK540 1247B—07/19/10 5 9UMS9001 PC MAIN CLOCK - CK540 Advance Information Absolute Maximum Ratings PARAMETER Maximum Supply Voltage Maximum Supply Voltage Maximum Supply Voltage Maximum Input Voltage Minimum Input Voltage Storage Temperature Input ESD protection SYMBOL VDDxxx_3.3 VDDxxx_1.8 VDDxxx_IO VIH VIL Ts ESD prot CONDITIONS Supply Voltage Supply Voltage Low-Voltage Differential I/O Supply 3.3V LVCMOS Inputs Any Input Human Body Model GND - 0.5 -65 2000 150 MIN MAX 4.6 2.3 3.8 4.6 UNITS Notes V V V V V ° 1,7 1,7 1,7 1,7,8 1,7 1,7 1,7 C V Electrical Characteristics - Input/Supply/Common Output Parameters PARAMETER Ambient Operating Temp Supply Voltage Supply Voltage Supply Voltage Input High Voltage Input Low Voltage Input Leakage Current Input Leakage Current Output High Voltage Output Low Voltage Output High Voltage Output Low Voltage Low Threshold InputHigh Voltage (Test Mode) Low Threshold InputHigh Voltage Low Threshold InputLow Voltage Operating Supply Current SYMBOL Tambient VDDxxx_3.3 VDDxxx_1.8 VDDxxx_IO VIHSE VILSE IIN IINRES VOHSE VOLSE VOHDIF VOLDIF VIH_FS_TEST VIH_FS VIL_FS IDD_DEFAULT IDD_LCDEN IDD_IO IDD_PD3.3 Power Down Current Input Frequency Pin Inductance Input Capacitance Spread Spectrum Modulation Frequency IDD_PDIO Fi Lpin CIN COUT CINX fSSMOD Logic Inputs Output pin capacitance X1 & X2 pins Triangular Modulation 30 1.5 CONDITIONS Supply Voltage Supply Voltage Low-Voltage Differential I/O Supply Single-ended inputs Single-ended inputs VIN = VDD , VIN = G ND Inputs with pull or pull down resistors VIN = VDD , VIN = G ND Single-ended outputs, IOH = - 1mA Single-ended outputs, IOL = 1 mA Differential Outputs Differential Outputs 3.3 V +/-5% 3.3 V +/-5% 3.3 V +/-5% 3.3V supply, LCDPLL off 3.3V supply, LCDPLL enabled 0.8V supply, Differential IO current, all outputs enabled 3.3V supply, Power Down Mode 0.8V IO supply, Power Down Mode VDD = 3.3 V 2 0.7 VSS - 0.3 0.7 MIN 0 3.135 1.71 1.05 2 VSS - 0.3 -5 -200 2.4 0.4 0.9 0.4 VDD + 0.3 1.5 0.35 80 100 25 1 0.1 15 7 5 6 7 33 MAX 70 3.465 1.89 3.465 VDD + 0.3 0.8 5 200 UNITS Notes °C V V V V V uA uA V V V V V V V mA mA mA mA mA MHz nH pF pF pF kHz 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 1 1 1 1 1 IDT® PC MAIN CLOCK - CK540 1247B—07/19/10 6 9UMS9001 PC MAIN CLOCK - CK540 Advance Information AC Electrical Characteristics - Input/Common Parameters PARAMETER Clk Stabilization Tdrive_SRC Tdrive_PD# Tdrive_CPU Tfall_PD# Trise_PD# SYMBOL TSTAB TDRSRC TDRPD TDRSRC TFALL TRISE CONDITIONS From VDD Power-Up or deassertion of PD# to 1st clock SRC output enable after PCI_STOP# de-assertion Differential output enable after PD# de-assertion CPU output enable after CPU_STOP# de-assertion Fall/rise time of PD#, PCI_STOP# and CPU_STOP# inputs MIN MAX 1.8 15 300 10 5 5 UNITS Notes ms ns us ns ns ns 1 1 1 1 1 1 AC Electrical Characteristics - Low Power Differential Outputs PARAMETER Rising Edge Slew Rate Falling Edge Slew Rate Rise/Fall Time Variation Maximum Output Voltage Minimum Output Voltage Differential Voltage Swing Crossing Point Voltage Crossing Point Variation Duty Cycle CPU Jitter - Cycle to Cycle SRC Jitter - Cycle to Cycle DOT Jitter - Cycle to Cycle CPU[1:0] Skew CPU[2_ITP:0] Skew SRC[3:0] Skew SYMBOL tSLR tFLR tSLVAR VHIGH VLOW VSWING VXABS VXABSVAR DCYC CPUJ C2C SRCJ C2C DOTJ C2C CPUSKEW10 CPUSKEW20 SRCSKEW CONDITIONS Differential Measurement Differential Measurement Single-ended Measurement Includes overshoot Includes undershoot Differential Measurement Single-ended Measurement Single-ended Measurement Differential Measurement Differential Measurement Differential Measurement Differential Measurement Differential Measurement Differential Measurement Differential Measurement 45 -300 300 300 550 140 55 85 125 250 100 150 250 MIN 1 1 MAX 4 4 125 1150 UNITS NOTES V/ns V/ns ps mV mV mV mV mV % ps ps ps ps ps ps 1,2 1,2 1 1 1 1 1,3,4 1,3,5 1 1 1 1 1 1 1 Electrical Characteristics - PCICLK/PCICLK_F PARAMETER Long Accuracy Clock period Absolute min/max period Output High Voltage Output Low Voltage Output High Current Output Low Current Rising Edge Slew Rate Falling Edge Slew Rate Duty Cycle Skew Intentional PCI-PCI delay Jitter, Cycle to cycle IDT® PC MAIN CLOCK - CK540 SYMBOL ppm Tperiod Tabs VOH VOL IOH IOL tSLR tFLR dt1 tskew tdelay tj c y c-c y c CONDITIONS see Tperiod min-max values 33.33MHz output nominal 33.33MHz output spread 33.33MHz output nominal/spread IOH = - 1 mA IOL = 1 mA V OH @MIN = 1.0 V VOH@MAX = 3.135 V VOL @ MIN = 1.95 V VOL @ MAX = 0.4 V Measured from 0.8 to 2.0 V Measured from 2.0 to 0.8 V VT = 1.5 V VT = 1.5 V VT = 1.5 V VT = 1.5 V MIN -300 29.99100 29.49100 2.4 MAX 300 30.00900 30.15980 30.65980 0.4 UNITS NOTES 1,6 ppm ns ns ns V V mA mA mA mA V/ns V/ns % ps ps ps 6 6 6 1 1 1 1 1 1 1 1 1 1 1,9 1 1247B—07/19/10 -33 -33 30 38 1 1 45 0 nominal 500 4 4 55 250 7 9UMS9001 PC MAIN CLOCK - CK540 Advance Information Electrical Characteristics - USB48MHz PARAMETER Long Accuracy Clock period Absolute min/max period Output High Voltage Output Low Voltage Output High Current Output Low Current Rising Edge Slew Rate Falling Edge Slew Rate Duty Cycle Jitter, Cycle to cycle SYMBOL ppm Tperiod Tabs VOH VOL IOH IOL tSLR tFLR dt1 tj c y c-c y c CONDITIONS see Tperiod min-max values 48.00MHz output nominal 48.00MHz output nominal IOH = - 1 mA IOL = 1 mA V OH @MIN = 1.0 V VOH@MAX = 3.135 V VOL @ MIN = 1.95 V VOL @ MAX = 0.4 V Measured from 0.8 to 2.0 V Measured from 2.0 to 0.8 V VT = 1.5 V VT = 1.5 V 1 1 45 29 27 2 2 55 350 -29 -23 MIN -100 20.83125 20.48130 2.4 0.4 MAX 100 20.83542 21.18540 UNITS NOTES ppm 1,2 ns ns V V mA mA mA mA V/ns V/ns % ps 2 2 1 1 1 1 1 1 1 1 1 1 Electrical Characteristics - SMBus Interface PARAMETER SMBus Voltage Low-level Output Voltage Current sinking at VOLSMB = 0.4 V SCLK/SDATA Clock/Data Rise Time SCLK/SDATA Clock/Data Fall Time Maximum SMBus Operating Frequency SYMBOL VDD VOLSMB IPULLUP TRI2C TFI2C FSMBUS @ IPULLUP SMB Data Pin (Max VIL - 0.15) to (Min VIH + 0.15) (Min VIH + 0.15) to (Max VIL - 0.15) Block Mode 4 1000 300 100 CONDITIONS MIN 2.7 MAX 5.5 0.4 UNITS Notes V V mA ns ns kHz 1 1 1 1 1 1 IDT® PC MAIN CLOCK - CK540 1247B—07/19/10 8 9UMS9001 PC MAIN CLOCK - CK540 Advance Information Electrical Characteristics - REF-14.318MHz PARAMETER Long Accuracy Clock period Absolute min/max period Output High Voltage Output Low Voltage Output High Current Output Low Current Rising Edge Slew Rate Falling Edge Slew Rate Duty Cycle Jitter SYMBOL ppm Tperiod Tabs VOH VOL IOH IOL tSLR tFLR dt1 tjcyc-cyc CONDITIONS see Tperiod min-max values 14.318MHz output nominal 14.318MHz output nominal IOH = - 1 mA IOL = 1 mA VOH @MIN = 1.0 V, VOH@MAX = 3.135 V VOL @MIN = 1.95 V, VOL @MAX = 0.4 V Measured from 0.8 to 2.0 V Measured from 2.0 to 0.8 V VT = 1.5 V VT = 1.5 V -33 30 1 1 45 MIN -300 69.8203 69.8203 2.4 0.4 -33 38 4 4 55 1000 MAX 300 69.8622 70.86224 UNITS Notes ppm ns ns V V mA mA V/ns V/ns % ps 1,2 2 2 1 1 1 1 1 1 1 1 Notes on Electrical Characteristics: 1 2 3 4 5 Guaranteed by design and characterization, not 100% tested in production. Slew rate measured through Vswing centered around differential zero Vxabs is defined as the voltage where CLK = CLK# O nly applies to the differential rising edge (CLK rising and CLK# falling) Defined as the total variation of all crossing voltages of CLK rising and CLK# falling. Matching applies to rising edge rate of CLK and falling edge of CLK#. It is measured using a +/-75mV window centered on the average cross point where CLK meets CLK#. The average cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate c alculations 6 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz 7 8 9 O peration under these conditions is neither implied, nor guaranteed. Maximum input voltage is not to exceed maximum VDD See PCI Clock-to-Clock Delay Figure IDT® PC MAIN CLOCK - CK540 1247B—07/19/10 9 9UMS9001 PC MAIN CLOCK - CK540 Advance Information General I2C serial interface information for the 9UMS9001 How to Write: Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the beginning byte location = N ICS clock will acknowledge Controller (host) sends the data byte count = X ICS clock will acknowledge Controller (host) starts sending Byte N through Byte N + X -1 (see Note 2) • ICS clock will acknowledge each byte one at a time • Controller (host) sends a Stop bit • • • • • • • • How to Read: • • • • • • • • • • • • • • Controller (host) will send start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) will send a separate start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the data byte count = X ICS clock sends Byte N + X -1 ICS clock sends Byte 0 through byte X (if X(H) was written to byte 8). Controller (host) will need to acknowledge each byte Controller (host) will send a not acknowledge bit Controller (host) will send a stop bit Index Block Write Operation Controller (Host) starT bit T Slave Address D2(H) WR WRite Beginning Byte = N ACK Data Byte Count = X ACK Beginning Byte N ACK X Byte ICS (Slave/Receiver) Index Block Read Operation Controller (Host) T starT bit Slave Address D2(H) WR WRite Beginning Byte = N ACK RT Repeat starT Slave Address D3(H) RD ReaD ACK Data Byte Count = X ACK Beginning Byte N ACK X Byte ICS (Slave/Receiver) ACK ACK Byte N + X - 1 ACK P stoP bit Byte N + X - 1 N P Not acknowledge stoP bit IDT® PC MAIN CLOCK - CK540 1247B—07/19/10 10 9UMS9001 PC MAIN CLOCK - CK540 Advance Information Byte 0 FS Readback, SS Enable, STOP Control Register Bit 7 6 5 4 3 2 1 0 Pin Name FSLC FSLB CPU_SS_EN LCD_Enable SRC3_STOP SRC2_STOP SRC1_STOP SRC0_STOP Description CPU Freq. Sel. Bit MSB CPU Freq. Sel. Bit LSB Spread spectrum enable for CPU/SRC/PCI outputs Turns On LCD PLL SRC 3 Stop Control SRC 2 Stop Control SRC 1 Stop Control SRC 0 Stop Control Type RW RW RW RW RW RW RW RW 0 1 See Frequency Select Table SS Disabled Off Free Running SS Enabled On Stops with PCI_STOP# Assertion Default Latch Latch 1 1 0 0 0 0 Byte 1 LCD Quick Config and CPU Stop ControlRegister Bit 7 6 5 4 3 2 1 0 Pin Name CPU_ITP_STOP CPU1_STOP CPU0_STOP LCD_SS_EN LCD_SSC_SEL LCD_CF2 LCD_CF1 LCD_CF0 Description CPU_ITP Stop Control CPU1 Stop Control CPU0 Stop Control Turns on SS for LCD PLL Select down or center SSC PLL3 Quick Config Bit 2 PLL3 Quick Config Bit 1 PLL3 Quick Config Bit 0 Type RW RW RW RW RW RW RW RW 0 Free Running Off Down spread 1 Stops with CPU_STOP# assertion On Center spread Default 0 1 1 1 0 0 0 1 See Table 2: LCD Quick Configuration Byte 2 Output Enable and Stop Control Register Bit 7 6 5 4 3 2 1 0 Pin Name PCI_F2_STOP PCI1_STOP PCI0_STOP REF_OE USB_OE PCIF2_OE PCI1_OE PCI0_OE Description Free running PCI Stop Control PCI1 Stop Control PCI 0 Stop Control Output enable for REF Output enable for USB Output enable for PCI2 Output enable for PCI1 Output enable for PCI0 Type RW RW RW RW RW RW RW RW 0 Free Running Output Output Output Output Output Disabled Disabled Disabled Disabled Disabled 1 Stops with PCI_STOP# assertion Output Enabled Output Enabled Output Enabled Output Enabled Output Enabled Default 0 1 1 1 1 1 1 1 Byte 3 Output Enable Register Bit 7 6 5 4 3 2 1 0 Pin Name CPU_ITP_OE CPU1_OE CPU0_OE Reserved SRC3_OE SRC2_OE SRC1_OE SRC0_OE Description Output enable for CPU_ITP Output enable for CPU1 Output enable for CPU0 Reserved Output enable for SRC4 Output enable for SRC4 Output enable for SRC4 Output enable for SRC4 Type RW RW RW RW RW RW RW RW 0 Output Disabled Output Disabled Output Disabled Output Output Output Output Disabled Disabled Disabled Disabled 1 Output Enabled Output Enabled Output Enabled Output Output Output Output Enabled Enabled Enabled Enabled Default 1 1 1 0 1 1 1 1 Byte 4 Output Enable and CLKREQ# Control Register Bit 7 6 5 4 3 2 1 0 Pin Name DOT96_OE LCD100_OE Reserved Reserved SRC3_CR SRC2_CR SRC1_CR SRC0_CR Description Output enable for DOT96 Output enable for LCD100 Reserved Reserved SRC3 CLKREQ3# Enable SRC2 CLKREQ2# Enable SRC1 CLKREQ1# Enable SRC0 CLKREQ0# Enable Type RW RW RW RW RW RW RW RW 0 Output Disabled Output Disabled 1 Output Enabled Output Enabled Default 1 1 0 0 0 0 0 0 Not controlled by CLKREQ# Controlled by CLKREQ# IDT® PC MAIN CLOCK - CK540 1247B—07/19/10 11 9UMS9001 PC MAIN CLOCK - CK540 Advance Information Byte 5 Drive Strength Control Register Bit 7 6 5 4 3 2 1 0 Pin Name PCI_F2 Strength PCI1 Strength PCI0 Strength 48MHz Strength REF Strength IO_VOUT2 IO_VOUT1 IO_VOUT0 Description Sets the PCI_F2 output drive strength Sets the PCI1 output drive strength Sets the PCI0 output drive strength Sets the 48MHz output drive strength Sets the REF output drive strength IO Output Voltage Select (Most Significant Bit) IO Output Voltage Select IO Output Voltage Select (Least Significant Bit) Type RW RW RW RW RW RW RW RW 0 1 Load 2 Loads 1 2 Loads 3 Loads Default 1 1 1 1 1 1 0 1 See Table 3: V_IO Selection (Default is 0.8V) Byte 6 Reserved Register Bit 7 6 5 4 3 2 1 0 Pin Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Description Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Type RW RW RW RW RW RW RW RW 0 1 Default 0 0 0 0 0 0 0 0 Byte 7 Vendor ID/ Revision ID Bit 7 6 5 4 3 2 1 0 Pin Name Rev Code Bit Rev Code Bit Rev Code Bit Rev Code Bit Vendor ID bit Vendor ID bit Vendor ID bit Vendor ID bit Description 3 2 1 0 3 2 1 0 Revision ID Type R R R R R R R R 0 1 Default X X X X 0 0 0 1 Vendor specific Vendor ID ICS is 0001, binary Byte 8 Device ID Register Bit 7 6 5 4 3 2 1 0 Pin Name Device_ID3 Device_ID2 Device_ID1 Device_ID0 Reserved Reserved Reserved Reserved Description Package ID code Reserved Reserved Reserved Reserved Type R R R R RW RW RW RW 0 1 Devide ID = 0011 Hex 56-pin QFN Default 0 0 1 1 0 0 0 1 Byte 9 Test Mode Register Bit 7 6 5 4 3 2 1 0 Pin Name LCD_STOP Reserved Reserved Test Mode Select Test Mode Entry Reserved Reserved PLL1_SS Description LCD Stop Control Reserved Reserved Allows test select, ignores Test Sel input pin Enters into test mode, ignores input pin Reserved Reserved PLL1 Spread Spectrum Mode Type RW RW RW RW RW RW RW RW 0 Free Running 1 Stops with PCI_STOP# assertion Default 0 0 0 0 0 0 0 0 Outputs HI-Z Normal operation Outputs = REF/N Test mode Down-spread Center-spread IDT® PC MAIN CLOCK - CK540 1247B—07/19/10 12 9UMS9001 PC MAIN CLOCK - CK540 Advance Information Test Clarification Table Comments HW SW REF/N or HI-Z B9b4 TEST TEST_MODE ENTRY BIT HW PIN B9b3 TEST_SEL HW PIN Power-up w/ TEST_SEL = 1 to enter test mode Cycle power to disable test mode TEST_MODE -->low Vth input TEST_MODE is a real time input 2.0V >2.0V >2.0V X 0 0 1 0 X X X 0 0 1 0 OUTPUT NORMAL HI-Z REF/N REF/N >2.0V 1 X 1 REF/N