54AC00

Semiconductor CD54AC00F3A, CD54ACT00F3A Quad 2-Input NAND Gate Description The CD54AC00F3A and CD54ACT00F3A are quad 2-input NAND gates that utilize the Harris Advanced CMOS Logic technology. July 1998 Features • This Circuit is Processed in Accordance to MIL-STD883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1. • Exceeds 2kV ESD Protection MIL-STD-883, Method 3015 • Meets JEDEC Standard No. 20 • SCR - Latch-Up-Resistant CMOS Process and Circuit Design • Speed of Bipolar FAST/A/S with Significantly Reduced Power Consumption • Functionally and Pin-Compatible with Industry 54 Bipolar Types in the FAST, AS and S Series • Balanced Propagation Delays • Military Operating Temperature Range - Ceramic (CERDIP) 54 Series: . . . . . . . . -55 to 125oC • ±24mA Output Drive Current, Drives 75Ω Lines without Need for Terminations • Fan Out (Over Temperature) - ACL Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2400 - FAST Loads. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 - AS Loads. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 • Balanced Noise Immunity at 30% of Supply for AC Types • Supply Voltage Range - AC Types . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5V to 5.5V - ACT Types . . . . . . . . . . . . . . . . . . . . . . . . . 4.5V to 5.5V Ordering Information PART NUMBER CD54AC00F3A CD54ACT00F3A NOTE: 1. Wafer and die for this part number is available which meets all electrical specifications. Please contact your local sales office or Harris customer service for ordering information. TEMP. RANGE (oC) -55 to 125 -55 to 125 PACKAGE 14 Ld CERDIP 14 Ld CERDIP PKG. NO. F14.3 F14.3 Functional Diagram 1A 1B 2A 2B 3B 3A 4B 4A 1 2 4 5 9 10 12 13 11 3 6 8 3Y 4Y 1Y 2Y GND = 7 VCC = 14 TRUTH TABLE Pinout A 1A 1 1B 2 1Y 3 2A 4 2B 5 2Y 6 GND 7 14 VCC 13 4A 12 4B 11 4Y 10 3A 9 3B 8 3Y INPUTS B L L H H OUTPUTS Y H H H L L H L H CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © Harris Corporation 1998 File Number 3876.1 1 CD54AC00F3A, CD54ACT00F3A Absolute Maximum Ratings DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 6V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . ±50mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . . ±50mA DC VCC or Ground Current, ICC or IGND (Note 2) . . . . . . . . . ±100mA Thermal Information Thermal Resistance (Typical, Note 4) θJA (oC/W) θJC (oC/W) CERDIP Package . . . . . . . . . . . . . . . . 80 24 Maximum Junction Temperature (Hermetic Package or Die) . . . 175oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC Operating Conditions Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC (Note 3) AC Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.5V to 5.5V ACT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Slew Rate, dt/dv AC Types 1.5V to 3V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50ns (Max) 3.6V to 5.5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20ns (Max) 4.5V to 5.5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10ns (Max) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 2. For up to 4 outputs per device, add ±25mA for each additional output. 3. Unless otherwise specified, all voltages are referenced to ground. 4. θJA is measured with the component mounted on an evaluation PC board in free air. DC Electrical Specifications TEST CONDITIONS PARAMETER AC TYPES High Level Input Voltage VIH 1.5 3 4.5 5.5 Low Level Input Voltage VIL 1.5 3 4.5 5.5 High Level Output Voltage VOH VIH or VIL -0.05 -0.05 -0.05 -4 -24 -50 (Note 6, 7) 1.5 3 4.5 3 4.5 5.5 1.2 2.1 3.15 (Note 5) 3.85 1.4 2.9 4.4 2.58 3.94 (Note 5) 0.3 0.9 1.35 (Note 5) 1.65 1.2 2.1 3.15 (Note 5) 3.85 1.4 2.9 4.4 2.4 3.7 (Note 5) 3.85 0.3 0.9 1.35 (Note 5) 1.65 V V V V V V V V V V V V V V SYMBOL VI (V) IO (mA) VCC (V) 25oC MIN MAX -55oC TO 125oC MIN MAX UNITS 2 CD54AC00F3A, CD54ACT00F3A DC Electrical Specifications (Continued) TEST CONDITIONS PARAMETER Low Level Output Voltage SYMBOL VOL VI (V) VIH or VIL IO (mA) 0.05 0.05 0.05 12 24 50 (Note 6, 7) Input Leakage Current Quiescent Device Current ACT TYPES High Level Input Voltage Low Level Input Voltage High Level Output Voltage VIH VIL VOH VIH or VIL -0.05 -24 -50 (Note 6, 7) Low Level Output Voltage VOL VIH or VIL 0.05 24 50 (Note 6, 7) Input Leakage Current Quiescent Device Current Additional Supply Current per Input Pin TTL Inputs High 1 Unit Load NOTES: 5. Tested at 100%. 6. Test one output at a time for a 1-second maximum duration. Measurement is made by forcing current and measuring voltage to minimize power dissipation. 7. Test verifies a minimum transmission-line-drive capability of 75Ω for 54AC/ACT Series. II ICC ∆ICC VCC or GND VCC or GND VCC -2.1 0 4.5 to 5.5 4.5 to 5.5 4.5 4.5 5.5 4.5 4.5 5.5 5.5 5.5 4.5 to 5.5 2 (Note 5) 4.4 3.94 (Note 5) 0.8 (Note 5) 0.1 0.36 (Note 5) ±0.1 (Note 5) 4 (Note 5) 2.4 2 (Note 5) 4.4 3.7 (Note 5) 3.85 0.8 (Note 5) 0.1 0.5 (Note 5) 1.65 ±1 (Note 5) 80 (Note 5) 3 V V V V V V V V µA µA mA II ICC VCC or GND 0 25oC MIN MAX 0.1 0.1 0.1 0.36 0.36 (Note 5) ±0.1 (Note 5) 4 (Note 5) -55oC TO 125oC MIN MAX 0.1 0.1 0.1 0.5 0.5 (Note 5) 1.65 ±1 (Note 5) 80 (Note 5) UNITS V V V V V V µA µA VCC (V) 1.5 3 4.5 3 4.5 5.5 5.5 5.5 ACT Input Load Table INPUT All UNIT LOAD 0.15 NOTE: Unit load is ∆ICC limit specified in DC Electrical Specifications Table, e.g., 2.4mA max at 25oC. 3 CD54AC00F3A, CD54ACT00F3A Switching Specifications Input tr, tf = 3ns, CL = 50pF (Worst Case) -55oC TO 125oC PARAMETER AC TYPES Propagation Delay, Input to Output tPLH, tPHL 1.5 3.3 (Note 9) 5 (Note 10) Input Capacitance Power Dissipation Capacitance ACT TYPES Propagation Delay, Input to Output tPLH tPHL Input Capacitance Power Dissipation Capacitance NOTES: 8. Limits tested at 100%. 9. 3.3V Min at 3.6V, Max at 3V. 10. 5V Min at 5.5V, Max at 4.5V 11. CPD is used to determine the dynamic power consumption per gate. AC: PD = VCC2 fi (CPD + CL) ACT: PD = VCC2 fi (CPD + CL) + VCC ∆ICC where fi = input frequency, CL = output load capacitance, VCC = supply voltage. CI CPD (Note 11) 5 (Note 10) 3.2 4 45 10.8 (Note 8) 13.2 (Note 8) 10 ns ns pF pF CI CPD (Note 11) 3.1 2.2 45 91 10.2 7.3 (Note 8) 10 ns ns ns pF pF SYMBOL VCC (V) MIN TYP MAX UNITS Burn-In Test Circuit Connections (Use DC II for F3A Burn-In and AC for Life Test) DC BURN-IN I DC CD54AC/ACT00 OPEN 3, 6, 8, 11 GROUND 1, 2, 4, 5, 7, 9, 10, 12, 13 VCC (6V) 14 OPEN 3, 6, 8, 11 DC BURN-IN II GROUND 7 VCC (6V) 1, 2, 4, 5, 9, 10, 12 - 14 OSCILLATOR AC CD54AC/ACT00 OPEN GROUND 7 1/2 VCC (3V) 3, 6, 8, 11 VCC (6V) 14 50kHz 1, 2, 4, 5, 9, 10, 12, 13 25kHz - NOTE: Each pin except VCC and Gnd will have a resistor of 2kΩ-47kΩ . tr = 3ns RL (NOTE) 500Ω DUT OUTPUT LOAD CL 50pF INPUT LEVEL VI VO VS tf = 3ns 90% VS 10% GND OUTPUT NOTE: For AC Series Only: When VCC = 1.5V, RL = 1kΩ. tPHL tPLH CD54AC Input Level Input Switching Voltage, VS Output Switching Voltage, VS VCC 0.5 VCC 0.5 VCC CD54ACT 3V 1.5V 0.5 VCC FIGURE 2. WAVEFORMS FIGURE 1. PROPAGATION DELAY TIMES 4